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PCA9544A-PCA9544ABS-PCA9544AD-PCA9544APW
PCA9544A; 4-channel I²C multiplexer with interrupt logic
2004 Sep 29
Product data sheet
Supersedes data of 2004 Jul 28
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
FEATURES 1-of-4 bi-directional translating multiplexer I2C interface logic; compatible with SMBus 4 Active-LOW Interrupt Inputs Active-LOW Interrupt Output 3 address pins allowing up to 8 devices on the I2C-bus Channel selection via I2C-bus Power-up with all multiplexer channels deselected Low RdsON switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses No glitch on power-up Supports hot insertion Low stand-by current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant Inputs 0 to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V per JESD22-C101 Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA Three packages offered: SO20, TSSOP20, and HVQFN20
DESCRIPTIONThe PCA9544A is a 1-of-4 bi-directional translating multiplexer,
controlled via the I2 C-bus. The SCL/SDA upstream pair fans out to
four SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, INT0 to INT3,
one for each of the SCx/SDx downstream pairs, are provided. One
interrupt output, INT, which acts as an AND of the four interrupt
inputs, is provided.
A power-on reset function puts the registers in their default state and
initializes the I2C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9544A. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
ORDERING INFORMATIONStandard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.2 C is a trademark of Philips Semiconductors Corporation.
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
PIN CONFIGURATION — SO, TSSOP
Figure 1. Pin configuration — SO, TSSOP
PIN CONFIGURATION — HVQFN
Figure 2. Pin configuration — HVQFN
PIN DESCRIPTION
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
BLOCK DIAGRAM
Figure 3. Block diagram
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
DEVICE ADDRESSINGFollowing a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9544A
is shown in Figure 4. To conserve power, no internal pull-up
resistors are incorporated on the hardware selectable address pins
and they must be pulled HIGH or LOW.
Figure 4. Slave addressThe last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTERFollowing the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9544A which will be
stored in the Control Register. If multiple bytes are received by the
PCA9544A, it will save the last byte received. This register can be
written and read via the I2 C-bus.
Figure 5. Control register
CONTROL REGISTER DEFINITIONA SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9544A
has been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a stop condition has been placed
on the I2C-bus. This ensures that all SCx/SDx lines will be in a
HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
INTERRUPT HANDLINGThe PCA9544A provides 4 interrupt inputs, one for each channel
and one open drain interrupt output. When an interrupt is generated by
any device, it will be detected by the PCA9544A and the interrupt
output will be driven LOW. The channel need not be active for
detection of the interrupt. A bit is also set in the control byte.
Bits 4 – 7 of the control byte correspond to channels 0 – 3 of the
PCA9544A, respectively. Therefore, if an interrupt is generated by
any device connected to channel 2, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9544A and read the contents of the
control byte to determine which channel contains the device
generating the interrupt. The master can then reconfigure the
PCA9544A to select this channel, and locate the device generating
the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to VDD through a
pull-up resistor.
Table 2. Control Register Read — Interrupt
NOTE: Several interrupts can be active at the same time. Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
POWER-ON RESETWhen power is applied to VDD, an internal Power On Reset holds
the PCA9544A in a reset condition until VDD has reached VPOR. At
this point, the reset condition is released and the PCA9544A
registers and I2 C state machine are initialized to their default states,
all zeroes causing all the channels to be deselected. Thereafter,
VDD must be lowered below 0.2 V to reset the device.
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
VOLTAGE TRANSLATIONThe pass gate transistors of the PCA9544A are constructed such
that the VDD voltage can be used to limit the maximum voltage that
will be passed from one I2 C-bus to another.
Figure 6. Vpass voltageFigure 6 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9544A to act as a voltage translator, the Vpass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then Vpass should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 6, we see that Vpass (max.) will be at 2.7 V when the
PCA9544A supply voltage is 3.5 V or lower so the PCA9544A
supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see
Figure 13).
More Information can be found in Application Note AN262 PCA954X
family of I2C/SMBus multiplexers and switches.
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
CHARACTERISTICS OF THE I2 C-BUSThe I2 C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transferOne data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 7).
Figure 7. Bit transfer
Start and stop conditionsBoth data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 8).
System configurationA device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 9).
Figure 8. Definition of start and stop conditions
Figure 9. System configuration
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
AcknowledgeThe number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Figure 10. Acknowledgement on the I2C-bus
Figure 11. WRITE control register
Figure 12. READ control register
Philips Semiconductors Product data sheet
PCA9544A4-channel I2 C multiplexer with interrupt logic
TYPICAL APPLICATION
Figure 13. Typical application
