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PCA9543AD-PCA9543APW-PCA9543BPW-PCA9543CPW
2-channel I虏C-bus switch with interrupt logic and reset
1. General descriptionThe PCA9543A/43B is a bidirectional translating switch, controlled by the I2 C-bus. The
SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual
SCx/SDx channels or combination of channels can be selected, determined by the
contents of the programmable control register. Two interrupt inputs, INT0 and INT1, one
for each of the downstream pairs, are provided. One interrupt output, INT, which acts as
an AND of the two interrupt inputs, is provided.
An active LOW reset input allows the PCA9543X to recover from a situation where one of
the downstream I2 C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2 C-bus state machine and causes all the channels to be deselected, as does the
internal power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which will be passed by the PCA9543X. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9543A and PCA9543B are identical except for the fixed portion of the slave
address.
2. Features and benefits 1-of-2 bidirectional translating switchesI2 C-bus interface logic; compatible with SMBus standards 2 active LOW interrupt inputs Active LOW interrupt output Active LOW reset input 2 address pins allowing up to 4 devices on the I2 C-bus Alternate address versions A and B allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts Channel selection via I2 C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V
PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
Rev. 8 — 3 April 2014 Product data sheet
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset5 V tolerant inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO14, TSSOP14
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Table 2. Ordering options
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
4. Block diagramNXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 3. Pin description
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
6. Functional descriptionRefer to Figure 1 “Block diagram of PCA9543A/43B”.
6.1 Device addressFollowing a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9543A/43B is shown in Figure 4. To conserve power,
no internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B is an alternate address version, if needed for larger systems or to resolve
address conflicts. The data sheet will reference the PCA9543A, but the PCA9543B
functions identically except for the slave address.
6.1.1 Address maps
Table 4. PCA9543A address map
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
6.2 Control registerFollowing the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A/43B, which will be stored in the control register. If multiple bytes
are received by the PCA9543A/43B, it will save the last byte received. This register can
be written and read via the I2 C-bus.
6.2.1 Control register definitionOne or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9543A/43B has been addressed. The LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I2 C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1
indicate the state of the corresponding interrupt input. D7 and D6 always read 0.
See Section 6.2.2.
Table 5. PCA9543B address map
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be
taken not to exceed the maximum bus capacitance.
6.2.2 Interrupt handlingThe PCA9543A/43B provides 2 interrupt inputs, one for each channel, and one
open-drain interrupt output. When an interrupt is generated by any device, it will be
detected by the PCA9543A/43B and the interrupt output will be driven LOW. The channel
need not be active for detection of the interrupt. A bit is also set in the control register.
Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the
PCA9543A/43B, respectively. Therefore, if an interrupt is generated by any device
connected to channel 1, the state of the interrupt inputs is loaded into the control register
when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master can
then address the PCA9543A/43B and read the contents of the control register to
determine which channel contains the device generating the interrupt. The master can
then reconfigure the PCA9543A/43B to select this channel, and locate the device
generating the interrupt and clearit.
It should be noted that more than one device can provide an interrupt on a channel, so it is
up to the master to ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Remark: Two interrupts can be active at the same time. D6 and D7 always read 0.
6.3 RESET inputThe RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A/43B will
reset its registers and I2 C-bus state machine and will deselect all channels. The RESET
input must be connected to VDD through a pull-up resistor.
Table 6. Control register: Write — channel selection; Read — channel status
Table 7. Control register: Read — interrupt
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
6.4 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9543A/43B in a reset condition until VDD has reached VPOR. At this point, the reset
condition is released and the PCA9543A/43B registers and I2 C-bus state machine are
initialized to their default states (all zeroes) causing all the channels to be deselected.
Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translationThe pass gate transistors of the PCA9543A/43B are constructed such that the VDD
voltage can be used to limit the maximum voltage that will be passed from one I2 C-bus to
another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data
sheet). In order for the PCA9543A/43B to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A/43B supply voltage
is 3.5 V or lower, so the PCA9543A/43B supply voltage could be set to 3.3 V. Pull-up
resistors can then be used to bring the bus voltages to their appropriate levels (see
Figure 14).
More Information can be found in Application Note AN262: PCA954X family of I2 C/SMBus
multiplexers and switches.
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
7. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
7.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure9).
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
7.3 System configurationA device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
7.4 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
7.5 Bus transactionsData is transmitted to the PCA9543A/43B control register using the Write mode as shown
in Figure 12.
Data is read from PCA9543A/43B using the Read mode as shown in Figure 13.
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
8. Application design-in informationNXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
9. Limiting values[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125C.
10. Thermal characteristics
Table 8. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground=0V).
Table 9. Thermal characteristics
NXP Semiconductors PCA9543A/43B
2-channel I2 C-bus switch with interrupt logic and reset
11. Static characteristics[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 10. Static characteristics at VDD =2.3 V to 3.6VVSS =0V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 11 on page 15 for VDD = 4.5 V to 5.5V.[1]
