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PCA9541PW
2-to-1 I2C-bus master selector with interrupt logic and reset
General descriptionThe PCA9541isa 2-to-1I2 C-bus master selector designedfor high reliability dual master2 C-bus applications where system operation is required, even when one master fails or
the controller card is removed for maintenance. The two masters (for example, primary
and back-up) are located on separate I2 C-buses that connect to the same downstream2 C-bus slave devices.I2 C-bus commands are sentby eitherI2 C-bus master and are used
to select one master at a time. Either master at any time can gain control of the slave
devices if the other master is disabled or removed from the system. The failed master is
isolated from the system and will not affect communication between the on-line master
and the slave devices on the downstream I2 C-bus.
Two versions are offered for different architectures. PCA9541/01 with channel 0 selected
at start-up and PCA9541/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which master has control of the
bus. One interrupt input (INT_IN) collects downstream information and propagates it to
the2 upstreamI2 C-buses (INT0 and INT1)if enabled. INT0 and INT1 are also usedtolet
the previous bus master know that it is not in control of the bus anymore and to indicate
the completion of the bus recovery/initialization sequence. Those interrupts can be
disabled and will not generate an interrupt if the masking option is set. bus recovery/initializationif enabled sends nine clock pulses,a not acknowledge, anda
STOP condition in order to set the downstream I2 C-bus devices to an initialized state
before actually switching the channel to the selected master.
An interrupt is sent to the upstream channel when the recovery/initialization procedure is
completed.
An internal bus sensor senses the downstream I2 C-bus traffic and generates an interrupt
if a channel switch occurs during a non-idle bus condition. This function is enabled when
the PCA9541 recovery/initialization is not used. The interrupt signal informs the master
that an external I2 C-bus recovery/initialization needs to be performed. It can be disabled
and an interrupt will not be generated.
The pass gatesof the switches are constructed such that the VDD pin canbe usedto limit
the maximum high voltage, which will be passed by the PCA9541. This allows the use of
different bus voltageson each pair,so that 1.8V, 2.5V,or 3.3V devices can communicate
with 5 V devices without any additional protection.
The PCA9541 does not isolate the capacitive loading on either side of the device, so the
designer must take into account all trace and device capacitances on both sides of the
device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the busto the desired voltage levelfor each channel.All I/O
pins are 6.0 V tolerant.
PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
Rev. 07 — 2 July 2009 Product data sheet
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and resetAn active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin
LOW resets the I2 C-bus state machine and configures the device to its default state as
does the internal Power-On Reset (POR) function.
Features 2-to-1 bidirectional master selectorI2 C-bus interface logic; compatible with SMBus standards PCA9541/01 powers up with Channel 0 selected PCA9541/03 powersup withno channel selected and either master can take controlof
the bus Active LOW interrupt input 2 active LOW interrupt outputs Active LOW reset input 4 address pins allowing up to 16 devices on the I2 C-bus Channel selection via I2 C-bus Bus initialization/recovery function Bus traffic sensor Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Software identical for both masters Low standby current Operating power supply voltage range of 2.3 V to 5.5V 6.0 V tolerant inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO16, TSSOP16, HVQFN16
Applications High reliability systems with dual masters Gatekeeper multiplexer on long single bus Bus initialization/recovery for slave devices without hardware reset Allows masters without arbitration logic to share resources
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset Ordering information Marking
Table 1. Ordering informationTamb= −40°Cto +85°C
PCA9541D/01 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PCA9541PW/01 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PCA9541BS/01 HVQFN16 plastic thermal enhanced very thin quadflat package;no leads;16 terminals;
body 4×4× 0.85 mm
SOT629-1
PCA9541D/03 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PCA9541PW/03 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PCA9541BS/03 HVQFN16 plastic thermal enhanced very thin quadflat package;no leads;16 terminals;
body 4×4× 0.85 mm
SOT629-1
Table 2. Marking codesPCA9541D/01 PCA9541D/01
PCA9541PW/01 9541/01
PCA9541BS/01 41/1
PCA9541D/03 PCA9541D/03
PCA9541PW/03 9541/03
PCA9541BS/03 41/3
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset Block diagram
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset Pinning information
7.1 Pinning
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
7.2 Pin description[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSSpin mustbe connectedto supply groundfor proper device operation.For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Table 3. Pin descriptionINT0 1 15 active LOW interrupt output 0 (external pull-up required)
SDA_MST0 2 16 serial data master 0 (external pull-up required)
SCL_MST0 3 1 serial clock master 0 (external pull-up required)
RESET 4 2 active LOW reset input (external pull-up required)
SCL_MST1 5 3 serial clock master 1 (external pull-up required)
SDA_MST1 6 4 serial data master 1 (external pull-up required)
INT1 7 5 active LOW interrupt output 1 (external pull-up required)
VSS 86[1] supply ground 9 7 address input 0 (externally held to VSS or VDD) 10 8 address input 1 (externally held to VSS or VDD) 11 9 address input 2 (externally held to VSS or VDD) 12 10 address input 3 (externally held to VSS or VDD)
SCL_SLAVE 13 11 serial clock slave (external pull-up required)
SDA_SLAVE 14 12 serial data slave (external pull-up required)
INT_IN 15 13 active LOW interrupt input (external pull-up required)
VDD 16 14 supply voltage
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset Functional descriptionRefer to Figure 1 “Block diagram of PCA9541”.
8.1 Device addressFollowing a START condition, the upstream master that wants to control the I2 C-bus or
make a status check must send the address of the slave it is accessing. The slave
address of the PCA9541 is shown in Figure 5. To conserve power, no internal pull-up
resistors are incorporatedon the hardware selectable pins and they mustbe pulled HIGH
or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while logic 0 selects a write operation.
Remark: ReservedI2 C-bus addresses mustbe used with caution since they can interfere
with:
‘reserved for future use’ I2 C-bus addresses (1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
8.2 Command CodeFollowing the successful acknowledgementof the slave address, the bus master will send
a byte to the PCA9541, which will be stored in the Command Code register.
The 2 LSBs are used as a pointer to determine which register will be accessed.
If the auto-increment flag is set (AI= 1), the two least significant bits of the Command
Code are automatically incremented aftera byte has been reador written. This allows the
user to program the registers sequentially or to read them sequentially.
During a read operation, the contents of these bits will roll over to 00b after the last
allowed register is accessed (10b).
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset During a write operation, the PCA9541 will acknowledge bytes sent to the IE and
CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status
Register sinceitisa read-only register. The2 LSBsof the Command Codedo not roll
over to 00b but stay at 10b.
Only the 2 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeros. Any command code (write operation)
different from ‘000AI 0000’, ‘000AI 0001’, and ‘000AI 0010’ will not be acknowledged. At
power-up, this register defaults to all zeros.
Each system master controlsits own setof registers, however they can also read specific
bits from the other system master.
8.3 Interrupt Enable and Control registers descriptionWhen a master seeks control of the bus by connecting its I2 C-bus channel to the
PCA9541 downstream channel, it has to write to the CONTROL register (Reg#01).
Bits MYBUS and BUSON allow the master to take control of the bus.
The MYBUS and the NMYBUS bits determine which master has control of the bus.
Table9 explains which master gets controlof the bus and how. Thereisno arbitration. Any
master can take controlof the bus whenit wants regardlessof whether the other masteris
using it or not.
The BUSON and the NBUSON bits determine whether the upstream bus is connected or
disconnected to/from the downstream bus. Table 10 explains when the upstream bus is
connected or disconnected.
Internally, the state machine does the following:
If the combination of the BUSON and the NBUSON bits causes the upstream to be
disconnected from the downstream bus, then thatis done. Soin this case, the values
of the MYBUS and the NMYBUS do not matter.
Table 4. Command Code register 0 IE R/W interrupt enable 1 CONTROL R/W control switch 0 ISTAT R only interrupt status 1 not allowed
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset If a master was connected to the downstream bus prior to the disconnect, then an
interrupt is sent on the respective interrupt output in an attempt to let that master
know thatitisno longer connectedto the downstream bus. Thisis indicatedby setting
the BUSLOST bit in the Interrupt Status Register.
If the combination of the BUSON and the NBUSON bits causes a master to be
connected to the downstream bus and if there is no change in the BUSON bits since
when the disconnect took effect, then the master requesting the bus is connected to
the downstream bus. If it requests a bus initialization sequence, then it is performed.
If there is no change in the combination of the BUSON and the NBUSON bits and a
new master wants the bus, then the downstream bus is disconnected from the old
master that was using it and the new master gets control of it. Again, the bus
initialization if requested is done. The appropriate interrupt signals are generated.
After a master has sent the bus control request: The previous master is disconnected from the I2 C-bus. An interrupt to the previous
master is sent through its INT line to let it know that it lost control of the bus.
BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by
setting the BUSLOSTMSK bit to logic1. A built-in bus initialization/recovery function can take temporary control of the
downstream channel to initialize the bus before making the actual switch to the new
bus master. This function is activated by setting the BUSINIT to logic 1 by the master
during the same write sequence as the one programming MYBUS and BUSON bits.
When activated and whether the bus was previously idle or not: 9 clock pulses are sent on the SCL_SLAVE. SDA_SLAVE line is released (HIGH) when the clock pulses are sent to
SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge. Finally a STOP condition is sent to the downstream slave channel.
This sequence will complete any read transaction which was previously in process
and the downstream slave configured as a slave-transmitter should release the SDA
line because the PCA9541 did not acknowledge the last byte. When the initialization has been requested and completed, the PCA9541 sends an
interrupt to the new master through its INT line and connects the new master to the
downstream channel. BUSINIT bit in the Interrupt Status Register is set.
The switch
operation occurs after the master asking the bus control has sent a STOP
command. This interrupt can be masked by setting the BUSINITMSK bit to logic1. When the bus initialization/recovery function has not been requested (BUSINIT= 0),
the PCA9541 connects the new masterto the slave downstream channel.
The switch
operation occurs after the master asking the bus control has sent a STOP
command. PCA9541 sends an interrupt to the new master through its INT line if the
built-in bus sensor function detects a non-idle condition in the downstream slave
channel at the switching time. BUSOK bit in the Interrupt Status Register is set. This
means that a STOP condition has not been detected in the previous bus
communication and that an external bus recovery/initialization must be performed. If
an idle condition has been detected at the switching time, no interrupt will be sent.
This interrupt can be masked by setting the BUSOKMSK bit to logic1.
Interrupt status can be read. See Section 8.4 “Interrupt Status registers” for more
information.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and resetThe MYTEST and the NMYTEST bits cause the interrupt pinsof the respective mastersto
be activated for a ‘functional interrupt test’.
Remark: The regular way to proceed is that a master asks to take the control of the bus
by programming MYBUS and BUSON bits based on NMUYBUS and NBUSON values.
Nevertheless, the same master can also decideto giveup the controlof the bus and give
it to the other master. This is also done by programming the MYBUS and BUSON bits
based on NMYBUS and NBUSON values.
Remark: Any writes either to the Interrupt Enable Register or the Control Register cause
the respective register to be updated on the 9th clock cycle, that is, on the rising edge of
the acknowledge clock cycle.
Remark: The actual switch from one channel to another or the switching off of both the
channels happens on a STOP command that is sent by the master requesting the switch.
8.3.1 Register 0: Interrupt Enable (IE) register (B1:B0= 00b)This register allows a master to read and/or write (if needed) Mask options for its own
channel.
The Interrupt Enable register described below is identical for both the masters.
Nevertheless, there are physically 2 internal Interrupt Enable registers, one for each
upstream channel. When Master 0 reads/writes in this register, the internal Interrupt
Enable Register 0 will be accessed. When Master 1 reads/writes in this register, the
internal Interrupt Enable Register 1 will be accessed.
Table 5. Register 0 - Interrupt Enable (IE) register (B1:B0 = 00b) bit allocation0000 BUSLOSTMSK BUSOKMSK BUSINITMSK INTINMSK
Table 6. Register 0 - Interrupt Enable (IE) register bit descriptionLegend: * default value
7:4 - R only 0* not used BUSLOSTMSK R/W 0* An interrupt on INT will be generated after the other master has been
disconnected. An interrupt on INT will not be generated after the other master has been
disconnected. BUSOKMSK R/W 0* After connection is requested and Bus Initialization not requested
(BUSINIT=0),an interrupton INTwillbe generated whena non-idle situation
has been detectedon the downstream slave channelbythe bus sensorat the
switching moment.
Remark: Channel switching is done automatically after the STOP command. After connection is requested and Bus Initialization not requested
(BUSINIT= 0), an interrupt on INT will not be generated when a non-idle
situation has been detected on the downstream slave channel by the bus
sensor at the switching moment (masked).
Remark: Channel switching is done automatically after the STOP command.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset[1] Default values are the same for PCA9541/01 and PCA9541/03.
8.3.2 Register 1: Control Register (B1:B0= 01b)The Control Register described below is identical for both the masters. Nevertheless,
there are physically 2 internal Control Registers, one for each upstream channel. When
master 0 reads/writes in this register, the internal Control Register 0 will be accessed.
When master 1 reads/writes in this register, the internal Control Register 1 will be
accessed.
[1] Default values are the same for PCA9541/01 and PCA9541/03. BUSINITMSK R/W 0* After connection is requested and Bus Initialization requested (BUSINIT=1),
an interrupt on INT will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed. After connection is requested and Bus Initialization requested (BUSINIT=1),
an interrupt on INT will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed. INTINMSK R/W 0* Interrupt on INT_IN will generate an interrupt on INT. Interrupt on INT_IN will not generate an interrupt on INT (masked)
Table 6. Register 0 - Interrupt Enable (IE) register bit description …continuedLegend: * default value
Table 7. Register 1 - Control Register (B1:B0 = 01b) bit allocationNTESTON TESTON 0 BUSINIT NBUSON BUSON NMYBUS MYBUS
Table 8. Register 1 - Control Register (B1:B0= 01b) bit descriptionLegend: * default value NTESTON R/W 0* A logic level HIGH to the INT line of the other channel is sent (interrupt
cleared). A logic level LOW to the INT line of the other channel is sent (interrupt
generated). TESTON R/W 0* A logic level HIGH to the INT line is sent (interrupt cleared). A logic level LOW to the INT line is sent (interrupt generated). - R only 0* not used BUSINIT R/W 0* Bus initialization is not requested. Bus initialization is requested. NBUSON R only see
Table11
NBUSON bit along with BUSON bit decides whether any upstream channel connectedto the downstream channelor not. See Table 10, Table 11, and
Table 12. BUSON R/W see
Table11
BUSON bit along with the NBUSON bit decides whether any upstream
channel is connected to the downstream channel or not. See Table 10,
Table 11, and Table 12. NMYBUS R only see
Table11
NMYBUS bit along with MYBUS bit decides which upstream channel is
connected to the downstream channel. See Table9, Table 11, and Table 12. MYBUS R/W see
Table11
MYBUS bit along with the NMYBUS bit decides which upstream channel is
connected to the downstream channel. See Table9, Table 11, and Table 12.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset[1] MYBUS and NMYBUS is an exclusive-OR type function where:
Equal values (00b or 11b) means that the master reading its Control Register has control of the bus.
Different values (01b or 10b) means that the master reading its Control Register does not have control of
the bus.
[1] BUSON and NBUSON is an exclusive-OR type function where:
Equal values (00bor 11b) means thatthe connection betweenthe upstream andthe downstream channels
is off.
Different values (01b or 10b) means that the connection between the upstream and the downstream
channels is on.
Switch to the new channel is done when the master initiating the switch request sends a
STOP command to the PCA9541.
If either master wants to change the connection of the downstream channel, it needs to
write to
its Control Register (Reg#01), and then send a STOP command because anupdate of the connection to the downstream according to the values in the two internal
Control Registers happens only on a STOP command. Writing to one control register
followed by a STOP condition on the other master's channel will not cause an update to
the downstream connection.
When both masters request a switch to their own channel at the same time, the master
who last wrote to its Control Register before the PCA9541 receives a STOP command
wins the switching sequence. There is no arbitration performed.
The Auto Increment feature (AI= 1) allows to program the PCA9541 in 4 bytes:
Start
111A3A2A1A0 + 0 PCA9541 Address + Write
00010000 Select Reg#00 with AI = 1
Data Reg#00 Interrupt Enable Register data
Data Reg#01 Control Register data
Stop
Table 9. MYBUS and NMYBUS truth tableAs a master reads its Control Register 0 The master reading this combination has control of the bus. 0 The master reading this combination does not have control of the bus. 1 The master reading this combination does not have control of the bus. 1 The master reading this combination has control of the bus.
Table 10. BUSON and NBUSON truth table 0 off
10on
01on 1 off
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and resetTable 12 describes which command needs to be written to the Control Register when a
master device wantsto take controlof theI2 C-bus. Byte writtento the Control Registerisa
function of the current I2 C-bus control status performed after an initial reading of the
Control Register.
Current status of the I2 C-bus is determined by the bits MYBUS, NMYBUS, BUSON and
NBUSON is one of the following:
The master reading its Control Register does not have control and the I2 C-bus is off.
The master reading its Control Register does not have control and the I2 C-bus is on.
The master reading its Control Register has control and the I2 C-bus is off.
The master reading its Control Register has control and the I2 C-bus is on.2 C-bus off’ means that upstream and downstream channels are not connected together.2 C-bus on’ means that upstream and downstream channels are connected together.
Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only
those bits control the I2 C-bus control. The logic value for the 4 MSBs is specific to the
application and are not discussed in the table.
The read sequence is performed by the master as:- 111xxxx0- 000x0001-Sr- 111xxxx1- DataRead-P
The write sequence is performed by the master as:- 111xxxx0- 000x0001- DataWritten-P
Table 11. Default Control Register valuesPCA9541/01 MST_0 0 0 0 0 0 1 0 0
MST_1 0 0 0 0 1 0 1 0
PCA9541/03 MST_0 0 0 0 0 0 0 0 0
MST_1 0 0 0 0 0 0 1 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and resetOnly the 4 LSBs are sho
wn.
x0x0 in binar
y = 0, 2, 8 or A in he
xadecimal
x0x1 in binar
y = 1, 3, 9 or B in he
xadecimal
x1x0 in binar
y = 4, 6, C or E in he
xadecimal
x1x1 in binar
y = 5, 7, D or F in he
xadecimal
x can be either ‘0’ or ‘1’ since those bits are read-only bits
le 12.
Bus contr
ol sequence
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
8.4 Interrupt Status registersThe PCA9541 provides 4 different types of interrupt:
To indicate to the former I2 C-bus master that it is not in control of the bus anymore
To indicate to the new I2 C-bus master that:
The bus recovery/initialization has been performed and that the downstream
channel connection has been done (built-in bus recovery/initialization active).
A ‘bus not well initialized’ condition has been detected by the PCA9541 when the
switch has been done (built-in bus recovery/initialization not active). This
information can be used by the new master to initiate its own bus
recovery/initialization sequence.
Indicate to both I2 C-bus upstream masters that a downstream interrupt has been
generated through the INT_IN pin.
Functionality wiring test.
8.4.1 Bus control lost interruptWhenan upstream master takes controlof theI2 C-bus while the other channel was using
the downstream channel, an interrupt is generated to the master losing control of the bus
(INT line goes LOW to let the master know that it lost the control of the bus) immediately
after disconnection from the downstream channel.
By setting the BUSLOSTMSK bit to ‘1’, the interrupt is masked and the upstream master
that lost the I2 C-bus control does not receive an interrupt (INT line does not go LOW).
8.4.2 Recovery/initialization interruptBefore switching to a new upstream channel, an automatic bus recovery/initialization can performedby the PCA9541. This functionis requestedby setting the BUSINITbitto ‘1’.
When the downstream bus has been initialized, an interrupt to the new master is
generated (INT line goes LOW).
By setting the BUSINITMSK bit to ‘1’, the interrupt is masked and the new master does
not receive an interrupt (INT line does not go LOW).
When the automatic bus recovery/initialization is not requested, if the built-in bus sensor
function (sensing permanently the downstream I2 C-bus traffic) detects a non-idle
condition (previous bus channel connected to the downstream slave channel, was
between a START and STOP condition), then an interrupt to the new master is sent (INT
line goes LOW). This interrupt tells the new master that an external bus
recovery/initialization must be performed. By setting the BUSOKMSK bit to ‘1’, the
interrupt is masked and the new master does not receive an interrupt (INT line does not
go LOW).
Remark: In this particular situation, after the switch to the new master is performed,
read of the Interrupt Status Register is not possible if the switch happened in the
middle of a read sequence because the new master does not have control of the SDAline.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
8.4.3 Downstream interruptAn interrupt can also be generated by a downstream device by asserting the INT_IN pin
LOW. When INT_INis asserted LOW andif both INTINMSK bits are not setto‘1’by either
master, INT0 and INT1 both go LOW. setting the INTINMSKbitto‘1’bya master and/or the INTINMSKbitto‘1’by the other
master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does
(do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW).
8.4.4 Functional test interrupt master can sendan interruptto itselfto testits own INT wireor sendan interruptto the
other master to test its INT line. This is done by:
setting the TESTON bit to ‘1’ to test its own INT line
setting the NTESTON bit to ‘1’ to test the other master INT line
Setting the TESTON and/or NTESTON bits to ‘0’ by a master will clear the interrupt(s).
Remark: Interrupt outputs havean open-drain structure. Interrupt input does not have any
internal pull-up resistor and must not be left floating (that is, pulled HIGH to VDD through
resistor) in order to avoid any undesired interrupt conditions.
8.4.5 Register 2: Interrupt Status Register (B1:B0= 10b)The Interrupt Status Register for both the masters is identical and is described below.
Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream
channel.
When Master 0 reads this register, the internal Interrupt Register 0 will be accessed.
When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.
Table 13. Register 2 - Interrupt Status register (B1:B0 = 10b) bit allocationNMYTEST MYTEST 0 0 BUSLOST BUSOK BUSINIT INTIN
Table 14. Register 2 - Interrupt Status (ISTAT) register bit descriptionLegend: * default value NMYTEST[2] R only 0* no interrupt generated due to NTESTON bit from the other master
(NTESTON= 0 from the other master)[3] interrupt generated due to TESTON bit from the other master
(NTESTON=1 from the other master)[3] MYTEST[2] R only 0* no interrupt generated by TESTON bit (TESTON=0)[3] interrupt generated by TESTON bit (TESTON=1)[3] - R only 0* not used - R only 0* not used BUSLOST[4] R only 0* no interrupt generated to the previous master when switching to the new one
is initiated interrupt generated to the previous master when switching to the new one is
initiated
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset[1] Default values are the same for PCA9541/01 and PCA9541/03.
[2] Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:
INT_IN lines goes HIGH for INTIN bit
TESTON bit is cleared for MYTEST bit
NTESTON bit is cleared for NMYTEST bit
[3] Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.
[4] BUSINIT, BUSOK and BUSLOSTbitsinthe Interrupt Status Registerget cleared aftera readofthe same registeris done. Precisely,the
register gets cleared on the second clock pulse during the read operation.
[5] If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been
masked).
8.5 Power-on resetWhen power is applied to VDD, an internal power-on reset holds the PCA9541 in a reset
condition until VDD has reached VPOR.At this point, the reset conditionis released and the
internal registers are initialized to their default states, with:
PCA9541/01: default Channel 0 (no STOP detect)
After power-up and/or insertion of the device in the main I2 C-bus, the upstream
Channel 0 and the downstream slave channel are connected together.
PCA9541/03: default ‘no channel’ (no STOP detect)
After power-up and/or insertion of the device in the main I2 C-bus, no channel will be
connected to the downstream channel. The device is ready to receive a START
condition and its address by a master.
If either register writes to its Control Register, then the connection between the
upstream and the downstream channels is determined by the values on the Control
Registers.
Thereafter, VDD must be lowered below 0.2 V to reset the device. BUSOK[4] R only 0* no interrupt generated by bus sensor function interrupt generated by bus sensor function (masked when bus
recovery/initialization requested) - Bus was not idle when the switch occurred BUSINIT[4] R only 0* no interrupt generated by the bus recovery/initialization function interrupt generated by the bus recovery/initialization function;
recovery/initialization done INTIN[2] R only 0* no interrupt on interrupt input (INT_IN)[5] interrupt on interrupt input (INT_IN)[5]
Table 14. Register 2 - Interrupt Status (ISTAT) register bit description …continuedLegend: * default value
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
8.6 External reset reset canbe accomplishedby holding the RESET pin LOWfora minimumof tw(rst)L. The
PCA9541 registers and I2 C-bus state machine will be held in their default states until the
RESET input is once again HIGH. This input typically requires a pull-up resistor to VDD.
Default states are:
I2 C-bus upstream Channel 0 connected to the I2 C-bus downstream channel for the
PCA9541/01
no I2 C-bus upstream channel connected to the I2 C-bus downstream channel for the
PCA9541/03.
8.7 Voltage translationThe pass gate transistors of the PCA9541 are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2 C-bus to another.
Figure8 shows the voltage characteristicsof the pass gate transistors (note that the graph
was generated using the data specified in Section 12 “Static characteristics” of this data
sheet). In order for the PCA9541 to act as a voltage translator, the Vo(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main buses were
runningat5V, and the downstream bus was 3.3V, then Vo(sw) shouldbe equaltoor below
3.3 V to effectively clamp the downstream bus voltages. Looking at Figure 8, we see that
Vo(sw)(max) will be at 3.3 V when the PCA9541 supply voltage is 3.5 V or lower so the
PCA9541 supply voltage couldbe setto 3.3V. Pull-up resistors can thenbe usedto bring
the bus voltages to their appropriate levels (see Figure 17).
More Information on voltage translation can be found in Application Note AN262:
PCA954X family of I2 C/SMBus multiplexers and switches.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure9).
9.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the ST ART condition (S). LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see Figure 10).
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
9.3 System configurationA device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 11).
9.4 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9541
2-to-1 I2 C-bus master selector with interrupt logic and reset
9.5 Bus transactions
Remark: If a third data byte is sent, it will not be acknowledged by the PCA9541.
Remark: If a fourth data byte is read, the first register will be accessed.
