PCA9538PW Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9538PW ,8-bit I虏C-bus and SMBus low power I/O port with interrupt and resetFeatures and benefits2 8-bit I C-bus GPIO with interrupt and reset Operating power supply voltage ..
PCA9538PWR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-TSSOP -40 to 85Electrical Characteristics....... 5211.1 Trademarks..... 276.5 I C Interface Timing Requirements 61 ..
PCA9539BS ,16-bit I虏C-bus and SMBus low power I/O port with interrupt and reset PCA9539; PCA9539R216-bit I C-bus and SMBus low power I/O port with interrupt and resetRev. 7 — 15 ..
PCA9539D ,PCA9539; 16-bit I²C and SMBus, low power I/O port with interrupt and resetapplications and was developed to enhance the NXP Semiconductors 2family of I C-bus I/O expanders. ..
PCA9539DBQR ,Remote 16-Bit I2C And SMBus, Low-Power I/O Expander With Interrupt Output, Reset & Config. Registers 24-SSOP -40 to 85Electrical Characteristics....... 6211.1 Trademarks..... 286.5 I C Interface Timing Requirements... ..
PCA9539PW ,16-bit I虏C-bus and SMBus low power I/O port with interrupt and resetFEATURESbits. The data for each Input or Output is kept in the corresponding2 Input or Output regis ..
PEMH1 ,NPN/NPN resistor-equipped transistors; R1 = 22 k惟, R2 = 22 k惟Features and benefits  100 mA output current capability Reduces component count Built-in bias re ..
PEMH10 ,R1 = 2.2 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH11 ,R1 = 10 kOhm, R2 = 10 kOhmapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PEMH13 ,R1 = 4.7 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openLimiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..

PCA9538PW
8-bit I虏C-bus and SMBus low power I/O port with interrupt and reset
1. General description
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion with interrupt and reset for I2 C-bus/SMBus applications
and was developed to enhance the NXP Semiconductors family of I2 C-bus I/O expanders.
I/O expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push-buttons, LEDs, fans, etc.
The PCA9538 consists of an 8-bit Configuration register (input or output selection),
8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the Input
Port register can be inverted with the Polarity Inversion register. All registers can be read
by the system master.
The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O
pull-up resistor which greatly reduces power consumption when the I/Os are held LOW,
replacement of A2 with RESET and different address range.
The PCA9538 open-drain interrupt output (INT) is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed. The power-on reset sets the registers to their
default values and initializes the device state machine. The RESET pin causes the same
reset/initialization to occur without de-powering the device.
Two hardware pins (A0 and A1) vary the fixed I2 C-bus address and allow up to four
devices to share the same I2 C-bus/SMBus.
2. Features and benefits 8-bit I2 C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5V
(5.0V10% for PCA9538PW/Q900 AEC-Q100 compliant devices)5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up
PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and
reset
Rev. 6 — 6 February 2013 Product data sheet
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Internal power-on reset 8 I/O pins which default to 8 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in three different packages: SO16, TSSOP16 and HVQFN16
3. Ordering information
[1] PCA9538PW/Q900 is AEC-Q100 compliant. Contact i2c.support for PPAP.
3.1 Ordering options
Table 1. Ordering information
PCA9538BS 9538 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body44 0.85 mm
SOT629-1
PCA9538D PCA9538D SO16 plastic small outline package; 16 leads;
body width 7.5 mm
SOT162-1
PCA9538PW PCA9538 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PCA9538PW/Q900[1] PCA9538 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Table 2. Ordering options
PCA9538BS PCA9538BS,118 HVQFN16 Reel pack, SMD,
13-inch
6000 Tamb= 40 C to +85C
PCA9538D PCA9538D,112 SO16 Tube, bulk pack 1920 Tamb= 40 C to +85C
PCA9538D,118 SO16 Reel pack, SMD,
13-inch
1000 Tamb= 40 C to +85C
PCA9538PW PCA9538PW,112 TSSOP16 Tube, bulk pack 2400 Tamb= 40 C to +85C
PCA9538PW,118 TSSOP16 Reel pack, SMD, 13-inch 2500 Tamb= 40 C to +85C
PCA9538PW/Q900 PCA9538PW/Q900,118 TSSOP16 Reel pack, SMD,
13-inch
2500 Tamb= 40 C to +125C
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
4. Block diagram
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Table 3. Pin description 1 15 address input 0 2 16 address input 1
RESET 3 1 active LOW reset input
IO0 4 2 input/output 0
IO1 5 3 input/output 1
IO2 6 4 input/output 2
IO3 7 5 input/output 3
VSS 86[1] supply ground
IO4 9 7 input/output 4
IO5 10 8 input/output 5
IO6 11 9 input/output 6
IO7 12 10 input/output 7
INT 13 11 interrupt output (open-drain)
SCL 14 12 serial clock line
SDA 15 13 serial data line
VDD 16 14 supply voltage
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9538”.
6.1 Device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the registers will be written or read.
6.2.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 4. Command byte read byte Input Port register read/write byte Output Port register read/write byte Polarity Inversion register read/write byte Configuration register
Table 5. Register 0 - Input Port register bit description
Legend: * default value. I7 read only X* value ‘X’ is determined by externally applied
logic level6 I6 read only X* I5 read only X* I4 read only X* I3 read only X* I2 read only X* I1 read only X* I0 read only X*
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
6.2.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a 0), the Input Port data polarity is retained.
Table 6. Register 1 - Output Port register bit description
Legend: * default value. O7 R 1* reflects outgoing logic levels of pins defined as outputs
by Register36O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
Table 7. Register 2 - Polarity Inversion register bit description
Legend: * default value. N7 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0*
3N3 R/W 0*
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
6.3 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9538 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9538 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst).
The PCA9538 registers and SMBus/I2 C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input requires a pull-up resistor to
VDD if no active connection is used.
6.5 Interrupt output
The open-drain interrupt output (INT) is activated when one of the port pins changes state
and the pin is configured as an input. The interrupt is de-activated when the input returns
to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
Table 8. Register 3 - Configuration register bit description
Legend: * default value. C7 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as an input
(default value)
6C6 R/W 1*
5C5 R/W 1*
4C4 R/W 1*
3C3 R/W 1*
2C2 R/W 1*
1C1 R/W 1*
0C0 R/W 1*
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.6 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figure7
and Figure 8. Data is read from the PCA9538 registers using the read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
7. Application design-in information
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
7.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OVI
at or above VDD and prevents additional supply current consumption when the LED is off.
8. Limiting values
Table 9. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +6.0 V input current - 20 mA
VI/O voltage on an input/output pin VSS 0.5 5.5 V
IO(IOn) output current on pin IOn - 50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating
all devices except PCA9538PW/Q900 40 +85 C
PCA9538PW/Q900 40 +125 C
Tj(max) maximum junction temperature - +125 C
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
9. Static characteristicsTable 10. Static characteristics for all devices except PCA9538PW/Q900
VDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD =5.5V; load; fSCL= 100 kHz 104 175 A
IstbL LOW-level standby current Standby mode; VDD =5.5V; load; VI =VSS;
fSCL=0 kHz; I/O= inputs
-0.25 1 A
IstbH HIGH-level standby current Standby mode; VDD =5.5V; load; VI =VDD;
fSCL=0 kHz; I/O= inputs
-0.25 1 A
VPOR power-on reset voltage no load; VI =VDD or VSS [1]- 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5 V
IOL LOW-level output current VOL =0.4V 3 7 - mA leakage current VI =VDD =VSS 1- +1 A input capacitance VI =VSS - 5 10 pF
I/Os
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL =0.5V
VDD =2.3V [2] 810 - mA
VDD =3.0V [2] 814 - mA
VDD =4.5V [2] 817 - mA
VOL =0.7V
VDD =2.3V [2] 10 13 - mA
VDD =3.0V [2] 10 19 - mA
VDD =4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH= 8mA
VDD =2.3V [3] 1.8 - - V
VDD =3.0V [3] 2.6 - - V
VDD =4.5V [3] 4.1 - - V
IOH= 10 mA
VDD =2.3V [3] 1.7 - - V
VDD =3.0V [3] 2.5 - - V
VDD =4.5V [3] 4.0 - - V
ILI input leakage current VI =VDD =VSS 1- +1 A input capacitance - 5 10 pF
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
Interrupt INT
IOL LOW-level output current VOL =0.4V 3 13 - mA
Select inputs A0, A1, RESET
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- +1 A
Table 10. Static characteristics for all devices except PCA9538PW/Q900 …continued
VDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.
Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device
VDD =5.0V10 %; VSS =0V; Tamb= 40 C to +125 C; unless otherwise specified.
Supplies
VDD supply voltage 4.5 - 5.5 V
IDD supply current operating mode; VDD =5.5V; load; fSCL= 100 kHz 104 175 A
IstbL LOW-level standby current Standby mode; VDD =5.5V; load; VI =VSS;
fSCL=0 kHz; I/O= inputs
-0.25 1 A
IstbH HIGH-level standby current Standby mode; VDD =5.5V; load; VI =VDD;
fSCL=0 kHz; I/O= inputs
-0.25 1 A
VPOR power-on reset voltage no load; VI =VDD or VSS [1]- 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5 V
IOL LOW-level output current VOL =0.4V 3 7 - mA leakage current VI =VDD =VSS 1- +1 A input capacitance VI =VSS - 5 10 pF
I/Os
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VDD =4.5V
VOL =0.5V [2] 817 - mA
VOL =0.7V [2] 10 24 - mA
VOH HIGH-level output voltage VDD =4.5V
IOH= 8mA [3] 4.1 - - V
IOH= 10 mA [3] 4.0 - - V
ILI input leakage current VI =VDD =VSS 1- +1 A input capacitance - 5 10 pF
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
Interrupt INT
IOL LOW-level output current VOL =0.4V 3 13 - mA
Select inputs A0, A1, RESET
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- +1 A
Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device …continued
VDD =5.0V10 %; VSS =0V; Tamb= 40 C to +125 C; unless otherwise specified.
NXP Semiconductors PCA9538
8-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
10. Dynamic characteristics
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
Table 12. Dynamic characteristics
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition
4.7 - 1.3 - s
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition
4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0 - 0 - ns
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s rise time of both SDA and SCL signals - 1000 20+ 0.1Cb[3] 300 ns fall time of both SDA and SCL signals - 300 20+ 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter
-50 - 50 ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 100 - 100 - ns
th(D) data input hold time 1 - 1 - s
Interrupt timing
tv(INT) valid time on pin INT -4 - 4 s
trst(INT) reset time on pin INT -4 - 4 s
RESET
tw(rst) reset pulse width 4 - 4 - ns
trec(rst) reset recovery time 0 - 0 - ns
trst reset time 400 - 400 - ns

Partno	Mfg	Dc	Qty	Available	Descript
PCA9538PW	NXP	N/a	1102	avai	8-bit I虏C-bus and SMBus low power I/O port with interrupt and reset