PCA9537DP ,4-bit I2C-bus and SMBus low power I/O port with interrupt and resetapplications2and was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders.I/ ..
PCA9538 ,8-bit I2C and SMBus low power I/O port with interrupt and resetBlock diagram IO0A0A1 IO18-bitIO2INPUT/SCL IO3INPUT 2I C-BUS/SMBusOUTPUTFILTERSDA IO4CONTROLwrite p ..
PCA9538D ,8-bit I2C and SMBus low power I/O port with interrupt and resetapplications 2and was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders. ..
PCA9538DB ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-SSOP -40 to 85Features 2 DescriptionThis 8-bit I/O expander for the two-line bidirectional1• Low Standby Current ..
PCA9538DBR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-SSOP -40 to 85 SCPS126F–SEPTEMBER 2006–REVISED JUNE 20144 Description (Continued)INT can be connected to the inte ..
PCA9538DGVR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-TVSOP -40 to 85Maximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
PEMH1 ,NPN/NPN resistor-equipped transistors; R1 = 22 k惟, R2 = 22 k惟Features and benefits 100 mA output current capability Reduces component count Built-in bias re ..
PEMH10 ,R1 = 2.2 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH11 ,R1 = 10 kOhm, R2 = 10 kOhmapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PEMH13 ,R1 = 4.7 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openLimiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PCA9537DP
4-bit I2C-bus and SMBus low power I/O port with interrupt and reset
General descriptionThe PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel
Input/Output (GPIO) expansion with interrupt and reset for I2 C-bus/SMBus applications
and was developedto enhance the NXP Semiconductors familyofI2 C-bus I/O expanders.
I/O expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push-buttons, LEDs, fans, etc.
The PCA9537 consists of a 4-bit Configuration register (input or output selection),
4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the Input
Port register can be inverted with the Polarity Inversion register. All registers can be read
by the system master.
The PCA9537 open-drain interrupt output (INT) is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed. The power-on reset sets the registers to their
default values and initializes the device state machine. The RESET pin causes the same
reset/initialization to occur without de-powering the device.
The I2 C-bus address is fixed and allows only one device on the same I2 C-bus/SMBus.
Features 4-bit I2 C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins that default to 4 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
PCA9537
4-bitI2 C-bus and SMBus low power I/O port with interrupt and
reset
Rev. 05 — 7 May 2009 Product data sheet
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in TSSOP10 package
Ordering information Block diagram
Table 1. Ordering informationTamb= −40 °C to +85°C
PCA9537DP 9537 TSSOP10 plastic thin shrink small outline package; leads; body width3 mm
SOT552-1
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin descriptionIO0 1 input/output 0
IO1 2 input/output 1
IO2 3 input/output 2
IO3 4 input/output 3
VSS 5 supply ground
RESET 6 active LOW reset input
INT 7 interrupt output (open-drain)
SCL 8 serial clock line
SDA 9 serial data line
VDD 10 supply voltage
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Functional descriptionRefer to Figure 1 “Block diagram of PCA9537”.
6.1 Device address
6.2 Registers
6.2.1 Command byteThe command byteis the first byteto follow the address byte duringa write transmission.
It is used as a pointer to determine which of the registers will be written or read.
6.2.2 Register 0 - Input Port registerThis registerisa read-only port.It reflects the incoming logic levelsof the pins, regardless whether the pinis definedasan inputoran outputby Register3. Writesto this register
have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 3. Command byte read byte Input Port register read/write byte Output Port register read/write byte Polarity Inversion register read/write byte Configuration register
Table 4. Register 0 - Input Port register bit descriptionLegend: * default value. I7 read only 1* not used I6 read only 1* I5 read only 1* I4 read only 1* I3 read only X* value ‘X’ is determined by externally applied logic
level2 I2 read only X* I1 read only X* I0 read only X*
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.3 Register 1 - Output Port registerThis register reflects the outgoing logic levelsof the pins definedas outputsby Register3.
Bit valuesin this register haveno effecton pins definedas inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection,
not the actual pinvalue.
6.2.4 Register 2 - Polarity Inversion registerThis register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a 0), the Input Port data polarity is retained.
Table 5. Register 1 - Output Port register bit descriptionLegend: * default value. O7 R 1* not used
6O6 R 1*
5O5 R 1*
4O4 R 1* O3 R 1* reflects outgoing logic levelsof pins definedas outputs
by Register32O2 R 1*
1O1 R 1*
0O0 R 1*
Table 6. Register 2 - Polarity Inversion register bit descriptionLegend: * default value. N7 R/W 0* not used N6 R/W 0* N5 R/W 0* N4 R/W 0* N3 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted N2 R/W 0* N1 R/W 0* N0 R/W 0*
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Register 3 - Configuration registerThis register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pinis enabledasan input with high-impedance output driver.Ifabitin
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
6.3 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9537 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9537 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET inputA reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst).
The PCA9537 registers and SMBus/I2 C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input requires a pull-up resistor to
VDD if no active connection is used.
6.5 Interrupt outputThe open-drain interrupt output (INT)is activated when oneof the port pins changes state
and the pin is configured as an input. The interrupt is de-activated when the input returns
to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
Table 7. Register 3 - Configuration register bit descriptionLegend: * default value. C7 R/W 1* not used C6 R/W 1* C5 R/W 1* C4 R/W 1* C3 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as an input
(default value) C2 R/W 1* C1 R/W 1* C0 R/W 1*
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.6 I/O portWhen an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage maybe raised above VDDtoa maximumof 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
stateof the Output Port register. Care shouldbe exercisedifan external voltageis appliedan I/O configuredasan output becauseof the low-impedance paths that exist between
the pin and either VDD or VSS.
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactionsData is transmitted to the PCA9537 registers using the write mode as shown in Figure5
and Figure 6. Data is read from the PCA9537 registers using the read mode as shown in
Figure 7 and Figure 8. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Application design-in information
7.1 Minimizing IDD when the I/Os are used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to VDD through a
resistoras shownin Figure9. Since the LED actsasa diode, when the LEDisoff the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater thanor equalto VDD when the LEDis off.
Figure 10 shows a high value resistor in parallel with the LED. Figure 11 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OVI
at or above VDD and prevents additional supply current consumption when the LED is off.
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Limiting values Static characteristics
Table 8. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V input current - ±20 mA
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(IOn) output current on pin IOn - ±50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
Tj(max) maximum junction temperature - +125 °C
Table 9. Static characteristicsVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
SuppliesVDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD= 5.5V; load; fSCL= 100 kHz 104 175 μA
IstbL LOW-level standby current Standby mode; VDD= 5.5V; load; VI =VSS;
fSCL=0 kHz; I/O= inputs 0.25 1 μA
IstbH HIGH-level standby current Standby mode; VDD= 5.5V; load; VI =VDD;
fSCL=0 kHz; I/O= inputs 0.25 1 μA
VPOR power-on reset voltage no load; VI =VDD or VSS [1]- 1.5 1.65 V
Input SCL; input/output SDAVIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL= 0.4V 3 7 - mA leakage current VI =VDD =VSS −1- +1 μA input capacitance VI =VSS - 5 10 pF
NXP Semiconductors PCA9537
4-bit I2 C-bus and SMBus low power I/O port with interrupt and reset[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
I/OsVIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL= 0.5V
VDD= 2.3V [2] 810 - mA
VDD= 3.0V [2] 814 - mA
VDD= 4.5V [2] 817 - mA
VOL= 0.7V
VDD= 2.3V [2] 10 13 - mA
VDD= 3.0V [2] 10 19 - mA
VDD= 4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH= −8mA
VDD= 2.3V [3] 1.8 - - V
VDD= 3.0V [3] 2.6 - - V
VDD= 4.5V [3] 4.1 - - V
IOH= −10 mA
VDD= 2.3V [3] 1.7 - - V
VDD= 3.0V [3] 2.5 - - V
VDD= 4.5V [3] 4.0 - - V leakage current VI =VDD =VSS −1- +1 μA input capacitance - 5 10 pF
Interrupt INTIOL LOW-level output current VOL= 0.4V 3 13 - mA
IOH HIGH-level output current VOL= 0.4V −1- +1 μA
Select input RESETVIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V leakage current VI =VDD =VSS −1- +1 μA
Table 9. Static characteristics …continuedVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
