PCA9536DP-PCA9536TK Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9536TK ,4-bit I2C-bus and SMBus I/O portFeatures2 4-bit I C-bus GPIO Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant ..
PCA9537DP ,4-bit I2C-bus and SMBus low power I/O port with interrupt and resetapplications2and was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders.I/ ..
PCA9538 ,8-bit I2C and SMBus low power I/O port with interrupt and resetBlock diagram IO0A0A1 IO18-bitIO2INPUT/SCL IO3INPUT 2I C-BUS/SMBusOUTPUTFILTERSDA IO4CONTROLwrite p ..
PCA9538D ,8-bit I2C and SMBus low power I/O port with interrupt and resetapplications 2and was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders. ..
PCA9538DB ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-SSOP -40 to 85Features 2 DescriptionThis 8-bit I/O expander for the two-line bidirectional1• Low Standby Current ..
PCA9538DBR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Config Registers 16-SSOP -40 to 85 SCPS126F–SEPTEMBER 2006–REVISED JUNE 20144 Description (Continued)INT can be connected to the inte ..
PEMD6 ,R2 = openLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH1 ,NPN/NPN resistor-equipped transistors; R1 = 22 k惟, R2 = 22 k惟Features and benefits  100 mA output current capability Reduces component count Built-in bias re ..
PEMH10 ,R1 = 2.2 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH11 ,R1 = 10 kOhm, R2 = 10 kOhmapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PEMH13 ,R1 = 4.7 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openLimiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter C ..

PCA9536DP-PCA9536TK
4-bit I2C-bus and SMBus I/O port
General descriptionThe PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2 C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2 C-bus I/O expanders. I/O expanders
provide a simple solution when additional I/O is needed for ACPI power switches,
sensors, push buttons, LEDs, fans, etc.
The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit
Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the read
register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.
The power-on reset sets the registers to their default values and initializes the device state
machine.
The I2 C-bus address is fixed and allows only one device on the same I2 C-bus/SMBus. Features 4-bit I2 C-bus GPIO Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins which default to 4 inputs with 100 kΩ internal pull-up resistor0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8), HVSON8
PCA9536
4-bit I2 C-bus and SMBus I/O port
Rev. 05 — 25 January 2010 Product data sheet
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Ordering information
[1] Also known as MSOP8. Block diagram
Table 1. Ordering information
Tamb= −40 °C to +85°C
PCA9536D PCA9536 SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCA9536DP 9536 TSSOP8[1] plastic thin shrink small outline package; leads; body width 3 mm
SOT505-1
PCA9536TK 9536 HVSON8 plastic thermal enhanced very thin small
outline package; no leads; 8 terminals;
body3×3× 0.85 mm
SOT908-1
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
IO0 1 input/output 0
IO1 2 input/output 1
IO2 3 input/output 2
VSS 4 supply ground
IO3 5 input/output 3
SCL 6 serial clock line
SDA 7 serial data line
VDD 8 supply voltage
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Functional description
Refer to Figure 1 “Block diagram of PCA9536”.
6.1 Registers
6.1.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally logic 1 when
no external signal externally applied because of the internal pull-up resistors.
Table 3. Command byte read byte Input Port register read/write byte Output Port register read/write byte Polarity Inversion register read/write byte Configuration register
Table 4. Register 0 - Input Port register bit description
Legend: * default value I7 read only 1* not used I6 read only 1* I5 read only 1* I4 read only 1* I3 read only X determined by externally applied logic level I2 read only X I1 read only X I0 read only X
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
‘Not used’ bits can be programmed with either logic 0 or logic1.
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
‘Not used’ bits can be programmed with either logic 0 or logic1.
Table 5. Register 1 - Output Port register bit description
Legend: * default value O7 R 1* not used
6O6 R 1*
5O5 R 1*
4O4 R 1* O3 R 1* reflects outgoing logic levels of pins defined as
outputs by Register 32O2 R 1*
1O1 R 1*
0O0 R 1*
Table 6. Register 2 - Polarity Inversion register bit description
Legend: * default value N7 R/W 0* not used
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0* N3 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default
value)
1 = Input Port register data inverted
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to VDD.
‘Not used’ bits can be programmed with either logic 0 or logic1.
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9536 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 kΩ typical) to VDD. The input voltage may
be raised above VDD to a maximum of 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
Table 7. Register 3 - Configuration register bit description
Legend: * default value C7 R/W 1* not used
6C6 R/W 1*
5C5 R/W 1*
4C4 R/W 1* C3 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
2C2 R/W 1*
1C1 R/W 1*
0C0 R/W 1*
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port
6.4 Device address
6.5 Bus transactions
Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure7
and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function, so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Application design-in information
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Limiting values Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V input current - ±20 mA
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(IOn) output current on pin IOn - ±50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature −40 +85 °C
Tj(max) maximum junction temperature - +125 °C
NXP Semiconductors PCA9536
4-bit I2 C-bus and SMBus I/O port Static characteristics
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
Table 9. Static characteristics
VDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD =5.5V; load; fSCL= 100 kHz 290 400 μA
Istb standby current Standby mode; VDD= 5.5 V; no load; =VSS; fSCL=0 kHz; I/O= inputs 225 350 μA
Standby mode; VDD= 5.5 V; no load; =VDD; fSCL=0 kHz; I/O= inputs
-0.25 1 μA
VPOR power-on reset voltage [1]- 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5 V
IOL LOW-level output current VOL =0.4V 3 6 - mA leakage current VI =VDD =VSS −1- +1 μA input capacitance VI =VSS - 6 10 pF
I/Os
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL =0.5 V; VDD =2.3V [2] 810 - mA
VOL =0.7 V; VDD =2.3V [2] 10 13 - mA
VOL =0.5 V; VDD =3.0V [2] 814 - mA
VOL =0.7 V; VDD =3.0V [2] 10 19 - mA
VOL =0.5 V; VDD =4.5V [2] 817 - mA
VOL =0.7 V; VDD =4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH= −8mA; VDD =2.3V [3] 1.8 - - V
IOH= −10 mA; VDD =2.3V [3] 1.7 - - V
IOH= −8mA; VDD =3.0V [3] 2.6 - - V
IOH= −10 mA; VDD =3.0V [3] 2.5 - - V
IOH= −8mA; VDD =4.75V [3] 4.1 - - V
IOH= −10 mA; VDD =4.75V [3] 4.0 - - V
ILIH HIGH-level input leakage
current
VDD =3.6 V; VI =VDD -- 1 μA
ILIL LOW-level input leakage
current
VDD =5.5 V; VI =VSS -- −100 μA input capacitance - 3.7 5 pF output capacitance - 3.7 5 pF

Partno	Mfg	Dc	Qty	Available	Descript
PCA9536DP	NXP	N/a	1984	avai	4-bit I2C-bus and SMBus I/O port
PCA9536TK	NXP	N/a	16553	avai	4-bit I2C-bus and SMBus I/O port