PCA9535BS ,16-bit I2C-bus and SMBus, low power I/O port with interruptGeneral descriptionThe PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of General ..
PCA9535CHF ,16-bit I2C-bus and SMBus, low power I/O port with interruptapplications and was2developed to enhance the NXP Semiconductors family of I C-bus I/O expanders. T ..
PCA9535CPW ,16-bit I2C-bus and SMBus, low power I/O port with interruptPCA9535; PCA9535C216-bit I C-bus and SMBus, low power I/O port with interruptRev. 05 — 15 September ..
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PCA9535D ,16-bit I2C-bus and SMBus, low power I/O port with interrupt
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PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB3 ,PNP resistor-equipped double transistor R1 = 4.7 kOhm, R2 = openLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB30 ,PNP/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = openApplicationsn Low current peripheral driver n Cost-saving alternative for BC857BSand BC857BVn Contr ..
PCA9535BS-PCA9535CHF-PCA9535CPW-PCA9535HF
16-bit I2C-bus and SMBus, low power I/O port with interrupt
General descriptionThe PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of General
Purpose parallel Input/Output (GPIO) expansionforI2 C-bus/SMBus applications and was
developed to enhance the NXP Semiconductors family of I2 C-bus I/O expanders. The
improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, and smaller packaging. I/O expanders provide a simple
solution when additional I/O is needed for ACPI power switches, sensors, push buttons,
LEDs, fans, etc.
The PCA9535 and PCA9535C consist of two 8-bit Configuration (Input or Output
selection), Input, Output and Polarity Inversion (active HIGH or active LOW operation)
registers. The system master can enable the I/Os as either inputs or outputs by writing to
the I/O configuration bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
Inversion register.All registers canbe readby the system master. Although pin-to-pin and2 C-bus address compatible with the PCF8575, software changes are required dueto the
enhancements and are discussed in Application Note AN469.
The PCA9535is identicalto the PCA9555 exceptfor the removalof the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9535C is identical to the PCA9535 except that all the I/O pins are
high-impedance open-drain outputs.
The PCA9535 and PCA9535C open-drain interrupt output is activated when any input
state differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2 C-bus address and allow up to eight
devices to share the same I2 C-bus/SMBus. The fixed I2 C-bus address of the PCA9535
and PCA9535C are the sameas the PCA9555 allowingupto eightof these devicesin any
combination to share the same I2 C-bus/SMBus.
Features Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs
PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
Rev. 05 — 15 September 2008 Product data sheet
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in four different packages: SO24, TSSOP24, HVQFN24 and HWQFN24
Ordering information
3.1 Ordering options
Table 1. Ordering informationPCA9535D SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
PCA9535PW TSSOP24 plastic thin shrink small outline package;24 leads; body
width 4.4 mm
SOT355-1
PCA9535BS HVQFN24 plastic thermal enhanced very thin quad flat package; leads; 24 terminals; body4×4× 0.85 mm
SOT616-1
PCA9535HF HWQFN24 plastic thermal enhanced very very thin quad flat
package; no leads; 24 terminals; body4×4× 0.75 mm
SOT994-1
PCA9535CD SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
PCA9535CPW TSSOP24 plastic thin shrink small outline package;24 leads; body
width 4.4 mm
SOT355-1
PCA9535CHF HWQFN24 plastic thermal enhanced very very thin quad flat
package; no leads; 24 terminals; body4×4× 0.75 mm
SOT994-1
Table 2. Ordering optionsPCA9535D PCA9535D Tamb= −40 °C to +85°C
PCA9535PW PCA9535PW Tamb= −40 °C to +85°C
PCA9535BS 9535 Tamb= −40 °C to +85°C
PCA9535HF P35H Tamb= −40 °C to +85°C
PCA9535CD PCA9535CD Tamb= −40 °C to +85°C
PCA9535CPW PCA9535C Tamb= −40 °C to +85°C
PCA9535CHF P35C Tamb= −40 °C to +85°C
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt Block diagram
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt Pinning information
5.1 Pinning
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
5.2 Pin description[1] HVQFN24 and HWQFN24 package die supply ground is connected to both the VSS pin and the exposed
center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board-level performance,the exposed pad needstobe solderedtothe board using
a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
[2] PCA9535 I/Os are totem pole, whereas the I/Os on PCA9535C are open-drain.
Table 3. Pin descriptionINT 1 22 interrupt output (open-drain) 2 23 address input 1 3 24 address input 2
IO0_0 4 1 port 0 input/output[2]
IO0_1 5 2
IO0_2 6 3
IO0_3 7 4
IO0_4 8 5
IO0_5 9 6
IO0_6 10 7
IO0_7 11 8
VSS 12 9[1] supply ground
IO1_0 13 10 port 1 input/output[2]
IO1_1 14 11
IO1_2 15 12
IO1_3 16 13
IO1_4 17 14
IO1_5 18 15
IO1_6 19 16
IO1_7 20 17 21 18 address input 0
SCL 22 19 serial clock line
SDA 23 20 serial data line
VDD 24 21 supply voltage
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt Functional descriptionRefer to Figure 1 “Block diagram of PCA9535; PCA9535C”.
6.1 Device address
6.2 Registers
6.2.1 Command byteThe command byteis the first byteto follow the address byte duringa write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command byte Input port0 Input port1 Output port0 Output port1 Polarity Inversion port0 Polarity Inversion port1 Configuration port0 Configuration port1
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
6.2.2 Registers 0 and 1: Input port registersThis register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
6.2.3 Registers 2 and 3: Output port registersThis register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined inputs.In turn, reads from this register reflect the value thatisin the flip-flop controlling
the output selection,
not the actual pin value.
6.2.4 Registers 4 and 5: Polarity Inversion registersThis register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Input port 0 Register
Table 6. Input port 1 register
Table 7. Output port 0 register
Table 8. Output port 1 register
Table 9. Polarity Inversion port 0 register
Table 10. Polarity Inversion port 1 register
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
6.2.5 Registers 6 and 7: Configuration registersThis register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
6.3 Power-on resetWhen poweris appliedto VDD,an internal power-on reset holds the PCA9535/PCA9535C
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9535/PCA9535C registers and SMBus state machine will initialize
to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 I/O portWhen an I/O is configured as an input on PCA9535, FETs Q1 and Q2 are off, creating a
high impedance input. The input voltage maybe raised above VDDtoa maximumof 5.5V.
In the case of PCA9535C, FET Q1 has been removed and the open-drain FET Q2 will
function the same as PCA9535.
If the I/O is configured as an output, then on PCA9535 either Q1 or Q2 is on, depending the stateof the Output Port register. Care shouldbe exercisedifan external voltageis
applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either VDD or VSS.
Table 11. Configuration port 0 register
Table 12. Configuration port 1 register
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
6.5 Bus transactions
6.5.1 Writing to the port registersData is transmitted to the PCA9535/PCA9535C by sending the device address and
setting the least significant bit to a logic 0 (see Figure 6 “PCA9535; PCA9535C device
address”). The command byteis sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9535/PCA9535C are configured to operate as four
register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and
Configuration Ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 8 and Figure 9). For example, if the first byte is
sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
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NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
6.5.2 Reading the port registersIn order to read data from the PCA9535/PCA9535C, the bus master must first send the
PCA9535/PCA9535C address with the least significant bit set to a logic 0 (see Figure 6
“PCA9535; PCA9535C device address”). The command byteis sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9535/PCA9535C (see
Figure 10, Figure11 and Figure 12). Datais clocked into the registeron the falling edgeof
the acknowledge clock pulse. After the first byteis read, additional bytes maybe read but
the data will now reflect the informationin the other registerin the pair. For example,if you
read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on
the numberof data bytes receivedin one read transmission but the final byte received, the
bus master must not acknowledge the data.
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NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
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NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
6.5.3 Interrupt outputThe open-drain interrupt output is activated when one of the port pins change state and
the pinis configuredasan input. The interruptis deactivated when the input returnstoits
previous state or the Input Port register is read (see Figure 11). A pin configured as an
output cannot causean interrupt. Since each 8-bit portis read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changingan I/O froman outputtoan input may causea false interruptto occur
if the state of the pin does not match the contents of the Input Port register.
Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 13).
7.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis definedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 14).
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt
7.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 15).
7.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH periodof the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9535; PCA9535C
16-bit I2 C-bus and SMBus, low power I/O port with interrupt Application design-in information
