PCA9530DP Fast Delivery |IC PHOENIX CO.,LIMITED

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PCA9530DP
2-bit I2C-bus LED dimmer
General descriptionThe PCA9530isa 2-bitI2 C-bus and SMBus I/O expander optimized for dimming LEDsin
256 discrete steps for Red/Green/Blue (RGB) color mixing and backlight applications.
The PCA9530 contains an internal oscillator with two user programmable blink rates and
duty cycles coupled to the output PWM. The LED brightness is controlled by setting the
blink rate high enough (> 100 Hz) that the blinking cannot be seen and then using the
duty cycleto vary the amountof time the LEDison and thus the average current through
the LED.
The initial setup sequence programs the two blink rates/duty cycles for each individual
PWM. From then on, only one command from the bus masteris requiredto turn individual
LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a
different brightness or blink at periods up to 1.69 second. The open-drain outputs directly
drive the LEDs with maximum output sink current of 25 mA per bit and 50 mA per
package.
To blink LEDs at periods greater than 1.69 second, the bus master (MCU, MPU, DSP,
chip set, etc.) must send repeated commands to turn the LED on and off as is currently
done when using normal I/O Expanders like the NXP Semiconductors PCF8574 or
PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose
parallel Input/Output (GPIO) expansion which provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, alarm monitoring, fans,
etc.
The active LOW hardware reset pin (RESET) and Power-On Reset (POR) initialize the
registers to their default state causing the bits to be set HIGH (LED off).
One hardware address pin on the PCA9530 allows two devices to operate on the same
bus. Features 2 LED drivers (on, off, ﬂashing at a programmable rate) 2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.591 Hz and 152 Hz (1.69 seconds and 6.58 milliseconds) 256 brightness steps Input/output not used as LED drivers can be used as regular GPIOs Internal oscillator requires no external componentsI2 C-bus interface logic compatible with SMBus Internal power-on reset
PCA9530
2-bit I2 C-bus LED dimmer
Rev. 03 — 26 February 2009 Product data sheet
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer Noise ﬁlter on SCL/SDA inputs Active LOW reset input (RESET) 2 open-drain outputs directly drive LEDs to 25 mA Edge rate control on outputs No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8) Ordering information
[1] Also known as MSOP8. Block diagram
Table 1. Ordering information
Tamb= −40 °C to +85°C
PCA9530D PCA9530 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9530DP 9530 TSSOP8[1] plastic thin shrink small outline package;8 leads; body width3 mm SOT505-1
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer Pinning information
5.1 Pinning
5.2 Pin description Functional description
Refer to Figure 1 “Block diagram”.
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9530 is shown in Figure 4. To conserve power, no
internal pull-up resistoris incorporatedon the hardware selectable address pin andit must
be pulled HIGH or LOW.
Table 2. Pin description 1 address input 0
LED0 2 LED driver 0
LED1 3 LED driver 1
VSS 4 supply ground
RESET 5 active LOW reset input
SCL 6 serial clock line
SDA 7 serial data line
VDD 8 supply voltage
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
The lastbitof the address byte deﬁnes the operationtobe performed. When setto logic1
a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgementof the slave address, the bus master will send
a byte to the PCA9530, which will be stored in the Control register.
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment ﬂag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contentsof these bits will rolloverto ‘000’ after the last register
is accessed.
When Auto-Increment ﬂag is set (AI= 1) and a read sequence is initiated, the sequence
must start by reading a register different from the Input register (B2 B1 B0≠00 0).
Only the 3 least signiﬁcant bits are affected by the AI ﬂag. Unused bits must be
programmed with zeroes.
6.2.1 Control register deﬁnition
Table 3. Register summary 0 0 INPUT read only input register 0 1 PSC0 read/write frequency prescaler 0 1 0 PWM0 read/write PWM register 0 1 1 PSC1 read/write frequency prescaler 1 0 0 PWM1 read/write PWM register 1 0 1 LS0 read/write LED selector
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
6.3 Register descriptions
6.3.1 INPUT - Input register
The INPUT register reﬂects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Remark: The default value‘X’is determinedby the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to VDD.
6.3.2 PCS0 - Frequency Prescaler0
PSC0 is used to program the period of the PWM output.
The period of BLINK0= (PSC0+1)/ 152.
6.3.3 PWM0 - Pulse Width Modulation0
The PWM0 register determines the duty cycleof BLINK0. The outputs are LOW (LED on)
when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If
PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off).
The duty cycle of BLINK0= PWM0/ 256.
6.3.4 PCS1 - Frequency Prescaler1
PSC1 is used to program the period of the PWM output.
The period of BLINK1= (PSC1+1)/ 152.
Table 4. INPUT - Input register description
Table 5. PSC0 - Frequency Prescaler 0 register description
Table 6. PWM0 - Pulse Width Modulation 0 register description
Table 7. PSC1 - Frequency Prescaler 1 register description
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
6.3.5 PWM1 - Pulse Width Modulation1
The PWM1 register determines the duty cycleof BLINK1. The outputs are LOW (LED on)
when the count is less than the value in PWM1 and HIGH (LED off) when it is greater. PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off).
The duty cycle of BLINK1= PWM1/ 256.
6.3.6 LS0 - LED selector
The LS0 LED select register determines the source of the LED data.= output is set high-impedance (LED off; default)= output is set LOW (LED on)= output blinks at PWM0 rate= output blinks at PWM1 rate
6.4 Pins used as GPIOs
LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs).
For use as input, set LEDn to high-impedance (00) and then read the pin state via the
INPUT register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmedas high-impedance, and LOW when the outputis programmed LOW through
the ‘LED selector’ register LS0. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
6.5 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9530 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9530 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device.
Table 8. PWM1 - Pulse Width Modulation 1 register description
Table 9. LS0 - LED selector register bit description
Legend: * default value.
LS0 7:4 1111* reserved
3:2 00* LED1 selected
1:0 00* LED0 selected
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
6.6 External RESET reset canbe accomplishedby holding the RESET pin LOWfora minimumof tw(rst). The
PCA9530 registers and I2 C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to VDD if no active connection is used. Characteristics of the I2 C-bus
TheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure6).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis deﬁnedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP
condition (P) (see Figure 7).
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
7.2 System conﬁguration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 8).
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
7.4 Bus transactions
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer Application design-in information
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 13. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD and is speciﬁed as ΔIDD in Table 12 “Static characteristics”.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater thanor equalto VDD when the LEDis off.
Figure 14 shows a high value resistor in parallel with the LED. Figure 15 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OVI
at or above VDD and prevent additional supply current consumption when the LED is off.
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
8.2 Programming example
The following example will show how to set LED0 to blink at 1 Hz at a 50 % duty cycle.
LED1 will be set to be dimmed at 25 % of their maximum brightness (duty cycle=25 %). Limiting values
Table 10. Programming PCA9530
START S
PCA9530 address with A0= LOW C0h
PSC0 subaddress + Auto-Increment 11h
Set prescaler PSC0 to achieve a period of 1 second:
PSC0= 151
97h
Set PWM0 duty cycle to 50%:
PWM0= 128
80h
Set prescaler PCS1 to dim at maximum frequency:
PSC1=0
00h
Set PWM1 output duty cycle to 25%:
PWM1=64
40h
Set LED0 to PWM0, and set LED1 to blink at PWM1 0Eh
STOP P
Blink period 1 PSC0 1+
152------------------------==
PWM0
256----------------- 0.5=
Blink period max=
PWM1
256----------------- 0.25=
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(LEDn) output current on pin LEDn - +25 mA
ISS ground supply current - 50 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA9530
2-bit I2 C-bus LED dimmer
10. Static characteristics
[1] Typical limits at VDD=3.3 V, Tamb =25°C.
[2] Additional current for one LED I/O at a time where VI=4.3V,
[3] VDD must be lowered to 0.2 V in order to reset part.
[4] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 50 mA.
Table 12. Static characteristics
VDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise speciﬁed.
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD= 5.5 V; no load; =VDD or VSS; fSCL= 100 kHz 350 500 μA
Istb standby current Standby mode; VDD= 5.5 V; no load; =VDDor VSS; fSCL=0 kHz 1.9 5.0 μA
ΔIDD additional quiescent
supply current
Standby mode; VDD= 5.5V;
every LED I/OatVI= 4.3V;
fSCL=0 kHz
[2]- - 200 μA
VPOR power-on reset voltage no load; VI =VDD or VSS [3]- 1.7 2.2 V
Input SCL; input/output SDA
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL= 0.4V 3 6.5 - mA leakage current VI =VDD =VSS −1- +1 μA input capacitance VI =VSS - 3.7 5 pF
I/Os
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL= 0.4V
VDD= 2.3V [4] 9- - mA
VDD= 3.0V [4] 12 - - mA
VDD= 5.0V [4] 15 - - mA
VOL= 0.7V
VDD= 2.3V [4] 15 - - mA
VDD= 3.0V [4] 20 - - mA
VDD= 5.0V [4] 25 - - mA input leakage current VDD= 3.6 V; VI=0 V or VDD −1- +1 μA
Cio input/output capacitance - 2.1 5 pF
Select inputs A0, RESET
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current −1- +1 μA input capacitance VI =VSS - 2.3 5 pF

Partno	Mfg	Dc	Qty	Available	Descript
PCA9530DP	NXP	N/a	2097	avai	2-bit I2C-bus LED dimmer