PCA9517D Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9517D ,Level translating I2C-bus repeaterGeneral descriptionThe PCA9517 is a CMOS integrated circuit that provides level shifting between lo ..
PCA9517DGKR ,Level-Translating I2C Bus Repeater 8-VSSOP -40 to 85 SCPS157E–DECEMBER 2007–REVISED JUNE 20144 Description (Continued)The B-side drivers operate from 2 ..
PCA9517DGKR ,Level-Translating I2C Bus Repeater 8-VSSOP -40 to 85Electrical Characteristics....... 611 Mechanical, Packaging, and Orderable6.6 Timing Requirements.. ..
PCA9517DGKRG4 ,Level-Translating I2C Bus Repeater 8-VSSOP -40 to 855 Pin Configuration and FunctionsD PACKAGE(TOP VIEW)DGK PACKAGE(TOP VIEW)V 1 8 VCCA CCBV VCCA 1 8 C ..
PCA9517DP ,Level translating I2C-bus repeaterFeaturesn 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side oft ..
PCA9517DP.118 , Level translating I2C-bus repeater
PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..

PCA9517D
Level translating I2C-bus repeater
General descriptionThe PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage (downto 0.9V) and higher voltage (2.7Vto 5.5V)I2 C-busor SMBus applications.
While retaining all the operating modes and features of the I2 C-bus system during the
level shifts, it also permits extension of the I2 C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF . Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s canbe connectedin series, A-sideto B-side, withno build-upin offset voltage
with only time of ﬂight delays to consider.
The PCA9517 drivers are not enabled unless VCCAis above 0.8V and VCCis above 2.5V.
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the B-side internal buffer LOW is set for approximately 0.5V,
while the input thresholdof the internal bufferis set about70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3VCCA to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9V. Features2 channel, bidirectional buffer isolates capacitance and allows 400pFon either sideof
the device Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5V Footprint and functional replacement for PCA9515/15AI2 C-bus and SMBus compatible
PCA9517
Level translating I2 C-bus repeater
Rev. 03 — 30 January 2007 Product data sheet
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard mode and Fast mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins A-side operating supply voltage range of 0.9 V to 5.5V B-side operating supply voltage range of 2.7 V to 5.5V5 V tolerant I2 C-bus and enable pins0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater). ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8 and TSSOP8 Ordering information
[1] Also known as MSOP8 Functional diagram
Table 1. Ordering information
Tamb= −40 °C to +85°C
PCA9517D PCA9517 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9517DP 9517 TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater Pinning information
5.1 Pinning
5.2 Pin description Functional description
Refer to Figure 1 “Functional diagram of PCA9517”.
The PCA9517 enables I2 C-bus or SMBus translation down to VCCA as low as 0.9V
without degradation of system performance. The PCA9517 contains two bidirectional
open-drain buffers speciﬁcally designed to support up-translation/down-translation
between the low voltage (as lowas 0.9V) anda 3.3Vor5VI2 C-busor SMBus.All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCCB
and/or VCCA=0 V). The PCA9517 includes a power-up circuit that keeps the output
drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA
can be applied in any sequence at power-up. After power-up and with the enable (EN)
HIGH, a LOW level on the A-side (below 0.3VCCA) turns the corresponding B-side driver
(either SDAor SCL)on and drives the B-side downto about 0.5V. When the A-side rises
above 0.3VCCA the B-side pull-down driver is turned off and the external pull-up resistor
pulls the pin HIGH. When the B-side falls ﬁrst and goes below 0.3VCCB the A-side driveris
turned on and the A-side pulls down to 0 V. The B-side pull-down is not enabled unless
the B-side voltage goes below 0.4V.If the B-side low voltage does notgo below 0.5V, the
A-side driver will turn off when the B-side voltage is above 0.7VCCB. If the B-side low
voltage goes below 0.4 V, the B-side pull-down driver is enabled and the B-side will only
Table 2. Pin description
VCCA 1 A-side supply voltage (0.9 V to 5.5V)
SCLA 2 serial clock A-side bus
SDAA 3 serial data A-side bus
GND 4 supply ground (0V) 5 active HIGH repeater enable input
SDAB 6 serial data B-side bus
SCLB 7 serial clock B-side bus
VCCB 8 B-side supply voltage (2.7 V to 5.5V)
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater
be able to rise to 0.5 V until the A-side rises above 0.3VCCA, then the B-side will continue
to rise being pulled up by the external pull-up resistor. The VCCA is only used to provide
the 0.3VCCA reference to the A-side input comparators and for the power good detect
circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin.
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCCB and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an2 C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2 C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port arein
an idle state to prevent system failures.
6.2I2 C-bus systems
As with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector conﬁguration of the I2 C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
modeI2 C-bus devicesin additionto SMBus devices. Standard modeI2 C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2 C-bus
system where Standard mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note AN255, I2 C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9517 in a system or using the PCA9517 in conjunction with other bus buffers.
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater Application design-in information
A typical application is shown in Figure 4. In this example, the system master is runninga 3.3VI2 C-bus while the slaveis connectedtoa 1.2V bus. Both buses runat 400 kHz.
Master devices can be placed on either bus.
The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When the A-side of the PCA9517 is pulled LOW by a driver on the I2 C-bus, a comparator
detects the falling edge whenit goes below 0.3VCCA and causes the internal driveron the
B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the
PCA9517 falls, ﬁrsta CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus masterin Figure4 wereto writeto the slave through the PCA9517, waveforms shown Figure8 wouldbe observedon theA bus. This looks likea normalI2 C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.
On the B bus side of the PCA9517, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517 for a short delay while the A bus side rises above 0.3VCCA then it continues
HIGH.Itis importantto note that any arbitrationor clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be
recognized by the PCA9517 and then transmitted to the A bus side.
Multiple PCA9517 A-sides canbe connectedina star conﬁguration (Figure5), allowingall
nodes to communicate with each other.
Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is
connected to the B-side. I2 C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-ﬂight considerations on the maximum bus speed requirements.
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCCB supply voltage, B-side bus 2.7 V to 5.5V −0.5 +7 V
VCCA supply voltage, A-side bus adjustable −0.5 +7 V
Vbus voltage on I2 C-bus B-side, or enable (EN) −0.5 +7 V DC current any pin - 50 mA
Ptot total power dissipation - 100 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating in free air −40 +85 °C junction temperature - +125 °C
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater Static characteristics
Table 4. Static characteristics
VCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise speciﬁed.
Supplies
VCCB supply voltage, B-side bus 2.7 - 5.5 V
VCCA supply voltage, A-side bus [1] 0.9 - 5.5 V
ICC(VCCA) supply current on pin VCCA -- 1 mA
ICCH HIGH-state supply current both channels HIGH;
VCC= 5.5V;
SDAn= SCLn= VCC 1.5 5 mA
ICCL LOW-state supply current both channels LOW;
VCC= 5.5V;
one SDA and one SCL= GND;
other SDA and SCL open 1.5 5 mA
ICCAc quiescent supply current in
contention
VCC= 5.5V;
SDAn= SCLn= VCC 1.5 5 mA
Input and output SDAB and SCLB
VIH HIGH-level input voltage 0.7VCCB- 5.5 V
VIL LOW-level input voltage [2] −0.5 - +0.3VCCB V
VILc LOW-level input voltage contention −0.5 0.4 - V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI= 0.2V - - 10 μA
VOL LOW-level output voltage IOL= 100 μA or 6 mA 0.47 0.52 0.6 V
VOL−VILc LOW-level input voltage below
output LOW-level voltage
guaranteed by design - - 70 mV
ILOH HIGH-level output leakage current VO= 3.6V - - 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC= 3.3V - 6 7 pF=3 V or 0 V; VCC =0V - 6 7 pF
Input and output SDAA and SCLA
VIH HIGH-level input voltage 0.7VCCA- 5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCCA V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI= 0.2V - - 10 μA
VOL LOW-level output voltage IOL=6 mA - 0.1 0.2 V
ILOH HIGH-level output leakage current VO= 3.6V - - 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC= 3.3V - 6 7 pF=3 V or 0 V; VCC =0V - 6 7 pF
NXP Semiconductors PCA9517
Level translating I2 C-bus repeater
[1] LOW-level supply voltage.
[2] VIL speciﬁcationisforthe ﬁrst LOW level seenbythe SDAB/SCLB lines. VILcisforthe second and subsequent LOW levels seenbythe
SDAB/SCLB lines.
[3] VIL for A-side with envelope noise must be below 0.3VCCA for stable performance.
10. Dynamic characteristics
[1] Times are speciﬁed with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on the B-side, and 167 Ω pull-up resistance
and 57 pF load capacitance on the A-side. Different load resistance and capacitance will alter the RC time constant, thereby changing
the propagation delay and transition times.
[2] Pull-up voltages are VCCA on the A-side and VCCB on the B-side.
[3] Typical values were measured with VCCA=3.3 V at Tamb =25 °C, unless otherwise noted.
[4] The tPLH delay data from B-sideto A-sideis measuredat0.5Vonthe B-sideto 0.5VCCAonthe A-side when VCCAis less than2V, and
1.5 V on the A-side if VCCA is greater than 2V.
[5] Typical value measured with VCCA=2.7 V at Tamb =25°C.
[6] The proportional delay data from A-side to B-side is measured at 0.3VCCA on the A-side to 1.5 V on the B-side.
[7] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
Enable
VIL LOW-level input voltage −0.5 - +0.3VCCB V
VIH HIGH-level input voltage 0.7VCCB- 5.5 V
IIL(EN) LOW-level input current on pin EN VI= 0.2 V, EN; VCC= 3.6V - −10 −30 μA
ILI input leakage current −1- +1 μA input capacitance VI= 3.0 V or 0V - 6 7 pF
Table 4. Static characteristics …continued
VCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise speciﬁed.
Table 5. Dynamic characteristics
VCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise speciﬁed. [1][2]
tPLH LOW-to-HIGH propagation delay B-side to A-side; Figure12 [4] 100 170 250 ns
tPHL HIGH-to-LOW propagation delay B-side to A-side; Figure10
VCCA≤ 2.7V [5] 30 80 110 ns
VCCA≥3V 10 66 300 ns
tt(LH) LOW-to-HIGH transition time A-side; Figure10 10 20 30 ns
tt(HL) HIGH-to-LOW transition time A-side; Figure10
VCCA≤ 2.7V [5]1 77 105 ns
VCCA≥3V 20 70 175 ns
tPLH LOW-to-HIGH propagation delay A-side to B-side; Figure11 [6] 25 53 110 ns
tPHL HIGH-to-LOW propagation delay A-side to B-side; Figure11 [6] 60 79 230 ns
tt(LH) LOW-to-HIGH transition time B-side; Figure11 120 140 170 ns
tt(HL) HIGH-to-LOW transition time B-side; Figure11 30 48 90 ns
tsu set-up time EN HIGH before START condition [7] 100 - - ns hold time EN HIGH after STOP condition [7] 100 - - ns

Partno	Mfg	Dc	Qty	Available	Descript
PCA9517D	NXP	N/a	1605	avai	Level translating I2C-bus repeater