PCA9517ADP-PCA9517ATP Fast Delivery |IC PHOENIX CO.,LIMITED

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PCA9517ADP-PCA9517ATP
Level translating I虏C-bus repeater
1. General description
The PCA9517A is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2 C-bus or SMBus
applications. While retaining all the operating modes and features of the I2 C-bus system
during the level shifts, it also permits extension of the I2 C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of
400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus
for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus port A drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the port B translating into a nearly 0V
LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),
or PCA9518. Port A of two or more PCA9517As can be connected together, however, to
allow a star topography with port A on the common bus, and port A can be connected
directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can
be connected in series, port A to port B, with no build-up in offset voltage with only time of
flight delays to consider.
The PCA9517A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The EN pin can also be used to turn the drivers on and off under system control.
Caution should be observed to only change the state of the enable pin when the bus is
idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.3VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.9V.
[1] PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system
updates.
[2] The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates
identically and should be used for all new designs and system updates.
PCA9517A
Level translating I2 C-bus repeater
Rev. 4 — 9 May 2012 Product data sheet
Table 1. PCA9517 and PCA9517A comparison
electrostatic discharge, HBM >2kV > 5.5kV
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
2. Features and benefits 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5V Footprint and functional replacement for PCA9515/15AI2 C-bus and SMBus compatible Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins Port A operating supply voltage range of 0.9 V to 5.5V Port B operating supply voltage range of 2.7 V to 5.5V 5V tolerant I2 C-bus and enable pins0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater) ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 and HWSON8
3. Ordering information
[1] Also known as MSOP8.
[2] PCA9517ADP/DG is functionally the same (electrically and mechanically) as the PCA9517ADP, but was initially produced (e.g., “born”)
with Dark Green (lead-free and halogen/antimony-free) package material and is a temporary unique orderable part number for
customers who desire to order and only receive Dark Green package material. The standard part PCA9517ADP will transition to Dark
Green package material in 2Q’12 and then the PCA9517ADP and PCA9517ADP/DG devices will be identical. The PCA9517ADP/DG
part number will be EOL after several years as customers who used this temporary part number update their BOM to the normal part
number.
Table 2. Ordering information
Tamb= −40 °C to +85 °C.
PCA9517AD PA9517A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9517ADP 9517A TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
PCA9517ADP/DG 9517A TSSOP8 [1][2] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
PCA9517ATP 17A HWSON8 plastic thermal enhanced very very thin small outline
package; no leads; 8 terminals; body2×3× 0.8 mm
SOT1069-2
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
4. Functional diagram
5. Pinning information
5.1 Pinning
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
5.2 Pin description
[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9517A”.
The PCA9517A enables I2 C-bus or SMBus translation down to VCC(A) as low as 0.9V
without degradation of system performance. The PCA9517A contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2 C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCC(B)
and/or VCC(A)=0 V). The PCA9517A includes a power-up circuit that keeps the output
drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and
VCC(A) can be applied in any sequence at power-up. After power-up and with the enable
(EN) HIGH, a LOW level on port A (below 0.3VCC(A)) turns the corresponding port B driver
(either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above
0.3VCC(A), the port B pull-down driver is turned off and the external pull-up resistor pulls
the pin HIGH. When port B falls first and goes below 0.3VCC(B) the port A driver is turned
on and port A pulls down to 0 V. The port B pull-down is not enabled unless the portB
voltage goes below 0.4 V. If the port B low voltage does not go below 0.5 V, the portA
driver will turn off when port B voltage is above 0.7VCC(B). If the port B low voltage goes
below 0.4 V, the port B pull-down driver is enabled and port B will only be able to rise to
0.5 V until port A rises above 0.3VCC(A), then port B will continue to rise being pulled up by
the external pull-up resistor. The VCC(A) is only used to provide the 0.3VCC(A) reference to
the port A input comparators and for the power good detect circuit. The PCA9517A logic
and all I/Os are powered by the VCC(B) pin.
Table 3. Pin description
VCC(A) 1 7 port A supply voltage (0.9 V to 5.5V)
SCLA 2 8 serial clock port A bus
SDAA 3 1 serial data port A bus
GND 4 2[1] supply ground (0V) 5 3 active HIGH repeater enable input
SDAB 6 4 serial data port B bus
SCLB 7 5 serial clock port B bus
VCC(B) 8 6 port B supply voltage (2.7 V to 5.5V)
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCC(B) and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an 2 C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2 C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2I2 C-bus systems
As with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2 C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I2 C-bus devices in addition to SMBus devices. Standard mode I2 C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2 C-bus
system where Standard-mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note AN255, I2 C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3V I2 C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
When port A of the PCA9517A is pulled LOW by a driver on the I2 C-bus, a comparator
detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the
bus master in Figure 5 were to write to the slave through the PCA9517A, waveforms
shown in Figure 9 would be observed on the A bus. This looks like a normal I2 C-bus
transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
On the B bus side of the PCA9517A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517A. After the eighth clock pulse, the data line
will be pulled to the VOL of the slave device which is very close to ground in this example.
At the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517A for a short delay while the A bus side rises above 0.3VCC(A) then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517A (VIL) be at or below 0.4 V to be
recognized by the PCA9517A and then transmitted to the A bus side.
Multiple PCA9517A port A sides can be connected in a star configuration (Figure 6),
allowing all nodes to communicate with each other.
Multiple PCA9517As can be connected in series (Figure 7) as long as port A is connected
to port B. I2 C-bus slave devices can be connected to any of the bus segments. The
number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
8. Limiting valuesTable 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC(B) supply voltage portB 2.7 V to 5.5V −0.5 +7 V
VCC(A) supply voltage portA adjustable −0.5 +7 V
VI/O voltage on an input/output pin port A and port B; enable pin (EN) −0.5 +7 V
II/O input/output current port A; portB - 50 mA input current EN, VCC(A), VCC(B), GND - 50 mA
Ptot total power dissipation - 100 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating in free air −40 +85 °C junction temperature - +125 °C
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
9. Static characteristicsTable 5. Static characteristics
VCC= 2.7 V to 5.5 V; GND=0 V; Tamb= −40 °Cto+85 °C; unless otherwise specified.
Supplies
VCC(B) supply voltage portB 2.7 - 5.5 V
VCC(A) supply voltage portA [1] 0.9 - 5.5 V
ICC(VCC(A)) supply current on pin VCC(A) -- 1 mA
ICCH HIGH-level supply current both channels HIGH;
VCC =5.5V;
SDAn= SCLn= VCC
-1.5 5 mA
ICCL LOW-level supply current both channels LOW;
VCC =5.5V;
one SDA and one SCL= GND;
other SDA and SCL open
-1.5 5 mA
ICC(A)c contention port A supply current VCC =5.5V;
SDAn= SCLn= VCC
-1.5 5 mA
Input and output SDAB and SCLB
VIH HIGH-level input voltage 0.7VCC(B) -5.5 V
VIL LOW-level input voltage [2] −0.5 - +0.3VCC(B)V
VILc contention LOW-level input
voltage
−0.5 0.4 - V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI =3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI =0.2V - - 10 μA
VOL LOW-level output voltage IOL =100 μA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
output and LOW-level input
voltage contention
guaranteed by design - - 70 mV
ILOH HIGH-level output leakage
current =3.6V - - 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC =3.3V - 6 7 pF=3 V or 0 V; VCC =0V - 6 7 pF
Input and output SDAA and SCLA
VIH HIGH-level input voltage 0.7VCC(A) -5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCC(A)V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI =3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI =0.2V - - 10 μA
VOL LOW-level output voltage IOL =6mA - 0.1 0.2 V
ILOH HIGH-level output leakage
current =3.6V - - 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC =3.3V - 6 7 pF=3 V or 0 V; VCC =0V - 6 7 pF
NXP Semiconductors PCA9517A
Level translating I2 C-bus repeater
[1] LOW-level supply voltage.
[2] VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAB/SCLB lines.
[3] VIL for port A with envelope noise must be below 0.3VCC(A) for stable performance.
10. Dynamic characteristics
[1] Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on port B, and 167 Ω pull-up resistance and pF load capacitance on port A. Different load resistance and capacitance will alter the RC time constant, thereby changing the
propagation delay and transition times.
[2] Pull-up voltages are VCC(A) on port A and VCC(B) on portB.
[3] Typical values were measured with VCC(A)=3.3 V at Tamb =25 °C, unless otherwise noted.
[4] The tPLH delay data from port B to port A is measured at 0.5 V on port B to 0.5VCC(A) on port A when VCC(A) is less than 2 V, and 1.5V
on port A if VCC(A) is greater than 2V.
[5] Typical value measured with VCC(A) =2.7 V at Tamb =25°C.
[6] The proportional delay data from port A to port B is measured at 0.3VCC(A) on port A to 1.5 V on portB.
[7] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
Enable
VIL LOW-level input voltage −0.5 - +0.3VCC(B)V
VIH HIGH-level input voltage 0.7VCC(B) -5.5 V
IIL(EN) LOW-level input current on
pin EN= 0.2 V, EN; VCC =3.6V - −10 −30 μA
ILI input leakage current −1- +1 μA input capacitance VI =3.0 V or 0V - 6 7 pF
Table 5. Static characteristics …continued
VCC= 2.7 V to 5.5 V; GND=0 V; Tamb= −40 °Cto+85 °C; unless otherwise specified.
Table 6. Dynamic characteristics
VCC= 2.7 V to 5.5 V; GND=0 V; Tamb= −40 °Cto+85 °C; unless otherwise specified. [1][2]
tPLH LOW to HIGH propagation delay port B to port A; Figure13 [4] 100 170 250 ns
tPHL HIGH to LOW propagation delay port B to port A; Figure11
VCC(A)≤ 2.7V [5] 30 80 110 ns
VCC(A)≥ 3V 10 66 300 ns
tTLH LOW to HIGH output transition time port A; Figure11 10 20 30 ns
tTHL HIGH to LOW output transition time port A; Figure11
VCC(A)≤ 2.7V [5] 177 105 ns
VCC(A)≥ 3V 20 70 175 ns
tPLH LOW to HIGH propagation delay port A to port B; Figure12 [6] 25 53 110 ns
tPHL HIGH to LOW propagation delay port A to port B; Figure12 [6] 60 79 230 ns
tTLH LOW to HIGH output transition time port B; Figure12 120 140 170 ns
tTHL HIGH to LOW output transition time port B; Figure12 30 48 90 ns
tsu set-up time EN HIGH before START condition [7] 100 - - ns hold time EN HIGH after STOP condition [7] 100 - - ns

Partno	Mfg	Dc	Qty	Available	Descript
PCA9517ADP	NXP	N/a	7514	avai	Level translating I虏C-bus repeater
PCA9517ATP	NXP	N/a	27004	avai	Level translating I虏C-bus repeater