PCA9516APW ,5-channel I2C-bus hubFeaturesn 5 channel, bidirectional buffer2n I C-bus and SMBus compatiblen Active HIGH individual re ..
PCA9516PW ,5-channel I2C hub
PCA9516PW ,5-channel I2C hub
PCA9517 ,Level translating I2C-bus repeaterGeneral descriptionThe PCA9517 is a CMOS integrated circuit that provides level shifting between lo ..
PCA9517ADP ,Level translating I虏C-bus repeaterFeatures and benefits 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on ei ..
PCA9517ATP ,Level translating I虏C-bus repeaterfeatures of the I C-bus system 2during the level shifts, it also permits extension of the I C-bus b ..
PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PCA9516APW
5-channel I2C-bus hub
General descriptionThe PCA9516A is a CMOS integrated circuit intended for application in I2 C-bus and
SMBus systems.
While retaining all the operating modes and features of the I2 C-bus system, it permits
extension of the I2 C-bus by buffering both the data (SDAn) and the clock (SCLn) lines,
thus enabling five buses of 400 pF.
The I2 C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9516A enables the system designerto divide the bus into five segmentsoff
of a hub where any segment-to-segment transition sees only one repeater delay. can alsobe usedto run different busesat5V and 3.3Vor 400 kHz and 100 kHz buses
where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required.
Two or more PCA9516As cannot be put in series. The PCA9516A design does not
allow this configuration. Since thereisno direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output of each
repeater in the hub. A ‘regular LOW’ applied at the input of a PCA9516A will be
propagated as a ‘buffered LOW’ with a slightly higher value on all the enabled outputs.
When this ‘buffered LOW’ is applied to another PCA9515A, PCA9516A, or PCA9518A in
series, the second PCA9515A, PCA9516A, or PCA9518A will not recognize it as a
‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again. The
PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the
PCA9515A, PCA9516A, or PCA9518A, but can be used in series with themselves since
they use shifting instead of static offsets to avoid lock-up conditions.
Features 5 channel, bidirectional bufferI2 C-bus and SMBus compatible Active HIGH individual repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins Operating supply voltage range of 2.3 V to 3.6V 5.5 V tolerant I2 C-bus and enable pins
PCA9516A
5-channel I2 C-bus hub
Rev. 03 — 23 April 2009 Product data sheet
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub0 Hz to 400 kHz clock frequency1 ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO16 and TSSOP16
Ordering information
3.1 Ordering options The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
Table 1. Ordering informationPCA9516AD SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
PCA9516APW TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Table 2. Ordering optionsPCA9516AD PCA9516AD Tamb= −40 °C to +85°C
PCA9516APW PA9516A Tamb= −40 °C to +85°C
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub Block diagramA more detailed view of Figure 1 buffer is shown in Figure2.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub Pinning information
5.1 Pinning
5.2 Pin description
Table 3. Pin descriptionSCL0 1 serial clock bus 0
SDA0 2 serial data bus 0
SCL1 3 serial clock bus 1
SDA1 4 serial data bus 1
EN1 5 active HIGH bus 1 enable input
SCL2 6 serial clock bus 2
SDA2 7 serial data bus 2
GND 8 supply ground
EN2 9 active HIGH bus 2 enable input
SCL3 10 serial clock bus 3
SDA3 11 serial data bus 3
EN3 12 active HIGH bus 3 enable input
SCL4 13 serial clock bus 4
SDA4 14 serial data bus 4
EN4 15 active HIGH bus 4 enable input
VCC 16 supply power
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub Functional descriptionThe PCA9516A is a five-way hub repeater, which enables I2 C-bus and similar bus
systems to be expanded with only one repeater delay and no functional degradation of
system performance.
The PCA9516A contains five bidirectional, open-drain buffers specifically designed to
support the standard low-level-contention arbitration of the I2 C-bus. Except during
arbitration or clock stretching, the PCA9516A acts like five pairs of non-inverting,
open-drain buffers, one for SDA and one for SCL. Refer to Figure 1 “Block diagram”.
6.1 EnableThe enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.
Each enable pin ENn controlsits associated SDAn and SCLn ports. When LOW, the ENn
pin blocks the inputs from SDAn and SCLn as well as disabling the output drivers on the
SDAn and SCLn pins. The enable pins should only change state when both the global bus
and the local port are in an idle state to prevent system failures.
The active HIGH enable pins allow the useof open-drain drivers which canbe wire-ORed
to create a distributed enable where either centralized control signal (master) or spoke
signal (submaster) can enable the channel when it is idle.
6.2I2 C-bus systemsAs with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector configuration of the I2 C-bus.)
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part is designed to work with Standard-mode and
Fast-modeI2 C-bus devicesin additionto SMBus devices. Standard-modeI2 C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic2 C-bus system where Standard-mode devices and multiple masters are possible. Please
see application note AN255, “I2 C/SMBus Repeaters, Hubs and Expanders” for additional
information on sizing resistors and precautions when using more than one
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction
with the P82B96.
Application design-in informationA typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2 C-bus while the slave is connected to a 5 V bus. All buses run at 100 kHz
unless slave 3 is isolated, and then the master bus and slave 1 and slave 2 can run at
400 kHz.
Any segmentof the hub can talkto any other segmentof the hub. Bus masters and slaves
can be located on all five segments with 400 pF load allowed on each segment.
Unused ports should be isolated by holding the enable pin (ENn) to GND and/or pulling
SDAn/SCLn pins to VCC through appropriately sized resistors. The primary bus master is
normally connected to SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to
be pulled to VCC through appropriately sized resistors.
NXP Semiconductors PCA9516A
5-channel I2 C-bus hubThe PCA9516A is 5.5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9516A is pulled LOW by a device on the I2 C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9516A will typically be at VOL= 0.5V.
In order to illustrate what would be seen in a typical application, refer to Figure 6 and
Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9516A, would see the waveform shownin Figure6on Bus0. This looks likea normalI2 C-bus
transmission until the falling edgeof the8th clock pulse.At that point, the master releases
the data line (SDA) while the slave pullsit LOW through the PCA9516A. Because the VOL the PCA9516Ais typically around 0.5V,a stepin the SDA willbe seen. After the master
has transmitted the 9th clock pulse, the slave releases the data line. the Bus1 sideof the PCA9516A, the clock and data lines would havea positive offset
from ground equalto the VOLof the PCA9516A. After the8th clock pulse, the data line will
be pulled to the VOL of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the VOLof the deviceson Bus1be70 mV below the VOLof the PCA9516A (see VOL−VILc Section 9 “Static characteristics”) to be recognized by the PCA9516A and then
transmitted to Bus0.
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub Limiting values
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to GND.
VCC supply voltage −0.5 +7 V
Vbus voltage range I2 C-bus SCLn or SDAn −0.5 +7 V DC current any pin - 50 mA
Ptot total power dissipation - 300 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub Static characteristics[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] Typical value taken at 3.3 V and 25°C.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
Table 5. Static characteristics (VCC= 3.0 V to 3.6V)VCC= 3.0 V to 3.6V[1]=0 V; Tamb= −40 °C to +85 °C; unless otherwise specified.
SuppliesVCC supply voltage 3.0 - 3.6 V
ICCH HIGH-level supply current both channels HIGH;
VCC= 3.6V;
SDAn= SCLn= VCC 2.1 5 mA
ICCL LOW-level supply current both channels LOW;
VCC= 3.6 V; one SDAn and
one SCLn= GND, other
SDAn and SCLn open 4.7 10 mA
ICCLc contention LOW-level supply current VCC= 3.6V;
SDAn= SCLn= GND 4.0 10 mA
Input SCLn; input/output SDAnVIH HIGH-level input voltage 0.7VCC- 5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] −0.5 - +0.4 V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V −1- +1 μA
IIL LOW-level input current SDAn, SCLn; VI= 0.2V - - 5 μA
VOL LOW-level output voltage IOL=0 mA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
output and LOW-level input voltage
contention
guaranteed by design - - 70 mV input capacitance VI=3 V or 0V - 6 10 pF
Enable inputs EN1 to EN4VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL LOW-level input current EN1 to EN4; VI= 0.2V - −12 −30 μA
ILI input leakage current −1- +1 μA input capacitance VI=3 V or 0V - 6 7 pF
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] Typical value taken at 2.5 V and 25°C.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
Table 6. Static characteristics (VCC= 2.3 V to 2.7V)VCC= 2.3 V to 2.7V[1]=0 V; Tamb= −40 °C to +85 °C; unless otherwise specified.
SuppliesVCC supply voltage 2.3 - 2.7 V
ICCH HIGH-level supply current both channels HIGH;
VCC= 2.7V;
SDAn= SCLn= VCC 2.1 5 mA
ICCL LOW-level supply current both channels LOW;
VCC= 2.7 V; one SDAn and
one SCLn= GND, other
SDAn and SCLn open 4.6 10 mA
ICCLc contention LOW-level supply current VCC= 2.7V;
SDAn= SCLn= GND 3.9 10 mA
Input SCLn; input/output SDAnVIH HIGH-level input voltage 0.7VCC- 5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] −0.5 - +0.4 V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 2.7V −1- +1 μA
IIL LOW-level input current SDAn, SCLn; VI= 0.2V - - 5 μA
VOL LOW-level output voltage IOL=0 mA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
output and LOW-level input voltage
contention
guaranteed by design - - 70 mV input capacitance VI=3 V or 0V - 6 10 pF
Enable inputs EN1 to EN4VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 1.5 - 5.5 V
IIL LOW-level input current EN1 to EN4; VI= 0.2V - −10 −30 μA
ILI input leakage current −1- +1 μA input capacitance VI=3 V or 0V - 6 7 pF
NXP Semiconductors PCA9516A
5-channel I2 C-bus hub
10. Dynamic characteristics[1] Typical value taken at 2.5 V and 25°C.
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
[1] Typical value taken at 3.3 V and 25°C.
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Table 7. Dynamic characteristics (VCC= 2.3 V to 2.7V)VCC =2.3 V to 2.7 V; GND=0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure8 45 93 150 ns
tPLH LOW to HIGH propagation delay Figure8 [2] 33 90 135 ns
tTHL HIGH to LOW output transition time Figure8 -60 - ns
tTLH LOW to HIGH output transition time Figure8 [2]- 131 - ns
tsu set-up time ENn to START condition 100 - - ns hold time ENn after STOP condition 130 - - ns
Table 8. Dynamic characteristics (VCC= 3.0 V to 3.6V)VCC =3.0 V to 3.6 V; GND=0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure8 45 75 120 ns
tPLH LOW to HIGH propagation delay Figure8 [2] 33 60 83 ns
tTHL HIGH to LOW output transition time Figure8 -47 - ns
tTLH LOW to HIGH output transition time Figure8 [2]- 130 - ns
tsu set-up time ENn to START condition 100 - - ns hold time ENn after STOP condition 100 - - ns
