PCA9515ADP ,I虏C-bus repeaterfeatures of the I C-bus system, it permits 2extension of the I C-bus by buffering both the data (SD ..
PCA9515ADR ,Dual Bidirectional I2C Bus and SMBus Repeater 8-SOIC -40 to 85Featuresnumber of devices and bus length. Using the1• Two-Channel Bidirectional BuffersPCA9515A ena ..
PCA9515ADT ,Dual Bidirectional I2C Bus and SMBus Repeater 8-SOIC -40 to 85features of theSON (8) 3.00 mm × 3.00 mm2I C system. This enables two buses of 400-pF bus2(1) For a ..
PCA9515APW ,Dual Bidirectional I2C Bus and SMBus Repeater 8-TSSOP -40 to 85Maximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
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PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
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PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PCA9515ADP
I虏C-bus repeater
1. General descriptionThe PCA9515A is a CMOS integrated circuit intended for application in I2 C-bus and
SMBus systems.
While retaining all the operating modes and features of the I2 C-bus system, it permits
extension of the I2 C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
enabling two buses of 400 pF.
The I2 C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus
more devices or longer length can be accommodated. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the
100 kHz bus is isolated when 400 kHz operation of the other is required.
Two or more PCA9515As cannot be put in series. The PCA9515A design does not allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output. A ‘regular
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with
themselves since they use shifting instead of static offsets to avoid lock-up conditions.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
2. Features and benefits 2-channel, bidirectional bufferI2 C-bus and SMBus compatible Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins Operating supply voltage range of 2.3 V to 3.6V 5.5 V tolerant I2 C-bus and enable pins
PCA9515A2 C-bus repeater
Rev. 5 — 23 March 2012 Product data sheet
NXP Semiconductors PCA9515A2 C-bus repeater0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater) ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8), HWSON8
3. Ordering information[1] Also known as MSOP8.
4. Functional diagram
Table 1. Ordering informationTamb= 40 C to +85 C.
PCA9515AD PA9515A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9515ADP 9515A TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
PCA9515ATP 15A HWSON8 plastic thermal enhanced very very thin small outline package; leads; 8 terminals; body23 0.8 mm
SOT1069-2
NXP Semiconductors PCA9515A2 C-bus repeater
5. Pinning information
5.1 Pinning
5.2 Pin description[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Table 2. Pin descriptionn.c. 1 7 not connected
SCL0 2 8 serial clock bus 0; open-drain 5 V tolerant I/O
SDA0 3 1 serial data bus 0; open-drain 5 V tolerant I/O
GND 4 2[1] supply ground (0V) 5 3 active HIGH repeater enable input
(internal pull-up with 100 k)
SDA1 6 4 serial data bus 1; open-drain 5 V tolerant I/O
SCL1 7 5 serial clock bus 1; open-drain 5 V tolerant I/O
VCC 8 6 supply voltage
NXP Semiconductors PCA9515A2 C-bus repeater
6. Functional descriptionRefer to Figure 1 “Functional diagram of PCA9515A”.
The PCA9515A integrated circuit contains two identical buffer circuits which enable 2 C-bus and similar bus systems to be extended without degradation of system
performance.
The PCA9515A contains two bidirectional, open-drain buffers specifically designed to
support the standard LOW-level contention arbitration of the I2 C-bus. Except during
arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain
buffers, one for SDA and one for SCL.
6.1 EnableThe EN pin is active HIGH with an internal pull-up and allows the user to select when the
repeater is active. This can be used to isolate a badly behaved slave on power-up until
after the system power-up reset. It should never change state during an I2 C-bus operation
because disabling during a bus operation will hang the bus and enabling part way through
a bus cycle could confuse the I2 C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2I2 C-bus systemsAs with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2 C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard-mode and
Fast-mode I2 C-bus devices in addition to SMBus devices. Standard-mode I2 C-bus
devices only specify 3 mA output drive; this limits the termination current to 3 mA in a
generic I2 C-bus system where Standard-mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used.
Please see Application Note AN255, I2 C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction
with the P82B96.
NXP Semiconductors PCA9515A2 C-bus repeater
7. Application design-in informationA typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2 C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515A is pulled LOW by a device on the I2 C-bus, a CMOS
hysteresis type input detects the falling edge and causes the internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515A will typically be at VOL =0.5V.
In order to illustrate what would be seen in a typical application, refer to Figure 6 and
Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9515A,
we would see the waveform shown in Figure 6 on bus 0. This looks like a normal I2 C-bus
transmission until the falling edge of the eighth clock pulse. At that point, the master
releases the data line (SDA) while the slave pulls it LOW through the PCA9515A.
Because the VOL of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen.
After the master has transmitted the ninth clock pulse, the slave releases the data line.
On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9515A. After the eighth clock pulse the data line
will be pulled to the VOL of the slave device, which is very close to ground in this example.
It is important to note that any arbitration or clock stretching events on bus 1 require that
the VOL of the PCA9515A (see VOLVILc in Section 9 “Static characteristics”) to be
recognized by the PCA9515A and then transmitted to bus0.
NXP Semiconductors PCA9515A2 C-bus repeater
8. Limiting values
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
VCC supply voltage 0.5 +7 V
VI2C-bus I2 C-bus voltage SCL or SDA 0.5 +7 V
II/O input/output current DC; any pin - 50 mA
Ptot total power dissipation - 100 mW
Tstg storage temperature 55 +125 C
Tamb ambient temperature operating in free air 40 +85 C
NXP Semiconductors PCA9515A2 C-bus repeater
9. Static characteristics[1] For operation between published voltage ranges (Table 4 for VCC=3.0 V to 3.6 V; Table 5 for VCC=2.3 V to 2.7 V), refer to worst-case
parameter in both ranges.
[2] Typical value taken at VCC=3.3 V and Tamb =25C.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
Table 4. Static characteristics (VCC =3.0 V to 3.6V)VCC= 3.0 V to 3.6V[1]=0 V; Tamb= 40 Cto +85 C; unless otherwise specified.
SuppliesVCC supply voltage 3.0 - 3.6 V
ICCH HIGH-level supply current both channels HIGH;
VCC =3.6V;
SDAn= SCLn= VCC
-0.8 5 mA
ICCL LOW-level supply current both channels LOW;
VCC =3.6V;
one SDA and one SCL= GND;
other SDA and SCL open
-1.7 5 mA
ICCLc contention LOW-level supply current VCC =3.6V;
SDAn= SCLn= GND
-1.6 5 mA
Input SCLn; input/output SDAnVIH HIGH-level input voltage 0.7VCC -5.5 V
VIL LOW-level input voltage [3] 0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] 0.5 - +0.4 V
VIK input clamping voltage II= 18 mA - - 1.2 V
ILI input leakage current VI =3.6V 1- +1 A
IIL LOW-level input current SDAn, SCLn; VI =0.2V - - 5 A
VOL LOW-level output voltage IOL =20 A or 6 mA 0.47 0.52 0.6 V
VOLVILc difference between LOW-level output
and LOW-level input voltage
contention
guaranteed by design - - 70 mV input capacitance VI =3V or 0V - 6 7 pF
EnableVIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL(EN) LOW-level input current on pin EN VI= 0.2 V - 10 30 A
ILI input leakage current 1- +1 A input capacitance VI= 3.0 V or 0V - 6 7 pF
NXP Semiconductors PCA9515A2 C-bus repeater[1] For operation between published voltage ranges (Table 4 for VCC=3.0 V to 3.6 V; Table 5 for VCC=2.3 V to 2.7 V), refer to worst-case
parameter in both ranges.
[2] Typical value taken at VCC=2.5 V and Tamb =25C.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
Table 5. Static characteristics (VCC =2.3 V to 2.7V)VCC= 2.3 V to 2.7V[1]=0 V; Tamb= 40 Cto +85 C; unless otherwise specified.
SuppliesVCC supply voltage 2.3 - 2.7 V
ICCH HIGH-level supply current both channels HIGH;
VCC =2.7V;
SDAn= SCLn= VCC
-0.8 5 mA
ICCL LOW-level supply current both channels LOW;
VCC =2.7V;
one SDA and one SCL= GND;
other SDA and SCL open
-1.6 5 mA
ICCLc contention LOW-level supply current VCC =2.7V;
SDAn= SCLn= GND
-1.6 5 mA
Input SCLn; input/output SDAnVIH HIGH-level input voltage 0.7VCC -5.5 V
VIL LOW-level input voltage [3] 0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] 0.5 - +0.4 V
VIK input clamping voltage II= 18 mA - - 1.2 V
ILI input leakage current VI =2.7V 1- +1 A
IIL LOW-level input current SDAn, SCLn; VI =0.2V - - 10 A
VOL LOW-level output voltage IOL =20 A or 6 mA 0.47 0.52 0.6 V
VOLVILc difference between LOW-level output
and LOW-level input voltage
contention
guaranteed by design - - 70 mV input capacitance VI =3V or 0V - 6 7 pF
EnableVIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL(EN) LOW-level input current on pin EN VI= 0.2 V - 10 30 A
ILI input leakage current 1- +1 A input capacitance VI= 3.0 V or 0V - 6 7 pF
NXP Semiconductors PCA9515A2 C-bus repeater
10. Dynamic characteristics[1] Typical values taken at VCC=2.5 V and Tamb =25C.
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
[1] Typical values taken at VCC=3.3 V and Tamb =25C.
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
10.1 AC waveforms
Table 6. Dynamic characteristics (VCC= 2.3 V to 2.7V)VCC= 2.3 V to 2.7 V; GND=0 V; Tamb= 40 Cto+85 C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure8 45 82 130 ns
tPLH LOW to HIGH propagation delay Figure8 [2] 33 113 190 ns
tTHL HIGH to LOW output transition time Figure8 -57 - ns
tTLH LOW to HIGH output transition time Figure8 [2] -148 - ns
tsu set-up time EN HIGH before START condition 100 - - ns hold time EN HIGH after STOP condition 130 - - ns
Table 7. Dynamic characteristics (VCC= 3.0 V to 3.6V)VCC= 3.0 V to 3.6 V; GND=0 V; Tamb= 40 Cto+85 C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure8 45 68 120 ns
tPLH LOW to HIGH propagation delay Figure8 [2] 33 102 180 ns
tTHL HIGH to LOW output transition time Figure8 -58 - ns
tTLH LOW to HIGH output transition time Figure8 [2] -147 - ns
tsu set-up time EN HIGH before START condition 100 - - ns hold time EN HIGH after STOP condition 100 - - ns
NXP Semiconductors PCA9515A2 C-bus repeater
11. Test information
