PCA9512AD ,Level shifting hot swappable I虏C-bus and SMBus bus bufferApplications cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required t ..
PCA9512ADP ,Level shifting hot swappable I虏C-bus and SMBus bus bufferGeneral description2The PCA9512A/B is a hot swappable I C-bus and SMBus buffer that allows I/O card ..
PCA9512BDP ,Level shifting hot swappable I虏C-bus and SMBus bus bufferFeatures and benefits Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SD ..
PCA9512DP ,Level shifting hot swappable I2C and SMBus buffer
PCA9513ADP ,Hot swappable I2C-bus and SMBus bus bufferFeaturesn Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA andSCL corr ..
PCA9514AD ,Hot swappable I2C-bus and SMBus bus bufferapplications5. Ordering informationTable 2. Ordering informationT = - 40 °C to +85 °CambType number ..
PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
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PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PCA9512AD-PCA9512ADP-PCA9512BDP
Level shifting hot swappable I虏C-bus and SMBus bus buffer
1. General descriptionThe PCA9512A/B is a hot swappable I2 C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A/B provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs.
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to
minimize the current required to charge the parasitic capacitance of the chip.
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows
them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in
parallel and to the I2 C compliant side of static offset bus buffers, but not to the static offset
side of those bus buffers.
2. Features and benefits Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems Compatible with I2 C-bus Standard mode, I2 C-bus Fast mode, and SMBus standards Built-in V/t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with
ability to disable V/t rise time accelerator through the ACC pin for lightly loaded
systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2)
to be the same5 V to 3.3 V level translation with optimum noise margin High-impedance SDAn and SCLn pins for VCCor VCC2 =0V1 V precharge on all SDAn and SCLn pins Supports clock stretching and multiple master arbitration and synchronization
PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
Rev. 6 — 1 March 2013 Product data sheet
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer Operating power supply voltage range: 2.7 V to 5.5V0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
4. Feature selectionTable 1. Feature selection chartIdle detect yes yes yes yes yes
High-impedance SDAn, SCLn pins for VCC=0V yesyesyes yesyes
Rise time accelerator circuitry on SDAn and SCLn pins- yes yes yes yes
Rise time accelerator circuitry hardware disable pin for
lightly loaded systems
--yes --
Rise time accelerator threshold 0.8 V versus 0.6V
improves noise margin
--- yes yes
Ready open-drain output yes yes - yes yes
Two VCC pins to support 5 V to 3.3 V level translation
with improved noise margins
--yes -- V precharge on all SDAn and SCLn pins in only yes yes - - A current source on SCLIN and SDAIN for PICMG
applications
--- yes -
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
5. Ordering information[1] Also known as MSOP8.
5.1 Ordering options
Table 2. Ordering informationPCA9512AD PA9512A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9512BD PA9512B
PCA9512ADP 9512A TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9512BDP 9512B
Table 3. Ordering optionsPCA9512AD PCA9512AD,112 SO8 standard marking *
IC’s tube- DSC bulk pack
2000 Tamb= 40 C to +85C
PCA9512AD,118 SO8 reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 C to +85C
PCA9512BD PCA9512BD,118 SO8 reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 C to +85C
PCA9512ADP PCA9512ADP ,118 TSSOP8 reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 C to +85C
PCA9512BDP PCA9512BDP ,118 TSSOP8 reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 C to +85C
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
6. Block diagramNXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
7.2 Pin description
8. Functional descriptionRefer to Figure 1 “Block diagram of PCA9512A/B”.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs. Customers should continue using the PCA9512A or move
to the PCA9512A during the next refresh if they are currently using the PCA9512B.
Description of the PCA9512A operation applies equally to the PCA9512B for the
remainder of this data sheet.
8.1 Start-upWhen the PCA9512A is powered up, either VCC or VCC2 may rise first, within a short time
of each other and either may be more positive or they may be equal, however the
PCA9512A will not leave the undervoltage lockout or initialization state until both VCC and
VCC2 have gone above 2.5 V. If either VCC or VCC2 drops below 2.0 V it will return to the
undervoltage lockout state.
Table 4. Pin descriptionVCC2 1 Supply voltage for devices on the card I2 C-bus. Connect pull-up resistors
from SDAOUT and SCLOUT to this pin.
SCLOUT 2 serial clock output to and from the SCL bus on the card
SCLIN 3 serial clock input to and from the SCL bus on the backplane
GND 4 ground supply; connect this pin to a ground plane for best results.
ACC 5 CMOS threshold digital input pin that enables and disables the rise time
accelerators on all four SDAn and SCLn pins. ACC enables all accelerators
when set to VCC2, and turns them off when set to GND.
SDAIN 6 serial data input to and from the SDA bus on the backplane
SDAOUT 7 serial data output to and from the SDA bus on the card
VCC 8 supply voltage; from the backplane, connect pull-up resistors from SDAIN
and SCLIN to this pin.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus bufferIn the undervoltage lockout state the connection circuitry is disabled, the rise time
accelerators are disabled, and the precharge circuitry is also disabled. After both VCC and
VCC2 are valid, independent of which is higher, the PCA9512A/B enters the initialization
state; during this state the 1 V precharge circuitry is activated and pulls up the SDAn and
SCLn pins to 1 V through individual 100 k nominal resistors. At the end of the
initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn
and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a
STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is
disabled when the connection is made, unless the ACC pin is LOW; the rise time
accelerators are enabled at this time also.
8.2 Connect circuitryOnce the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that
isolates the input bus capacitance from the output bus capacitance while communicating.
If VCC VCC2, then a level shifting function is performed between input and output. A LOW
forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the
PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7VCC and VCC
on the SDAIN and SCLIN pins, and 0.7VCC2 and VCC2 on the SDAOUT and SCLOUT pins
is generally ignored because a falling edge is only recognized when it falls below 0.7VCC
for SDAIN and SCLIN (or 0.7VCC2 for SDAOUT and SCLOUT pins) with a slew rate of at
least 1.25 V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a
pull-down driver that is referenced to a small voltage above the falling pin. The driver will
pull the pin down at a slew rate determined by the driver and the load. The first falling pin
may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial
pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then
the second pin will be pulled down at its initial slew rate only until it is just above the first
pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving, that pin will rise and rise above
the nominal offset voltage until the internal driver catches up and pulls it back down to the
offset voltage. This bounce is worst for low capacitances and low resistances, and may
become excessive. When the last external driver stops driving a LOW, that pin will bounce
up and settle out just above the other pin as both rise together with a slew rate determined
by the internal slew rate control and the RC time constant. As long as the slew rate is at
least 1.25 V/s, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are
turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time
accelerator circuits will be disabled, but the pull-down driver will still turn off.
8.3 Maximum number of devices in seriesEach buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher
temperatures. Maximum offset (Voffset) is 0.150 V with a 10 k pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I2 C-bus specification of 3 mA will produce VOL< 0.4 V, although if
lightly loaded the VOL may be ~0.1 V. Assuming VOL= 0.1 V and Voffset= 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus bufferrising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and bufferB
in series as shown in Figure 4. Consider if the VOL at the input of buffer A is 0.3 V and the
VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
Slave B and then from Slave B to Master. Before the direction change you would observe
VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output
of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ~0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and bufferC
would see a false clock rather than a stretched clock, which would cause a system error.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
8.4 Propagation delaysThe delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The tPLH may be
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The tPHL can never be negative because the output does not start to fall until the input is
below 0.7VCC (or 0.7VCC2 for SDAOUT and SCLOUT), and the output turn-ON has a
non-zero delay, and the output has a limited maximum slew rate, and even if the input
slew rate is slow enough that the output catches up it will still lag the falling voltage of the
input by the offset voltage. The maximum tPHL occurs when the input is driven LOW with
zero delay and the output is still limited by its turn-on delay and the falling edge slew rate.
The output falling edge slew rate is a function of the internal maximum slew rate which is
a function of temperature, VCC or VCC2 and process, as well as the load current and the
load capacitance.
8.5 Rise time acceleratorsDuring positive bus transactions, a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded.
The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators.
The built-in V/t rise time accelerators on all SDA and SCL lines requires the bus pull-up
voltage and respective supply voltage (VCC or VCC2) to be the same. The built-in V/t
rise time accelerators can be disabled through the ACC pin for lightly loaded systems.
8.6 ACC boost current enableUsers having lightly loaded systems may wish to disable the rise time accelerators.
Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn
pins. Driving this pin to the VCC2 voltage enables normal operation of the rise time
accelerators.
8.7 Resistor pull-up value selectionThe system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/s on the SDAn and SCLn pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value using the formula given in
Equation1:
(1)
where RPU is the pull-up resistor value in , VCC(min) is the minimum VCC voltage in volts,
and C is the equivalent bus capacitance in picofarads.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus bufferIn addition, regardless of the bus capacitance, always choose RPU 65.7 k for
VCC= 5.5 V maximum, RPU45 k for VCC= 3.6 V maximum. The start-up circuitry
requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the
card, and these pull-up values are needed to overcome the precharge voltage. See the
curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
8.8 Hot swapping and capacitance buffering applicationFigure 7 through Figure 9 illustrate the usage of the PCA9512A in applications that take
advantage of both its hot swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the backplane, all of the
backplane and card capacitances would add directly together, making rise time and
fall time requirements difficult to meet. Placing a bus buffer on the edge of each card,
however, isolates the card capacitance from the backplane. For a given I/O card, the
PCA9512A drives the capacitance of everything on the card and the backplane must drive
only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and
all additional cards on the backplane.
See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on
applications and technical assistance.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus bufferNXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
8.9 Voltage level translator discussion
8.9.1 SummaryThere are two popular configurations for the interface of low voltage logic (i.e., core
processor with 3.3 V supply) to standard bus levels (i.e., I2 C-bus with 5 V supply). A single
FET transistor and two additional resistors may be used effectively, or an
application-specific IC part requiring no external components and no additional resistors.
The FET solution becomes problematic as the low voltage logic levels trend downwards.
The FET solution will stop working completely when the FET specification is no longer
matched to the LOW level logic supply voltage requirements.
The dominant advantage of the FET solution is cost, but the IC part provides additional
advantages to the design, which increases reliability to the end user.
8.9.2 Why do level translation?Advances in processing technology require lower supply voltages, due to reduced
clearances in the fabrication technology. Lower supply voltages drive down signal swings,
or require that on die high voltage I/O sections are added, creating larger die area, or
greater I/O pin count. Existing standards for interoperability of equipment connected by
cables or between subsystems require higher voltage signal swings (typically 5 V).
An external voltage level translator solves these problems, but requires additional parts.
8.10 Limitations of the FET voltage level translator
8.10.1 VGSth, gate-source threshold voltageWhen the VA input is logic LOW, the FET is turned on, pulling VB output LOW. This can
only occur when the threshold voltage of the FET is less than the VA supply voltage minus
the maximum level of the VA signal, VAIL. Using CMOS logic thresholds of 0.3 and
0.7 times the supply, and a 1.1 V VA gives a worst-case of just 330 mV, much less than
VGSth of the popular 2N7002 FET.
VGSth; ID = 250 A; VDS =VGS; 1.1 V (min.)/1.6 V (typ.)/2.1 V (max.)
Additionally, the FET threshold voltage is specified in the linear region of the FET, with
weak conduction. Ideally the FET should have very low ON-resistance. For the 2N7002,
this is specified at 5 V VGS (not the 1 V available in this application). Note that the
ON-resistance decreases rapidly as VGS is increased beyond the VGSth specification.
Unintended operation in the linear region further compromises logic level noise immunity.
8.10.2 FET body diode voltageThe FET is required to conduct in both directions, as the I2C-bus is bidirectional. When
the VB input is logic LOW, the body diode of the FET conducts first, pulling the FET
source LOW along with the FET drain, until the FET conducts. During this transition the
forward voltage drop of the body diode reduces the available FET gain to source bias. The
body diode is specified:
VSD, source-drain voltage; IS =115 mA; VGS=0 V; 0.47 V (min.)/0.75 V (typ.)/1.1V
(max.)
Conduction of the FET body diode impacts both the delay time and logic transition speed.
NXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
8.11 Additional system compromises Additional parts
Additional assembly cost
Reduced system reliability due to complexity
Reduced logic level noise margin (immunity)
Sensitivity to ground offsets between sub-systems (cable links, for example)
Increased loading on the low voltage side (must carry the high voltage side
sink current)
ESD robustness
9. Application design-in informationNXP Semiconductors PCA9512A; PCA9512B
Level shifting hot swappable I2 C-bus and SMBus bus buffer
10. Limiting values[1] Card side supply voltage.
[2] Maximum current for inputs.
[3] Maximum current for I/O pins.
11. Characteristics
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +7 V
VCC2 supply voltage 2[1] 0.5 +7 V voltage on any other pin 0.5 +7 V input current [2]- 20 mA
II/O input/output current [3]- 50 mA
Toper operating temperature 40 +85 C
Tstg storage temperature 65 +125 C
Tsp solder point temperature 10 s maximum - 300 C
Tj(max) maximum junction temperature - 125 C
Table 6. CharacteristicsVCC = 2.7 V to 5.5 V; Tamb= 40 C to +85 C; unless otherwise specified.
Power supplyVCC supply voltage [1] 2.7 - 5.5 V
VCC2 supply voltage 2[2] [1] 2.7 - 5.5 V
ICC supply current VCC =5.5V;
VSDAIN =VSCLIN =0V
-1.8 3.6 mA
ICC2 supply current 2 VCC =5.5V;
VSDAOUT =VSCLOUT =0V
-1.7 2.9 mA
Start-up circuitryVpch precharge voltage SDA, SCL floating [1] 0.8 1.1 1.2 V
ten enable time on power-up [3]- 180 - s
tidle idle time [1][4] 50 140 250 s
Rise time acceleratorsItrt(pu) transient boosted pull-up
current
positive transition on SDA, SCL;
VACC =0.7 VCC2; VCC =2.7V;
slew rate= 1.25 V/s
[5][6] 12 - mA
Vth(dis)(ACC) disable threshold voltage pin ACC
0.3VCC2 0.5VCC2 -V
Vth(en)(ACC) enable threshold voltage pin ACC
-0.5VCC2 0.7VCC2 V
II(ACC) input current on pin ACC 1 0.1 +1 A
tPD(on/off)(ACC) on/off propagation delay pin ACC - ns
