PCA9502BS Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9502BS ,8-bit I/O expander with I2C-bus/SPI interfaceApplicationsn Factory automation and process controln Portable and battery operated devicesn Cellul ..
PCA9504A ,Glue chip 4
PCA9504A ,Glue chip 4
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PCA9506BS ,40-bit I2C-bus I/O port with RESET, OE and INTFeatures and benefits2 Standard mode (100 kHz) and Fast mode (400 kHz) compatible I C-bus serial i ..
PCA9506DGG ,40-bit I2C-bus I/O port with RESET, OE and INTApplications Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gami ..
PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..

PCA9502BS
8-bit I/O expander with I2C-bus/SPI interface
General descriptionThe PCA9502isan 8-bit I/O expander withI2 C-bus/SPI host interface. The device comes
in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery
operated applications.
The device also supports software reset, which allows the host to reset the device at any
time, independent of the hardware reset signal. Features
2.1 General features Selectable I2 C-bus or SPI interface 3.3 V or 2.5 V operation Industrial temperature range: −40 °C to +85°C Eight programmable I/O pins Software reset Industrial and commercial temperature ranges Available in HVQFN24 package 16 hardware-selectable slave addresses
2.2I2 C-bus features Noise ﬁlter on SCL/SDA inputs 400 kbit/s (maximum) Compliant with I2 C-bus Fast-mode Slave mode only
2.3 SPI features 15 Mbit/s maximum speed Slave mode only SPI Mode 0 Applications Factory automation and process control Portable and battery operated devices Cellular data devices
PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
Rev. 03 — 13 October 2006 Product data sheet
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface Ordering information Block diagram
Table 1. Ordering information
PCA9502BS HVQFN24 plastic thermal enhanced very thin quadﬂat package; leads; 24 terminals; body 4×4× 0.85 mm
SOT616-3
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
RESET 1 I device hardware reset (active LOW)[1]
VDD 2,3, 11,
22, 24 power supply
I2C/SPI 4 I I2 C-busor SPI interface select.I2 C-bus interfaceis selectedif this
pin is at logic HIGH. SPI interface is selected if this pin is at logic
LOW.
CS/A0 5 I SPI chip select or I2 C-bus device address select A0. If SPI
conﬁguration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt trigger, active LOW). If I2 C-bus conﬁguration
is selected by I2C/SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SI/A1 6 I SPI data input pin or I2 C-bus device address select A1. If SPI
conﬁgurationis selectedby I2C/SPI pin, thisis the SPI data input
pin. If I2 C-bus conﬁguration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to Table 11. 7 O SPI data output pin. If SPI conﬁguration is selected by I2C/SPI
pin, this is a 3-stateable output pin. If I2 C-bus conﬁguration is
selected by I2C/SPI pin, this pin function is undeﬁned and must
be left as n.c. (not connected).
SCL/SCLK 8 I I2 C-bus or SPI input clock.
SDA 9 I/O I2 C-bus data input/output, open-drain if I2 C-bus conﬁguration is
selected by I2C/SPI pin. If SPI conﬁguration is selected then this
pin is an undeﬁned pin and must be connected to VSS.
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
[1] See Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset” Functional description
The device interfacestoa host through eitherI2 C-busor SPI interface (selectable through
I2C/SPI pin), and provides the host with eight programmable GPIO pins.
7.1 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registersas indicatedin
Table3.
Table 3 summarizes the state of registers after reset.
Table 4 summarizes the state of hardware pins after reset.
IRQ 12 O Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the I/O Interrupt Enable register
(IOIntEna). The interrupt condition is the change of state of the
input pins. An external resistor (1 kΩ for 3.3 V, 1.5kΩ for 2.5V)
must be connected between this pin and VDD.
GPIO0 13 I/O programmable I/O pin
GPIO1 14 I/O programmable I/O pin
GPIO2 15 I/O programmable I/O pin
GPIO3 16 I/O programmable I/O pin
GPIO4 18 I/O programmable I/O pin
GPIO5 19 I/O programmable I/O pin
GPIO6 20 I/O programmable I/O pin
GPIO7 21 I/O programmable I/O pin
VSS 10, 17, ground
VSS center
pad The center pad on the back side of the HVQFN24 package is
metallic and shouldbe connectedto groundon the printed-circuit
board.
Table 2. Pin description …continued
Table 3. Registers after reset
I/O direction all bits cleared
I/O interrupt enable all bits cleared
I/O control all bits cleared
Table 4. Signals after reset
I/Os inputs
IRQ HIGH by external pull-up
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
7.2 Interrupts
The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)
enables interrupts due to I/O pin change of state, and the IRQ signal in response to an
interrupt generation. Register descriptions
The programming combinations for register selection are shown in Table5.
[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).
[2] These bits are reserved and should be set to 0.
8.1 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to
GPIO7.
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.
Table 5. Register map - read/write properties
IODir I/O pin direction I/O pin direction
IOState I/O pin states n/a
IOIntEna I/O interrupt enable register I/O interrupt enable register
IOControl I/O pins control I/O pins control
Table 6. PCA9502 internal registers
General Register Set
Table 7. IODir register (address 0x0A) bit description
7:0 IODir set GPIO pins 7:0 to input or output= input= output
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
8.2 Programmable I/O pins State register (IOState)
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding IO pin programmed as output.
8.3 I/O Interrupt Enable register (IOIntEna)
This register enables the interrupt due to a change in the I/O conﬁgured as inputs.
8.4 I/O Control register (IOControl)
Table 8. IOState register (address 0x0B) bit description
7:0 IOState Write this register: set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register: return states of all pins
Table 9. IOIntEna register (address 0x0C) bit description
7:0 IOIntEna input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
Table 10. IOControl register (address 0x0E) bit description
7:4 - reserved for future use SReset software reset
A write to this bit will reset the device. Once the device is reset this
bit is automatically set to 0.
2:1 - reserved for future use IOLatch enable/disable inputs latching= input values are not latched.A changein any input generatesan
interrupt.A readof the input register clears the interrupt.If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
Example: If GPIO4 input was as logic 0 and the input goes to logic1
then back to logic 0, the IOState register will capture this change and
an interrupt is generated (if enabled). When the read is performed on
the IOState register, the interruptis de-asserted, assuming there were
no additional input(s) that changed, and bit 4 of the IOState register
will read ‘1’. The next read of the IOState register should now read ‘0’.
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface I2 C-bus operation
The two linesof theI2 C-bus area serial data line (SDA) anda serial clock line (SCL). Both
lines are connectedtoa positive supply viaa pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously,a passive function likean LCD driver could onlybea receiver, whilea
microcontroller or a memory can both transmit and receive data.
9.1 Data transfers
One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changesin the data lineat this time willbe interpretedas control signals.A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH deﬁnes a STOP
condition (see Figure5). The busis consideredtobe busy after the START condition and
free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most signiﬁcantbit ﬁrst, andis followedbyan acknowledge bit.
(see Figure6). The clock pulse relatedto the acknowledgebitis generatedby the master.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse, while the transmitting device releases this pulse (see Figure 7).
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There is an exception to the ‘acknowledge after every byte’ rule. It occurs when a master
is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
9.2 Addressing and transfer formats
Each deviceon the bus hasits own unique address. Before any datais transmittedon the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
ﬁrst byte transmitted by the master after the ST ART condition. addresson the networkis seven bits long, appearingas the most signiﬁcant bitsof the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in Figure8.
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
Whenan addressis sent, each devicein the system compares the ﬁrst seven bits after the
START with its own address. If there is a match, the device will consider itself addressed
by the master, and will send an acknowledge. The device could also determine if in this
transactionitis assigned the roleofa slave receiveror slave transmitter, dependingon the
R/W bit.
Each node of the I2 C-bus network has a unique seven-bit address. The address of a
microcontroller is of course fully programmable, while peripheral devices usually have
ﬁxed and programmable address portions.
When the master is communicating with one device only, data transfers follow the format Figure8, where the R/Wbit could indicate either direction. After completing the transfer
and issuinga STOP condition,ifa master would liketo address some other deviceon the
network, it could start another transaction by issuing a new START.
Another wayfora masterto communicate with several different devices wouldbeby using
a ‘repeated START’. After the last byte of the transaction was transferred, including its
acknowledge (or negative acknowledge), the master issues another START, followed by
address byte and data, without effecting a STOP . The master may communicate with a
number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes
place, the master issues a STOP and releases the bus. Possible data formats are
demonstratedin Figure9. Note that the repeated START allowsfor both changeofa slave
anda changeof direction, without releasing the bus. We shall see lateron that the change
of direction feature can come in handy even when dealing with a single device.
In a single master system, the repeated START mechanism may be more efﬁcient than
terminating each transfer with a STOP and starting again. In a multimaster environment,
the determinationof which formatis more efﬁcient couldbe more complicated,as whena
master is using repeated ST ARTs it occupies the bus for a long time and thus preventing
other devices from initiating transfers.
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
9.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The ﬁrst byte after the ST ART condition carries the address of
the slave device and the read/write bit.T able 11 shows how the PCA9502’s address can
be selected by using A1 and A0 pins. For example, if these 2 pins are connected to VDD,
then the PCA9502’s addressis setto 0x90, and the master communicates withit through
this address.
[1] X = logic 0 for write cycle; X = logic 1 for read cycle.
9.4 Use of sub-addresses
When a master communicates with the PCA9502 it must send a sub-address in the byte
following the slave address byte. This sub-addressis the internal addressof the word the
master wants to access for a single byte transfer, or the beginning of a sequence of
locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device
address,it does not containa direction (R/W) bit, and like any byte transferredon the bus
it must be followed by an acknowledge.
A register write cycle is shown in Figure 10. The START is followed by a slave address
byte with the directionbit setto ‘write’,a sub-address byte,a numberof data bytes, anda
STOP signal. The sub-address indicates which register the master wants to access. and
the data bytes which follow will be written one after the other to the sub-address location.
Table 11. PCA9502 address map
VDD VDD 0x90 (1001 000X)
VDD VSS 0x92 (1001 001X)
VDD SCL 0x94 (1001 010X)
VDD SDA 0x96 (1001 011X)
VSS VDD 0x98 (1001 100X)
VSS VSS 0x9A (1001 101X)
VSS SCL 0x9C (1001 110X)
VSS SDA 0x9E (1001 111X)
SCL VDD 0xA0 (1010 000X)
SCL VSS 0xA2 (1010 001X)
SCL SCL 0xA4 (1010 010X)
SCL SDA 0xA6 (1010 011X)
SDA VDD 0xA8 (1010 100X)
SDA VSS 0xAA (1010 101X)
SDA SCL 0xAC (1010 110X)
SDA SDA 0xAE (1010 111X)
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
The register read cycle (see Figure 11) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then,in orderto reverse the directionof the transfer, the master issuesa repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followedbya negative acknowledge, signalling the endof transfer. The cycleis terminated
by a STOP signal.
Table 12. Register address byte (I2 C-bus) - not used
6:3 A[3:0] internal register select
2:1 - not used, set to 0 - not used
NXP Semiconductors PCA9502
8-bit I/O expander with I2 C-bus/SPI interface
10. SPI operation
11. Limiting values
[1] 5.5V steady state voltage toleranceon inputs and outputsis valid only whenthe supply voltageis present.
4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.
Table 13. Register address byte (SPI)
7R/W 1: read from PCA9502
0: write to PCA9502
6:3 A[3:0] internal register select
2:1 - not used, set to 0 - not used
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.3 +4.6 V input voltage any input −0.3 +5.5[1] V input current any input −10 +10 mA output current any output −10 +10 mA
Ptot total power dissipation - 300 mW
P/out power dissipation per output - 50 mW
Tamb ambient temperature −40 +85 °C
Tstg storage temperature −65 +150 °C

Partno	Mfg	Dc	Qty	Available	Descript
PCA9502BS	NXP	N/a	2970	avai	8-bit I/O expander with I2C-bus/SPI interface