PCA9501D-PCA9501PW Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9501D ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pinsApplicationsn Board version tracking and conﬁgurationn Board health monitoring and status reporting ..
PCA9501PW ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501PW ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501PW ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pinsGeneral descriptionThe PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM.The I/O expa ..
PCA9502BS ,8-bit I/O expander with I2C-bus/SPI interfaceApplicationsn Factory automation and process controln Portable and battery operated devicesn Cellul ..
PCA9504A ,Glue chip 4
PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..

PCA9501D-PCA9501PW
8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
General descriptionThe PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM.
The I/O expandable eight quasi-bidirectional data pins canbe independently assignedas
inputsor outputsto monitor board level statusor activate indicator devices suchas LEDs.
The system master writes to the I/O conﬁguration bits in the same way as for the
PCF8574. The data for each input or output is kept in the corresponding input or output
register. The system master can read all registers.
The EEPROM can be used to store error codes or board manufacturing data for
read-back by application software for diagnostic purposes and are included in the I/O
expander package.
The PCA9501 active LOW open-drain interrupt output is activated when any input state
differs from its corresponding input port register state. It is used to indicate to the system
master that an input state has changed and the device needs to be interrogated.
The PCA9501 has six address pins with internal pull-up resistors allowing up to devices to share the common two-wire I2 C-bus software protocol serial data bus. The
ﬁxed GPIO address starts with ‘0’ and the ﬁxed EEPROM I2 C-bus address starts with ‘1’,
so the PCA9501 appears as two separate devices to the bus master.
The PCA9501 supports hot insertion to facilitate usage in removable cards on backplane
systems. Features 8 general purpose input/output expander/collector Replacement for PCF8574 with integrated 2-kbit EEPROM Internal 256× 8 EEPROM Self timed write cycle (5 ms typical) 16 byte page write operationI2 C-bus and SMBus interface logic Internal power-on reset Noise ﬁlter on SCL/SDA inputs Active LOW interrupt output 6 address pins allowing up to 64 devices on the I2 C-bus/SMBus No glitch on power-up Supports hot insertion Power-up with all channels conﬁgured as inputs
PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit
EEPROM and 6 address pins
Rev. 04 — 10 February 2009 Product data sheet
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Low standby current Operating power supply voltage range of 2.5 V to 3.6V5 V tolerant inputs/outputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO20, TSSOP20, HVQFN20 Applications Board version tracking and conﬁguration Board health monitoring and status reporting Multi-card systems in telecom, networking, and base station infrastructure equipment Field recall and troubleshooting functions for installed boards General-purpose integrated I/O with memory Replacement for PCF8574 with integrated 2-kbit EEPROM Bus master sees GPIO and EEPROM as two separate devices Six hardware address pins allow up to 64 PCA9501s to be located in the same2 C-bus/SMBus Ordering information
4.1 Ordering options
Table 1. Ordering information
PCA9501D SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
PCA9501PW TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
PCA9501BS HVQFN20 plastic thermal enhanced very thin quad ﬂat package; leads; 20 terminals; body5×5× 0.85 mm
SOT662-1
Table 2. Ordering options
PCA9501D PCA9501D −40 °C to +85°C
PCA9501PW PCA9501 −40 °C to +85°C
PCA9501BS 9501 −40 °C to +85°C
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Block diagram Pinning information
6.1 Pinning
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
6.2 Pin description
[1] HVQFN20 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal padthe board andfor proper heat conduction throughthe board, thermal vias needtobe incorporatedinthe
printed-circuit board in the thermal pad region.
Table 3. Pin description 1 19 address lines (internal pull-up) 2 20 3 1 12 10 11 9 9 7
IO0 4 2 quasi-bidirectional I/O pins
IO1 5 3
IO2 6 4
IO3 7 5
IO4 13 11
IO5 14 12
IO6 15 13
IO7 16 14
INT 8 6 active LOW interrupt output (open-drain)
VSS 10 8[1] supply ground 17 15 active LOW write control pin
SCL 18 16 I2 C-bus serial clock
SDA 19 17 I2 C-bus serial data
VDD 20 18 supply voltage
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Functional description
Refer also to Figure 1 “Block diagram of PCA9501”.
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9501 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware-selectable address pins.
The lastbitof the address byte deﬁnes the operationtobe performed. When setto logic1
a read is selected, while a logic 0 selects a write operation.
Remark: ReservedI2 C-bus addresses mustbe used with caution since they can interfere
with: Reserved for future use I2 C-bus addresses (0000 011, 1111 1xx) Slave devices that use the 10-bit addressing scheme (1111 0xx) Slave devices that are designed to respond to the General Call address (0000 000) Hs-mode master code (0000 1xx)
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.2 Control register
The PCA9501 contains a single 8-bit register called the Control register, which can be
written and read via the I2 C-bus. This register is sent after a successful acknowledgment
of the slave address.
It contains the I/O operation information.
7.3 I/O operations
(Refer also to Figure 5.)
Each of the PCA9501's eight I/Os can be independently used as an input or output.
Output datais transmittedto the portby the I/O Write mode (see Figure 7). Input I/O data
is transferred from the port to the microcontroller by the Read mode (see Figure 8).
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.3.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switchedoffby the negative edgeof SCL. The I/Os shouldbe HIGH before being usedas
inputs. See Figure9.
7.3.2 Interrupt
The PCA9501 provides an open-drain output (INT) which can be fed to a corresponding
input of the microcontroller. This gives these chips a type of master function which can
initiate an action elsewhere in the system. See Figure 10. interruptis generatedby any risingor falling edgeof the port inputsin the input mode.
After time tv(INT) the signal INT is valid. See Figure 11.
Resetting and reactivating the interrupt circuit is achieved when data on the port is
changed to the original setting or data is read from or written to the port which has
generated the interrupt.
Resetting occurs as follows: In the Read mode at the acknowledge bit after the rising edge of the SCL signal In the Write modeat the acknowledgebit after the HIGH-to-LOW transitionof the SCL
signal Returning of the port data to its original setting Interrupts which occur during the acknowledge clock pulse maybe lost (or very short)
due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting will be detected and, after the next rising clock
edge, willbe transmittedas INT. Reading fromor writingto another device does not affect
the interrupt circuit.
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4 Memory operations
7.4.1 Write operations
Write operations require an additional address ﬁeld to indicate the memory address
location to be written. The address ﬁeld is eight bits long providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and ‘page
write’.
Write operationis possible when the Write Control pin (WC)is putata LOW logic level (0).
When this control signalis setat1, write operationis not possible and datain the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
7.4.1.1 Byte write performa byte write, the START conditionis followedby the memory slave address and
the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9501 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycleto the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4.1.2 Page write page writeis initiatedin the same wayas the byte write,if after sending the ﬁrst wordof
data the STOP condition is not received, the PCA9501 considers subsequent words as
data. After each data word the PCA9501 responds withan acknowledge and the four least
signiﬁcant bits of the memory address ﬁeld are incremented. Should the master not send
a STOP condition after 16 data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
7.4.2 Read operations
PCA9501 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
7.4.2.1 Current address read
The PCA9501 contains an internal address counter that increments after each read or
write access andasa result,if the last word accessed wasat address‘n’ then the address
counter contains the address ‘n+1’.
When the PCA9501 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address storedin the address counter. The master ceases the transmissionby issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4.2.2 Random read
The PCA9501’s random read mode allows the addresstobe read fromtobe speciﬁedby
the master. This is done by performing a dummy write to set the address counter to the
location to be read. The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the acknowledge from the
PCA9501, the master re-issues the START condition and memory slave address with the
R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed location. The master
ceases the transmission by issuing the STOP condition after the eighth bit, omitting the
ninth clock cycle acknowledge.
7.4.2.3 Sequential read
The PCA9501 sequential read is an extension of either the current address read or
random read. If the master does not issue a STOP condition after it has received the
eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the
address counter and use the next eight cyclesto transmit the data from that location. The
master can continue this process to read the contents of the entire memory. Upon
reaching address 255 the counter will return to address 0 and continue transmitting data
until a STOP condition is received. The master ceases the transmission by issuing the
STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Characteristics of the I2 C-bus
TheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 17).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis deﬁnedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP
condition (P) (see Figure 18).
8.2 System conﬁguration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 19).
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Application design-in information
A central processor/controller typically located on the system main board can use the
400 kHz I2 C-bus/SMBus to poll the PCA9501 devices located on the system cards for
status or version control type of information. The PCA9501 may be programmed at
manufacturing to store information regarding board build, ﬁrmware version, manufacturer
identiﬁcation, conﬁguration option data, andso on. Alternately, these devices canbe used convenient interfacefor board conﬁguration, thereby utilizing theI2 C-bus/SMBusasan
intra-system communication bus
NXP Semiconductors PCA9501
8-bit I2 C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
10. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +4.0 V input voltage VSS− 0.5 5.5 V input current −20 +20 mA output current −25 +25 mA
IDD supply current −100 +100 mA
ISS ground supply current −100 +100 mA
Ptot total power dissipation - 400 mW
P/out power dissipation per output - 100 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C

Partno	Mfg	Dc	Qty	Available	Descript
PCA9501D	NXP	N/a	2000	avai	8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501PW	NXP	N/a	18	avai	8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins