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PCA9501PW ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
PCA9501PW ,8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins
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PCA9500PW
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
Product data
Supersedes data of 27 Sep 2002
2003 Jun 27
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
FEATURES 8 general purpose input/output expander/collector Drop in replacement for PCF8574 with integrated 2-kbit EEPROM Internal 256 × 8 EEPROM Self timed write cycle 4 byte page write operation I2C and SMBus interface logic Internal power-on reset Noise filter on SCL/SDA inputs 3 address pins allowing up to 8 devices on the I2C/SMBus No glitch on power-up Supports hot insertion Power-up with all channels configured as inputs Low standby current Operating power supply voltage range of 2.5 V to 3.6 V 5 V tolerant inputs/outputs 0 to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA Package offerred: SO16, TSSOP16, HVQFN16
DESCRIPTIONThe PCA9500 is an 8-bit I/O expander with an on-board 2-kbit
EEPROM.
The I/O expander’s eight quasi bidirectional data pins can be
independently assigned as inputs or outputs to monitor board level
status or activate indicator devices such as LEDs. The system
master writes to the I/O configuation bits in the same way as for the
PCF8574. The data for each Input or Output is kept in the
corresponding Input or Output register. The system master can read
all registers.
The EEPROM can be used to store error codes or board
manufacturing data for read-back by application software for
diagnostic purposes and is included in the I/O expander package.
The PCA9500 has three address pins with internal pull-up resistors
allowing up to 8 devices to share the common two-wire I2C software
protocol serial data bus. The fixed GPIO I2C address is the same as
the PCF8574 and the fixed EEPROM I2C address is the same as
the PCF8582C-2, so the PCA9500 appears as two separate devices
to the bus master.
The PCA9500 supports hot insertion to facilitate usage in removable
cards on backplane systems.
The PCA9501 is an alternative to the functionally similar PCA9500
for systems where a higher number of devices are required to share
the same I2C-bus or an interrupt output is required.
ORDERING INFORMATIONStandard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2 C patent.
I2C is a trademark of Philips Semiconductors Corporation.
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
PIN CONFIGURATION - SO, TSSOP
Figure 1. Pin configuration - SO, TSSOP
PIN CONFIGURATION - HVQFN
Figure 2. Pin configuration - HVQFN
PIN DESCRIPTION
BLOCK DIAGRAM
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
FUNCTIONAL DESCRIPTION
Figure 4. Simplified schematic diagram of each I/O
DEVICE ADDRESSINGFollowing a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.
Figure 5. PCA9500 slave addressesThe last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write
operation.
CONTROL REGISTERThe PCA9500 contains a single 8-bit register called the Control Register, which can be written and read via the I2 C-bus. This register is sent
after a successful acknowledgment of the slave address.
It contains the I/O operation information.
I/O OPERATIONS (see also Figure 4)Each of the PCA9500’s eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE
mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
Figure 6. I/O WRITE mode (output)
Figure 7. I/O READ mode (input)
Quasi-bidirectional I/Os (see Figure 8)A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.
In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs.
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before
being used as inputs.
Figure 8. Transient pull-up current IOHt while I/O3 changes from LOW-to-HIGH and back to LOW
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
MEMORY OPERATIONS
Write operationsWrite operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long, providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.
Write operation is possible when WC control pin put at a low logic
level (0). When this control signal is set at 1, write operation is not
possible and data in the memory is protected.
Byte Write and Page Write explained below assume that Write
Control pin (WC) is set to 0.
Byte Write (see Figure 9)To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PCA9500 will respond
with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the
data. The PCA9500 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
Quasi-bidirectional I/O are allowed during the internal write cycle.
Page Write (see Figure 10)A page write is initiated in the same way as the byte write. If after
sending the first word of data, the stop condition is not received the
PCA9500 considers subsequent words as data. After each data
word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after four data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.
Figure 9. Byte write
Figure 10. Page Write
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
Read operationsPCA9500 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address’
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.
Current Address Read (see Figure 11)The PCA9500 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.
When the PCA9500 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.
Random Read (see Figure 12)The PCA9500’s random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PCA9500 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PCA9500 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Sequential Read (see Figure 13)The PCA9500 sequential read is an extension of either the current
address read or random read. If the master doesn’t issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PCA9500 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Figure 11. Current Address Read
Figure 12. Random Read
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
CHARACTERISTICS OF THE I2 C-BUSThe I2 C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transferOne data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 14).
Start and stop conditionsBoth data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 15).
System configurationA device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 16).
Figure 14. Bit transfer
Figure 15. Definition of start and stop conditions
Figure 16. System configuration
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
Acknowledge (see Figure 17)The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set-up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
Figure 17. Acknowledgment on the I2 C-bus
Philips Semiconductors Product data
PCA95008-bit I2 C and SMBus I/O port with 2-kbit EEPROM
TYPICAL APPLICATION
Applications Board version tracking and configuration Board health monitoring and status reporting Multi-card systems in Telecom, Networking, and Base Station
Infrastructure Equipment Field recall and troubleshooting functions for installed boards General-purpose integrated I/O with memory Drop in replacement for PCF8574 with integrated 2-kbit EEPROM Bus master sees GPIO and EEPROM as two separate devices Three hardware address pins allow up to 8 PCA9500s to be
located in the same I2 C/SMBus
Figure 18. Typical applicationA central processor/controller typically located on the system main
board can use the 400 kHz I2C/SMBus to poll the PCA9500 devices
located on the system cards for status or version control type of
information. The PCA9500 may be programmed at manufacturing to
store information regarding board build, firmware version,
manufacturer identification, configuration option data… Alternately,
these devices can be used as convenient interface for board
configuration, thereby utilizing the I2C/SMBus as an intra-system
communication bus.
