PCA8575PW ,Remote 16-bit I/O expander for I2C-bus with interruptApplicationsn LED signs and displaysn Serversn Industrial controln Medical equipmentn PLCsn Cellula ..
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PCA8575PW
Remote 16-bit I/O expander for I2C-bus with interrupt
General descriptionThe PCA8575 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional I2 C-bus (serial clock (SCL), serial data (SDA)).
The device consists of a 16-bit quasi-bidirectional port and an I2 C-bus interface. The
PCA8575 has a low current consumption and includes latched outputs with high current
drive capability for directly driving LEDs.
The PCA8575 also possesses an interrupt line (INT) which can be connected to the
interrupt logicof the microcontroller.By sendingan interrupt signalon this line, the remote
I/O can inform the microcontroller if there is incoming data on its ports without having to
communicate via the I2 C-bus. The internal Power-On Reset (POR) initializes the I/Os as
inputs.
Features 400 kHz I2 C-bus interface 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 16-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 400 mA Active LOW open-drain interrupt output 8 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current (10 μA max.) −40 °C to +85 °C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA Packages offered: SO24, SSOP24 (QSOP24), TSSOP24, HVQFN24, DHVQFN24
Applications LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones
PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
Rev. 02 — 21 March 2007 Product data sheet
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt Gaming machines Instrumentation and test measurement
Ordering information[1] Also known as QSOP24.
Block diagram
Table 1. Ordering informationPCA8575D PCA8575D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA8575DB PCA8575DB SSOP24 plastic shrink small outline package;24 leads; body width 5.3 mm SOT340-1
PCA8575DK PCA8575 SSOP24[1] plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
SOT556-1
PCA8575PW PCA8575PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA8575BQ 8575 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad
flat package; no leads; 24 terminals; body 3.5× 5.5× 0.85 mm
SOT815-1
PCA8575BS 8575 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 4×4× 0.85 mm
SOT616-1
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt Pinning information
6.1 Pinning
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
6.2 Pin description[1] HVQFN and DHVQFN packagedie supply groundis connectedto boththe VSSpin andthe exposed center
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 2. Pin descriptionINT 1 22 interrupt output (active LOW)
AD1 2 23 address input 1
AD2 3 24 address input 2
P00 4 1 quasi-bidirectional I/O 00
P01 5 2 quasi-bidirectional I/O 01
P02 6 3 quasi-bidirectional I/O 02
P03 7 4 quasi-bidirectional I/O 03
P04 8 5 quasi-bidirectional I/O 04
P05 9 6 quasi-bidirectional I/O 05
P06 10 7 quasi-bidirectional I/O 06
P07 11 8 quasi-bidirectional I/O 07
VSS 12[1] 9[1] supply ground
P10 13 10 quasi-bidirectional I/O 10
P11 14 11 quasi-bidirectional I/O 11
P12 15 12 quasi-bidirectional I/O 12
P13 16 13 quasi-bidirectional I/O 13
P14 17 14 quasi-bidirectional I/O 14
P15 18 15 quasi-bidirectional I/O 15
P16 19 16 quasi-bidirectional I/O 16
P17 20 17 quasi-bidirectional I/O 17
AD0 21 18 address input 0
SCL 22 19 serial clock line input
SDA 23 20 serial data line input/output
VDD 24 21 supply voltage
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt Functional descriptionRefer to Figure 1 “Block diagram of PCA8575”.
7.1 Device addressFollowing a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA8575 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 3 “PCA8575 address map”.
Remark: The General Call address (0000 0000b) and the Device ID address
(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this
requirement will cause the PCA8575 not to acknowledge.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is
applied.
7.1.1 Address map
Table 3. PCA8575 address map010000020h
010000121h
010001022h
010001123h
010010024h
010010125h
010011026h
010011127h
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt I/O programming
8.1 Quasi-bidirectional I/O architectureThe PCA8575’s 16 ports (see Figure 2) are entirely independent and can be used either
as input or output ports. Input data is transferred from the ports to the microcontroller in
the Read mode (see Figure 12). Output datais transmittedto the portsin the Write mode
(see Figure 11).
Every data transmission from the PCA8575 must consistofan even numberof bytes, the
first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third
will be referred to as P07 to P00, and so on.
This quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data directions. At power-on the I/Os are HIGH. In this mode only a current
source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising
edges into heavily loaded outputs. These devices turnon whenan outputis written HIGH,
and are switchedoffby the negative edgeof SCL. The I/Os shouldbe HIGH before being
used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as
inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the
Write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large
current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the Write mode is entered. The
PCA8575 acknowledges and the master sends the first data bytefor P07to P00. After the
first data byteis acknowledgedby the PCA8575, the second data byte P17to P10is sent the master. Once again, the PCA8575 acknowledges the receiptof the data. Each 8-bit
data is presented on the port lines after it has been acknowledged by the PCA8575.
The number of data bytes that can be sent successively is not limited. After every two
bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data
byte in every pair refers to Port 1 (P17 to P10). See Figure 10.
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
8.3 Reading from a port (Input mode)All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.
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NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
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NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
8.4 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8575 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA8575 registers andI2 C-bus/SMBus state machine will initializeto their default
states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)The PCA8575 providesan open-drain interrupt (INT) which canbe fedtoa corresponding
input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these
chips a kind of master function which can initiate an action elsewhere in the system. interruptis generatedby any risingor falling edgeof the port inputs. After time tv(D) the
signal INT is valid.
The interrupt disappears when dataon the portis changedto the original settingor datais
read from or written to the device which has generated the interrupt. the Write mode, the interrupt may become deactivated (HIGH)on the rising edgeof the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the Read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interruptis reset any changein I/Os willbe detected and transmittedas INT.
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
9.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis definedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16.)
9.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
9.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications the 8-bit I/O expander application shownin Figure 19, P00 and P01 are inputs, and P02
to P07 are outputs. When used in this configuration, during a write, the input (P00 and
P01) must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to
P07). During a read, the logic levels of the external devices driving the input ports (P00
and P01) and the previous written logic level to the output ports (P02 to P07) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microprocessor.By sendingan interrupt signalon this line, the remote I/O informs the
microprocessor that thereis incoming dataora changeof dataonits ports without having
to communicate via the I2 C-bus.
10.2 High current-drive load applicationsThe GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
NXP Semiconductors PCA8575
Remote 16-bit I/O expander for I2 C-bus with interrupt
10.3 Differences between the PCA8575 and the PCF8575The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical software modifications, but thereisa differencein interrupt output release timing during
the read operation.
Write operations are identical. At the completion of each 8-bit write sequence the data is
stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n
while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n
then P1n again. Any write will update both read registers and clear interrupts.
Read operations are identical. Both devices update the byte register with the pin data as
each 8-bit read is initiated, the very first read after an address cycle corresponds to ports
P0n while the second (even byte) corresponds to P1n and subsequent reads without a
STOP wrap around to P0n then P1n again.
During read operations, the PCA8575 interrupt output will be cleared in a byte-wise
fashion as each byte is read. Reading the first byte will clear any interrupts associated
with the P0n pins. This first byte read operation will haveno effecton interrupts associated
with changes of state on the P1n pins. Interrupts associated with the P1n pins will be
cleared when the second byte is read. Reading the second byte has no effect on
interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt
output will clear after reading both bytesof data regardlessof whether data was changed
in the first byte or the second byte or both bytes.
11. Limiting values[1] Total package (maximum) output current is 600 mA.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6 V
IDD supply current - ±100 mA
ISS ground supply current - ±600 mA input voltage VSS− 0.5 5.5 V input current - ±20 mA output current - ±50[1] mA
Ptot total power dissipation - 600 mW
P/out power dissipation per output - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
