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PCA8550D-PCA8550PW
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM DIP switch
Product data
Supersedes data of 2001 Jan 12
2003 Jun 27
Philips Semiconductors Product data
PCA85504-bit multiplexed/1-bit latched 5-bit 2 C EEPROM DIP switch
FEATURES 4-bit 2-to-1 multiplexer, 1-bit latch DIP switch 5-bit internal non-volatile register Override input forces all outputs to logic 0 Internal non-volatile register write/readable via I2 C-bus Write-protect pin enables/disables I2 C writes to register 2.5 V multiplexed outputs 3.3 V non-multiplexed output (latched) 5 V tolerant inputs Useful for ‘jumperless’ configuration of PC motherboards Designed for use in Pentium Pro/Pentium II systems
DESCRIPTIONThe primary function of the 4-bit 2-to-1 I2 C multiplexer is to select
either a 4-bit input or data from a non-volatile register and drive this
value onto the output pins. One additional non-multiplexed register
output is also provided. The non-multiplexed output is latched to
prevent output value changes during I2 C writes to the non-volatile
register. A write protect input is provided to enable/disable the ability
to write to the non-volatile register. An “override” input feature forces
all outputs to logic 0.
PIN CONFIGURATION
Figure 1. Pin configuration
ORDERING INFORMATIONStandard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
FUNCTIONAL DESCRIPTIONWhen the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE_N signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
The write protect (WP) input is used to control the ability to write the
contents of the 5-bit non-volatile register. If the WP signal is logic 0,
the I2C-bus will be able to write the contents of the non-volatile
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the
I2C bus (described in the next section).
The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have
internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
Philips Semiconductors Product data
PCA85504-bit multiplexed/1-bit latched 5-bit 2 C EEPROM DIP switch
PIN DESCRIPTION
FUNCTION TABLE
Table 1. Function table
NOTE Latched NON_MIXED_OUT state will be the value present on
the NON_MUXED_OUT output at the time of the MUX_SELECT
input transitioned from a logic 0 to a logic 1 state.
2 C INTERFACECommunicating with this device is initiated by sending a valid
address on the I2 C-bus. The address format (see FIgure 2) is a fixed
unique 7-bit value followed by a 1-bit read/write value which
determines the direction of the data transfer.
Figure 2. I2C Address ByteFollowing the address and acknowledge bit are 8 data bits which,
depending on the read/write bit in the address, will read data from or
write data to the non-volatile register. Data will be written to the
register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The three
high-order bits (see FIgure 3) are logic 0. The next bit is data which
is non-multiplexed. The low four bits are the data which will be
multiplexed. A write with any of the first three bits non-zero will be
aborted.
NOTE: To ensure data integrity, the non-volatile register must be
internally write protected when VCC to the I2C-bus is powered
down or VCC to the component is dropped below normal
operating levels.
Figure 3. I2 C Data Byte
POWER-ON RESET (POR)When power is applied to VCC, an internal power-on reset holds the
PCA8550 in a reset state until VCC has reached VPOR. At that point,
the reset condition is released and the PCA8550 volatile registers
and I2 C state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
the OVERRIDE_N and MUX_SELECT logic levels
the previously stored values in the EEPROM register/current
MUX_IN pin values as shown in Table 1.
Philips Semiconductors Product data
PCA85504-bit multiplexed/1-bit latched 5-bit 2 C EEPROM DIP switch
BLOCK DIAGRAM
Figure 4. Block diagram
Philips Semiconductors Product data
PCA85504-bit multiplexed/1-bit latched 5-bit 2 C EEPROM DIP switch
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product data
PCA85504-bit multiplexed/1-bit latched 5-bit 2 C EEPROM DIP switch
DC CHARACTERISTICSTemp = 0 to +70 °C 3.0 V < VCC ≤ 3.6 V
NOTES: VHYS is the hysteresis of Schmitt-Trigger inputs Human body model
NON-VOLATILE STORAGE SPECIFICATIONSApplication Note AN250 I2C DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles.
