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PC16552DV
Dual Universal Asynchronous Receiver/Transmitter with FIFO's
TL/C/9426
PC16552D
Dual
Universal
Asynchronous
Receiver/Transmitter
with
FIFOs
June 1995
PC16552D
Dual Universal Asynchronous
Receiver/Transmitter with FIFOs²
General Description
The PC16552Disa dual versionofthe PC16550DUniversal
AsynchronousReceiver/Transmitter (UART).Thetwo serial
channelsare completely independent exceptfora common
CPU interfaceand crystal input.On power-upboth channels
are functionally identicaltothe 16450*. Each channelcan
operate with on-chip transmitterand receiver FIFOs (FIFO
mode)to relievethe CPUof excessive software overhead. FIFOmode each channel iscapableof buffering16 bytes
(plus3bitsof error dataper bytein theRCVR FIFO)of data boththe transmitter and receiver.Allthe FIFO control
logicis on-chipto minimize system overheadand maximize
system efficiency.
Signallingfor DMA transfersis done throughtwo pinsper
channel (TXRDYand RXRDY).The RXRDY functionis mul-
tiplexedon onepin withthe OUT2 and BAUDOUT func-
tions. The CPUcan select these functions througha new
register (Alternate Function Register).
Each channel performs serial-to-parallel conversionon data
characters received froma peripheral deviceora MODEM,
and parallel-to-serial conversionon data charactersre-
ceived fromthe CPU. The CPU can readthe complete
statusof each channelatany time. Status informationre-
ported includesthe typeand conditionof thetransfer opera-
tions being performedbythe DUART,aswellasany error
conditions (parity, overrun, framing,or break interrupt).
The DUART includesone programmable baudrate genera-
torfor each channel. Eachis capableof dividingthe clock
inputby divisorsof1to (216b1),and producinga16c
clockfor drivingthe internal transmitter logic. Provisionsare
also includedtousethis16c clockto drivethe receiver
logic. TheDUARThas complete MODEM-control capability,
anda processor-interrupt system. Interrupts canbe pro-
grammedtothe user’s requirements, minimizingthe com-
puting requiredto handlethe communications link.
The DUARTis fabricated using National Semiconductor’s
advanced M2CMOSTM.
Features Dual independent UARTs Capableof runningall existing 16450 and PC16550D
software After reset,all registersare identicaltothe 16450 reg-
isterset Readand write cycle timesof84nsInthe FIFO mode transmitter and receiverare each
buffered with 16-byte FIFOsto reducethe numberof
interrupts presentedtothe CPU Holdingand shift registersinthe 16450 Mode eliminate
the needfor precise synchronization betweenthe CPU
and serial data Addsor deletes standard asynchronous communication
bits (start, stop, and parity)toor fromthe serial data Independently controlled transmit, receive, line status,
and dataset interrupts Programmable baud generators divide any input clock
by1to(216b1)and generatethe16c clock MODEM control functions (CTS, RTS, DSR, DTR,RI,
and DCD) Fully programmable serial-interface characteristics:5-,6-,7-,or 8-bit characters Even, odd,or no-paritybit generationand detection1-, 1(/2-,or 2-stopbit generation Baud generation (DCto 1.5M baud) with16c clock False startbit detection Complete status reporting capabilities TRI-STATEÉ TTL driveforthe dataand control buses Line break generationand detection Internal diagnostic capabilities: Loopback controlsfor communications link fault
isolation Break, parity, overrun, framing error simulation Full prioritized interrupt system controls
*Canalsobereset to16450 Mode under software control.
²Note:Thispartis patented.
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation
M2CMOSTM isatrademarkofNational SemiconductorCorporation
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
