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PC16550DVEF
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs
TL/C/8652
PC16550D
Universal
Asynchronous
Receiver/Transmitter
with
FIFOs
June 1995
PC16550D Universal Asynchronous
Receiver/Transmitter with FIFOs²
General Description
The PC16550Dis animproved versionofthe original 16450
Universal Asynchronous Receiver/Transmitter (UART).
Functionally identicaltothe 16450on powerup (CHARAC-
TER mode)*the PC16550Dcanbeput intoan alternate
mode(FIFO mode)to relievethe CPUofexcessive software
overhead.this mode internal FIFOsare activated allowing16 bytes
(plus3bitsof error dataper byteinthe RCVR FIFO)tobe
storedin bothreceiveand transmit modes.Allthe logic ison
chipto minimize system overheadand maximize systemef-
ficiency. Twopin functions have been changedto allowsig-
nallingof DMA transfers.
The UART performs serial-to-parallel conversionon data
characters received froma peripheral deviceora MODEM,
and parallel-to-serial conversionon data charactersre-
ceived fromthe CPU. The CPU can readthe complete
statusofthe UARTatany time duringthe functional opera-
tion. Status information reported includesthe typeand con-
ditionofthe transfer operations being performedbythe
UART,aswellasany error conditions (parity, overrun, fram-
ing,or break interrupt).
The UART includesa programmable baud rate generator
thatis capableof dividingthe timing reference clock input divisorsof1to (216b1),and producinga16c clockfor
drivingthe internal transmitter logic. Provisionsare alsoin-
cluded tousethis16c clockto drivethe receiver logic.The
UARThas complete MODEM-control capability,anda proc-
essor-interrupt system. Interrupts canbe programmedto
the user’s requirements, minimizingthe computing required handlethe communicationslink.
The UARTis fabricated using National Semiconductor’sad-
vanced M2CMOS process.
*Canalso beresetto 16450Mode under software control.
²Note:This partis patented.
Features Capableof runningall existing 16450 software.Pinforpin compatible withthe existing 16450 except
for CSOUT (24) andNC (29). The former CSOUT and pinsare TXRDYand RXRDY, respectively. After reset,all registersare identicaltothe 16450 reg-
isterset.Inthe FIFO mode transmitter and receiverare each
buffered with16 byte FIFO’sto reducethe numberof
interrrupts presentedtothe CPU. Addsor deletes standard asynchronous communication
bits (start, stop, and parity)toor fromthe serial data. Holdingand shift registersinthe 16450 Mode eliminate
the needfor precise synchronization betweenthe CPU
and serial data. Independently controlled transmit, receive, line status,
and dataset interrupts. Programmable baud generator divides any input clock
by1to(216b1)and generatesthe16c clock. Independent receiver clock input. MODEM control functions (CTS, RTS, DSR, DTR,RI,
and DCD). Fully programmable serial-interface characteristics:5-,6-,7-,or 8-bit characters Even, odd,or no-paritybit generationand detection1-, 1(/2-,or 2-stopbit generation Baud generation (DCto 1.5M baud). False startbit detection. Complete status reporting capabilities. TRI-STATEÉ TTL driveforthe dataand control buses. Line break generationand detection. Internal diagnostic capabilities: Loopback controlsfor communications link fault
isolation Break, parity, overrun, framing error simulation. Full prioritized interrupt system controls.
Basic Configuration
TL/C/8652–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorp.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
