P89LPC952FA-P89LPC952FBD Fast Delivery |IC PHOENIX CO.,LIMITED

P89LPC952FBD ,8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADCP89LPC952/9548-bit microcontroller with accelerated two-clock 80C51 core8 kB/16 kB 3 V byte-erasabl ..
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PCD3312CP ,DTMF/modem/musical-tone generators
PCD3312CP ,DTMF/modem/musical-tone generators

P89LPC952FA-P89LPC952FBD
8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
General descriptionThe P89LPC952/954 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC952/954 in order to reduce component count,
board space, and system cost. Features
2.1 Principal features8 kB/16kB byte-erasable ﬂash code memory organized into1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM. 8-input multiplexed 10-bit ADC with window comparator that can generatean interrupt
for in or out of range results. Two analog comparators with selectable inputs and
reference source. Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer
overﬂoworto becomea PWM output) anda 23-bit system timer that can alsobe used
as a RTC. Two enhanced UARTs with a fractional baud rate generator, break detect, framing
error detection, and automatic address detection; 400 kHz byte-wide I2 C-bus
communication port and SPI communication port. High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator optionis selectable and ﬁne
tunable. Fast switching between the internal RC oscillator and any oscillator source
provides optimal support of minimal power active mode with fast switching to
maximum performance. 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V). 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip
oscillator and reset options. Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins
have high sinking capability (20 mA). A maximum limit is speciﬁed for the entire chip. Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
P89LPC952/954
8-bit microcontroller with accelerated two-clock 80C51 core kB/16 kB 3 V byte-erasable ﬂash with 10-bit ADC
Rev. 04 — 24 July 2008 Product data sheet
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequencyfor the same performance resultsin power savings and reduced
EMI. Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs. Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted
in the end application. In-Application Programming (IAP)of the ﬂash code memory. This allows changing the
code in a running application. Low voltage (brownout) detect allows a graceful system shutdown when power fails.
May optionally be conﬁgured as an interrupt. Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled). On-chip power-on reset allows operation without external reset components. A
software reset function is also available. Programmable external reset pin (P1.5) conﬁguration options: open drain bidirectional
reset input/output, reset input with pull-up, push-pull reset output, input-only port. A
reset counter and reset glitch suppression circuitry prevent spurious and incomplete
resets. Only power and ground connections are required to operate the P89LPC952/954
when internal reset option is selected. Conﬁgurable on-chip oscillator with frequency range options selected by user
programmed ﬂash conﬁguration bits. Oscillator options support frequencies from kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Programmable port output conﬁguration options: quasi-bidirectional, open drain,
push-pull, input-only. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns
minimum ramp times. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Extended temperature range. Emulation support.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC Ordering information
3.1 Ordering options
Table 1. Ordering information
P89LPC952FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
P89LPC952FBD LQFP44 plastic low proﬁle quad ﬂat package; 44 leads;
body 10×10× 1.4 mm
SOT389-1
P89LPC954FA PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
P89LPC954FBD44 LQFP44 plastic low proﬁle quad ﬂat package; 44 leads;
body 10×10× 1.4 mm
SOT389-1
P89LPC954FBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;
body 7×7× 1.4 mm
SOT313-2
Table 2. Ordering options
P89LPC952FA 8kB −40 °Cto+85°C 0 MHzto18 MHz
P89LPC952FBD 8kB −40 °Cto+85°C 0 MHzto18 MHz
P89LPC954FA 16kB −40 °Cto+85°C 0 MHzto18 MHz
P89LPC954FBD44 16kB −40 °Cto+85°C 0 MHzto18 MHz
P89LPC954FBD48 16kB −40 °Cto+85°C 0 MHzto18 MHz
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC Block diagram
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC Functional diagram
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC Pinning information
6.1 Pinning
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
6.2 Pin description
Table 3. Pin description
P0.0 to P0.7 I/O Port0: Port 0 is an 8-bit I/O port with a user-conﬁgurable
output type. During reset Port0 latches are conﬁguredinthe
input only mode with the internal pull-up disabled. The
operationof Port0 pinsas inputs and outputs depends upon
the port conﬁguration selected. Each port pin is conﬁgured
independently. Refer to Section 7.13.1 “Port conﬁgurations”
and Table 11 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described
below:
P0.0/CMP2/
KBI0/AD05 43 37 I/O P0.0 — Port 0 bit0. CMP2 — Comparator 2 output. KBI0 — Keyboard input0. AD05 — ADC0 channel 5 analog input.
P0.1/CIN2B/
KBI1/AD00 42 36 I/O P0.1 — Port 0 bit1. CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input1. AD00 — ADC0 channel 0 analog input.
P0.2/CIN2A/
KBI2/AD01 41 35 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive input A. KBI2 — Keyboard input2. AD01 — ADC0 channel 1 analog input.
P0.3/CIN1B/
KBI3/AD02 40 34 I/O P0.3 — Port 0 bit3. CIN1B — Comparator 1 positive input B. KBI3 — Keyboard input3. AD02 — ADC0 channel 2 analog input.
P0.4/CIN1A/
KBI4/AD03 39 33 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive input A. KBI4 — Keyboard input4. AD03 — ADC0 channel 3 analog input.
P0.5/CMPREF/
KBI5 38 32 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
P0.6/CMP1/
KBI6 37 31 I/O P0.6 — Port 0 bit6. CMP1 — Comparator 1 output. KBI6 — Keyboard input6.
P0.7/T1/KBI7 31 35 29 I/O P0.7 — Port 0 bit7.
I/O T1 — Timer/counter 1 external count input or overﬂow
output. KBI7 — Keyboard input7.
P1.0 to P1.7 I/O,I
[1] Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable
output type, except for three pins as noted below. During
reset Port 1 latches are conﬁgured in the input only mode
with the internal pull-up disabled. The operation of the
conﬁgurable Port1 pinsas inputs and outputs depends upon
the port conﬁguration selected. Eachof the conﬁgurable port
pins are programmed independently. Referto Section 7.13.1
“Port conﬁgurations” and Table11 “Static characteristics”for
details. P1.2 to P1.3 are open drain when used as outputs.
P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described
below:
P1.0/TXD0 4 10 4 I/O P1.0 — Port 1 bit0. TXD0 — Transmitter output for serial port 0.
P1.1/RXD0 3 9 3 I/O P1.1 — Port 1 bit1. RXD0 — Receiver input for serial port 0.
P1.2/T0/SCL 2 8 2 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overﬂow
output (open-drain when used as output).
I/O SCL —I2 C-bus serial clock input/output.
P1.3/INT0/SDA1 7 1 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input.
I/O SDA —I2 C-bus serial data input/output.
P1.4/INT1 48 6 44 I/O P1.4 — Port 1 bit4. INT1 — External interrupt 1 input.
Table 3. Pin description …continued
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
P1.5/RST 47 5 43 I P1.5 — Port 1 bit 5 (input only). RST — External Reset input during power-on or maybe a
reset input/outputif selectedvia UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripheralsto takeon their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until VDD has reached its
speciﬁed level. When system poweris removed VDD will
fall below the minimum speciﬁed operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD
falls below the minimum speciﬁed operating voltage.
P1.6 46 4 42 I/O P1.6 — Port 1 bit6.
P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit7. AD04 — ADC0 channel 4 analog input.
P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-conﬁgurable
output type. During reset Port2 latches are conﬁguredinthe
input only mode with the internal pull-up disabled. The
operationof Port2 pinsas inputs and outputs depends upon
the port conﬁguration selected. Each port pin is conﬁgured
independently. Refer to Section 7.13.1 “Port conﬁgurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit0. AD07 — ADC0 channel 7 analog input.
P2.1/AD06 41 44 38 I/O P2.1 — Port 2 bit1. AD06 — ADC0 channel 6 analog input.
P2.2/MOSI 30 34 28 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slave in. When conﬁgured as
master, this pin is output; when conﬁgured as slave, this pin
is input.
P2.3/MISO 29 33 27 I/O P2.3 — Port 2 bit3.
I/O MISO — When conﬁgured as master, this pin is input, when
conﬁgured as slave, this pin is output.
P2.4/SS 28 32 26 I/O P2.4 — Port 2 bit4.
I/O SS — SPI Slave select.
Table 3. Pin description …continued
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
P2.5/SPICLK 27 31 25 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When conﬁguredas master, thispinis
output; when conﬁgured as slave, this pin is input.
P2.6 26 - - I/O P2.6 — Port 2 bit6.
P2.7 5 - - I/O P2.7 — Port 2 bit7.
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable
output type. During reset Port3 latches are conﬁguredinthe
input only mode with the internal pull-up disabled. The
operationof Port3 pinsas inputs and outputs depends upon
the port conﬁguration selected. Each port pin is conﬁgured
independently. Refer to Section 7.13.1 “Port conﬁgurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described
below:
P3.0/XTAL2/
CLKOUT 12 6 I/O P3.0 — Port 3 bit0. XTAL2 — Output fromthe oscillator ampliﬁer (whena crystal
oscillator option is selected via the ﬂash conﬁguration. CLKOUT — CPU clock divided by 2 when enabled via SFR
bit (ENCLK -TRIM.6). It can be used if the CPU clock is the
internal RC oscillator, watchdog oscillator or external clock
input, except when XTAL1/XTAL2 are usedto generate clock
source for the RTC/system timer.
P3.1/XTAL1 6 11 5 I/O P3.1 — Port 3 bit1. XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (when selectedvia the ﬂash conﬁguration).
It can be a port pin if internal RC oscillator or watchdog
oscillator is used as the CPU clock source, and if
XTAL1/XT AL2 are not used to generate the clock for the
RTC/system timer.
P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-conﬁgurable
output type. During reset Port4 latches are conﬁguredinthe
input only mode with the internal pull-up disabled. The
operationof Port4 pinsas inputs and outputs depends upon
the port conﬁguration selected. Each port pin is conﬁgured
independently. Refer to Section 7.13.1 “Port conﬁgurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 4 also provides various special functions as described
below:
P4.0 25 30 24 I/O P4.0 — Port 4 bit0.
P4.1/TRIG 24 29 23 I/O P4.1 — Port 4 bit1. TRIG — Debugger trigger output.
P4.2/TXD1 23 28 22 I/O P4.2 — Port 4 bit2. TXD1 — Transmitter output for serial port 1.
P4.3/RXD1 22 27 21 I/O P4.3 — Port 4 bit3. RXD1 — Receiver input for serial port 1.
Table 3. Pin description …continued
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P4.4 21 26 20 I/O P4.4 — Port 4 bit4.
P4.5/TDI 20 25 19 I/O P4.5 — Port 4 bit5.
I/O TDI — Serial data input/output for debugger interface.
P4.6 19 24 18 I/O P4.6 — Port 4 bit6.
P4.7/TCLK 18 23 17 I/O P4.7 — Port 4 bit7. TCLK — Serial clock input for debugger interface.
P5.0 to P5.7 I/O Port 5: Port 5 is an 8-bit I/O port with a user-conﬁgurable
output type. During reset Port5 latches are conﬁguredinthe
input only mode with the internal pull-up disabled. The
operationof Port5 pinsas inputs and outputs depends upon
the port conﬁguration selected. Each port pin is conﬁgured
independently. Refer to Section 7.13.1 “Port conﬁgurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 5 also provides various special functions as described
below:
P5.0 16 21 15 I/O P5.0 — Port 5 bit 0. High current source.
P5.1 15 20 14 I/O P5.1 — Port 5 bit 1. High current source.
P5.2 14 19 13 I/O P5.2 — Port 5 bit 2. High current source.
P5.3 13 18 12 I/O P5.3 — Port 5 bit 3. High current source.
P5.4 12 17 11 I/O P5.4 — Port 5 bit 4. High current source.
P5.5 11 16 10 I/O P5.5 — Port 5 bit 5. High current source.
P5.6 10 15 9 I/O P5.6 — Port 5 bit 6. High current source.
P5.7 9 14 8 I/O P5.7 — Port 5 bit 7. High current source.
VSS 17, 45 3, 22 16, 41 I Ground: 0 V reference.
VREFN 44 - - negative ADC reference voltage
VDD 8, 32 13, 36 7, 30 I Power supply: This is the power supply voltage for normal
operation as well as Idle and Power-down modes.
VREFP 33 - - positive ADC reference voltage
Table 3. Pin description …continued
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC Functional description
Remark: Please referto the P89LPC952/954 User’s Manualfora more detailed functional
description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways: User must not attempt to access any SFR locations not deﬁned. Accessesto any deﬁned SFR locations mustbe strictlyfor the functionsfor the SFRs. SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives. ‘0’ must be written with ‘0’, and will return a ‘0’ when read. ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 4.
Special function register
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 4.
Special function register
…contin
ued
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 4.
Special function register
…contin
ued
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 4.
Special function register
…contin
ued
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 4.
Special function register
…contin
ued
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
Indicates SFRs that are bit addressab
All por
ts are in input only (high-impedance) state after po
er-up
BRGR1_0 and BRGR0_0 m
ust only be wr
itten if BRGEN_0 in BRGCON_0 SFR is logic
0. If an
y are wr
itten while BRGEN_0
1, the resul
t is unpredictab
The
RSTSRC
register
reﬂects
the
cause
the
P89LPC952/954
reset.
Upon
er-up
reset,
all
reset
source
ﬂags
are
cleared
xcept
POF
and
BOF;
the
er-on
reset
alue
xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 4.
Special function register
…contin
ued
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
le 5.
Extended special function register
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NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
Extended
SFRs
are
ysically
located
on-chip
logically
located
xter
nal
data
memor
address
space
(XD
A).
The
A,@DPTR
and
@DPTR
instr
uctions
are
used to access these e
xtended SFRs
BRGR1_1 and BRGR0_1 m
ust only be wr
itten if BRGEN_1 in BRGCON_1 SFR is logic
0. If an
y are wr
itten while BRGEN_1
1, the resul
t is unpredictab
le 5.
Extended special function register
…contin
ued
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.2 Enhanced CPU
The P89LPC952/954 usesan enhanced 80C51 CPU which runsat six times the speedof
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock deﬁnitions
The P89LPC952/954 device has several internal clocks as deﬁned below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 6) and can also be optionally divided to a slower frequency (see
Section 7.8 “CCLK modiﬁcation: DIVM register”).
Note: fosc is deﬁned as the OSCCLK frequency.
CCLK — CPU clock; outputof the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executedin oneto two machine cycles (twoor four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
7.3.2 CPU clock (OSCCLK)
The P89LPC952/954 provides several user-selectable oscillator optionsin generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are conﬁgured when the ﬂashis programmed and includean
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this conﬁguration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this conﬁguration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this conﬁguration. When using a clock frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
speciﬁed level. When system power is removed VDD will fall below the minimum
speciﬁed operating voltage. When using a clock frequency above 12 MHz, in some
applications,an external brownout detect circuit may be requiredto hold the device
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
in reset when VDD falls below the minimum speciﬁed operating voltage. These
requirements for clock frequencies above 12 MHz do not apply when using the
internal RC oscillator in clock doubler mode.
7.3.6 Clock output
The P89LPC952/954 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock inputon XTAL1) andif the RTCis not using the crystal oscillatorasits clock
source. This allows external devicesto synchronizeto the P89LPC952/954. This outputis
enabled by the ENCLK bit in the TRIM register.
The frequencyof this clock outputis1⁄2 thatof the CCLK.If the clock outputis not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC952/954 has a 6-bit TRIM register that can be used to tune the frequency of
the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed
value to adjust the oscillator frequency to 7.373 MHz±1 % at room temperature.
End-user applications can writeto the TRIM registerto adjust the on-chip RC oscillatorto
other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1), the output
frequencyis 14.746 MHz.If CCLKis8 MHzor slower, the CLKLP SFRbit (AUXR1.7) can
be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing
highest performance access. This bit can then be set in software if CCLK is running at MHz or slower.
The requirements in Section 7.3.5 “High speed oscillator option” for conﬁguring P1.5 as
an external reset input and using an external reset circuit when the clock frequency is
greater than 12 MHz do not apply when using the internal RC oscillator’s clock doubler
option.
7.5 Watchdog oscillator option
The watchdog hasa separate oscillator which hasa frequencyof 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this conﬁguration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XT AL2 pin may be
used as a standard port pin or a clock output.
When using an external clock input frequency above 12 MHz, the reset input
function of P1.5 must be enabled. An external circuit is required to hold the device resetat power-up until VDD has reachedits speciﬁed level. When system poweris
removed VDD will fall below the minimum speciﬁed operating voltage. When using
an external clock input frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when VDD falls
below the minimum speciﬁed operating voltage. These requirements for clock
frequencies above 12 MHz do not apply when using the internal RC oscillator in
clock doubler mode.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.7 CCLK wake-up delay
The P89LPC952/954 hasan internal wake-up timer that delays the clock untilit stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus μsto100 μs.If the clock sourceis either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60 μsto100 μs.
7.8 CCLK modiﬁcation: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the abilityto respondto events that would not exit Idle modeby executingits normal
programata lower rate. This can also allow bypassing the oscillator start-up timein cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.
This bit can then be set in software if CCLK is running at 8 MHz or slower.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.10 Memory organization
The various P89LPC952/954 memory spaces are as follows: DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing. XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip
XDATA memory, plus extended SFRs located in XDATA. CODE kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown inT able6.
7.12 Interrupts
The P89LPC952/954 uses a four priority level interrupt structure. This allows great
ﬂexibility in controlling the handling of the many interrupt sources. The P89LPC952/954
supports17 interrupt sources: external interrupts0 and1, timers0 and1, serial port0 TX,
serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX,
combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I2 C-bus, keyboard,
comparators 1 and 2, SPI, and ADC completion.
Each interrupt source canbe individually enabledor disabledby settingor clearingabitin
the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Table 6. On-chip data memory usages
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
XDATA Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
256
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and
IP2H. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority
interrupt service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an
interrupt request.an external interruptis enabled when the P89LPC952/954is put into Power-downor Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes” for details.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.13 I/O ports
The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5.
Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O
pins available depends upon the clock and reset options and package chosen, as shown Table7.
[1] Required for operation above 12 MHz.
7.13.1 Port conﬁgurations
All but three I/O port pinson the P89LPC952/954 maybe conﬁguredby softwareto oneof
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. T wo conﬁguration registers for each port
select the output type for each port pin. P1.5/RST can only be an input and cannot be conﬁgured. P1.2/T0/SCL and P1.3/INT0/SDA may only be conﬁgured to be either input-only or
open-drain.
7.13.1.1 Quasi-bidirectional output conﬁguration
Quasi-bidirectional output type canbe usedas bothan input and output without the need
to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similartoan open-drain output except that there are three pull-up transistorsin
the quasi-bidirectional output that serve different purposes.
The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to VDD,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
7.13.1.2 Open-drain output conﬁguration
The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output,a port conﬁguredin this manner must havean external pull-up, typicallya resistor
tied to VDD.
Table 7. Number of I/O pins available
On-chip oscillator or watchdog
oscillator
No external reset (except during power-up) 42 40
External RST pin supported 41 39
External clock input No external reset (except during power-up) 41 39
External RST pin supported[1] 40 38
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during power-up) 40 38
External RST pin supported[1] 39 37
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
7.13.1.3 Input-only conﬁguration
The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that
also has a glitch suppression circuit.
7.13.1.4 Push-pull output conﬁguration
The push-pull output conﬁguration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a
Schmitt triggered input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC952/954 incorporates two Analog Comparators. In order to give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to ‘0’s to enable digital functions.
7.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from
the LPC76x series of devices. After power-up, all I/O pins except P1.5, may be conﬁgured by software. Pin P1.5 is input only. Pins P1.2 and P1.3 are conﬁgurable for either input-only or
open-drain.
Every outputon the P89LPC952/954 has been designedto sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 11 for detailed speciﬁcations.
All ports pins that can functionasan output have slew rate controlled outputsto limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC952/954 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during operation.
This is accomplished with two hardware functions: Power-on detect and brownout detect.
7.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. The default operationisfora brownout detectionto causea processor reset,
however it may alternatively be conﬁgured to generate an interrupt.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
Brownout detection may be enabled or disabled in software.
If brownout detection is enabled the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (seeT able11 “Static characteristics”), andis negated when VDD
rises above Vbo. If the P89LPC952/954 device is to operate with a power supply that can
be below 2.7V , BOE should be left in the unprogrammed state so that the device can
operate at 2.4V , otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of brownout detect, the VDD rise and fall times must be observed.
Please see Table 11 “Static characteristics” for speciﬁcations.
7.14.2 Power-on detection
The Power-on detect hasa function similarto the brownout detect, butis designedto work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an
initial power-up condition. The POF ﬂag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC952/954 supports three different power reduction modes. These modes are
Idle mode, Power-down mode, and total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC952/954 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage maybe reducedto the data retention supply
voltage VDDR. This retains the RAM contents at the point where Power-down mode was
entered. SFR contents are not guaranteed after VDD has been loweredto VDDR, therefore
it is highly recommended to wake-up the processor via reset in this case. VDD must be
raised to within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, comparators (note that comparators can be powered down separately),
and RTC/system timer. The internal RC oscillatoris disabled unless both the RC oscillator
has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillatoris disabled unless both the RC oscillator has been selectedas the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there willbe high power consumption. Please usean external low frequency
clock to achieve low power with the RTC running during power-down.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.16 Reset
The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input
with an internal pull-up, a bidirectional reset input/output (open drain output with an
internal pull-up), or as push-pull reset output. These modes are selected by the RPE
(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.
Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and
this pin always functions as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this pin will function as deﬁned by the RPE and RPE1
bits. Only a power-up reset will temporarily override the selection deﬁned by RPE and
RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.
Remark: During a power cycle, VDD must fall below VPOR before power is reapplied, in
order to ensure a power-on reset (see Table 11 “Static characteristics” on page 51).
Remark: When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its speciﬁed level. When system power is removed VDD
will fall below the minimum speciﬁed operating voltage. When using an oscillator
frequency above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum speciﬁed
operating voltage.
Reset can be triggered from the following sources: External reset pin (during power-up or if user conﬁgured via UCFG1, UCGF2); Power-on detect; Brownout detect; Watchdog timer; Software reset; UART break character detect reset.
For every reset source, thereisa ﬂagin the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ﬂag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set: During a power-on reset, both POF and BOF are set but the other ﬂag bits are
cleared. For any other reset, previously set ﬂag bits that have not been cleared will remain set.
Table 8. Reset pin modes
General purpose input 0 0
Reset input with pull-up 0 1
Bidirectional reset input/output (open drain with pull-up) 1 0
Reset output 1 1
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.16.1 Reset vector
Following reset, the P89LPC952/954 will fetch instructions from either address 0000H or
the Boot address. The Boot addressis formedby using the boot vectoras the high byteof
the address and the low byte of the address= 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0)= 1, or the device is forced into ISP mode during power-on (see
P89LPC952/954 User’s Manual). Otherwise, instructions will be fetched from address
0000H.
7.17 Timers/counters 0 and 1
The P89LPC952/954 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to
operate eitheras timersor event counters. An optionto automatically toggle theT0 and/or
T1 pins upon timer overﬂow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle. the ‘Counter’ function, the registeris incrementedin responsetoa 1-to-0 transitionatits
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have ﬁve operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer1.
7.17.2 Mode1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode2
Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode2
operation is the same for Timer 0 and Timer1.
7.17.4 Mode3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters andis providedfor applications that requirean extra 8-bit timer. When Timer1is
in Mode 3 it can still be used by the serial port as a baud rate generator.
7.17.5 Mode6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.17.6 Timer overﬂow toggle output
Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer
overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst
timer overﬂow when this mode is turned on.
7.18 RTC/system timer
The P89LPC952/954 hasa simple RTC that allowsa userto continue runningan accurate
timer while the rest of the device is powered down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again
and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU
clock (CCLK)or the XTAL oscillator, provided that the XTAL oscillatoris not being usedas
the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use
CCLKasits clock source. Only power-on reset will reset the RTC andits associated SFRs
to the default state.
7.19 UARTs
The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional
80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The
P89LPC952/954 does include an independent Baud Rate Generator for each UART
(BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the
oscillator (divided by a constant), Timer 1 overﬂow, or the independent Baud Rate
Generator associated with the speciﬁc UART. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt options.
The UARTs can be operated in 4 modes: shift register, 8-bit UART , 9-bit UART, and CPU
clock/32 or CPU clock/16.
7.19.1 Mode0
Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are
transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at1 ⁄16 of the CPU clock
frequency.
7.19.2 Mode1 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), data bits (LSB ﬁrst), anda stopbit (logic 1). When datais received, the stopbitis stored
in RB8_n in Special Function Register SnCON. The baud rate is variable and is
determinedby the Timer1 overﬂow rateor the Baud Rate Generator (describedin Section
7.19.5 “Baud rate generator and selection”).
7.19.3 Mode2 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0), data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8_n in SnCON) can be assigned the value of ‘0’ or ‘1’. Or,
for example, the parity bit (P , in the PSW) could be moved into TB8_n. When data is
received, the9th databit goes into RB8_nin Special Function Register SnCON, while the
NXP Semiconductors P89LPC952/954
8-bit microcontroller with 10-bit ADC
stopbitis not saved. The baud rateis programmableto either1⁄16or1⁄32of the CPU clock
frequency,as determinedby the SMOD1bitin PCON. The SMOD1bit controls the Timer
1 output rate available to both UARTs.
7.19.4 Mode3 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8
data bits (LSB ﬁrst),a programmable9th data bit, anda stopbit (logic1).In fact, Mode3is
the sameas Mode2inall respects except baud rate. The baud ratein Mode3is variable
and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in
Section 7.19.5 “Baud rate generator and selection”).
7.19.5 Baud rate generator and selection
Each enhanced UART has an independent Baud Rate Generator. The baud rate is
determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UARTs can use either Timer 1 or their respective baud rate generator output (see
Figure8). Note that TimerT1is further dividedby2if the SMOD1bit (PCON.7)is cleared.
The independent Baud Rate Generators use OSCCLK.
7.19.6 Framing error
Framing erroris reportedin the status register (SnSTAT).In addition,if SMOD0 (PCON.6)
is ‘1’, framing errors can be made available in SnCON.7 respectively. If SMOD0 is ‘0’,
SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up
when SMOD0 is ‘0’.
7.19.7 Break detect
Break detect is reported in the status register (SnSTA T). A break is detected when consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
7.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.

Partno	Mfg	Dc	Qty	Available	Descript
P89LPC952FA	NXP	N/a	15	avai	8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
P89LPC952FA	PHILIS	N/a	210	avai	8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
P89LPC952FBD	NXP	N/a	2500	avai	8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC