P89LPC935FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersP89LPC933/934/9358-bit microcontroller with accelerated two-clock 80C51 core4 kB/8 kB 3 V byte-eras ..
P89LPC935FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersfeatures■ 4 kB/8 kB byte-erasable Flash code memory organized into 1 kB sectors and64-byte pages. S ..
P89LPC935FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersGeneral descriptionThe P89LPC933/934/935 is a single-chip microcontroller, available in low costpac ..
P89LPC936FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures■ 4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB/2 kB sectorsand 64-byt ..
P89LPC936FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 nsfor all ..
P89LPC936FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all ..
PCD-148D1MH , 15 Amp Low Profile Power PC Board Relay
PCD3310T ,Pulse and DTMF diallers with redial
PCD3310T ,Pulse and DTMF diallers with redial
PCD3311 ,DTMF/modem/musical-tone generators
PCD3312 ,DTMF/modem/musical-tone generators
PCD3312CP ,DTMF/modem/musical-tone generators
P89LPC935FA-P89LPC935FDH
8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
P89LPC933/934/9358-bit microcontroller with accelerated two-clock 80C51 core kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
Rev. 04 — 09 February 2004 Objective data General descriptionThe P89LPC933/934/935 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes
instructionsin twoto four clocks, six times the rateof standard 80C51 devices. Many
system-level functions have been incorporated into the P89LPC933/934/935in order
to reduce component count, board space, and system cost.
Features
2.1 Principal features4 kB/8 kB byte-erasable Flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage. 256-byte RAM data memory. (P89LPC935 also includes a 512-byte auxiliary
on-chip RAM). 512-byte customer Data EEPROMon chip allows serializationof devices, storage
of set-up parameters, etc. (P89LPC935) Dual 4-input multiplexed 8-bit A/D converters (P89LPC935, single A/D on
P89LPC934/933). Two analog comparators with selectable inputs and reference
source. Two 16-bit counter/timers (each may be configured to toggle a port output upon
timer overflow or to become a PWM output) and a 23-bit system timer that can
also be used as a Real-Time clock. Enhanced UART with fractional baudrate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2 C-bus
communication port and SPI communication port. Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions (P89LPC935). High-accuracy internal RC oscillator option allows operation without external
oscillator components.The RC oscillator option is selectable and fine tunable. 2.4Vto 3.6V VDD operating range. I/O pins are5V tolerant (maybe pulledupor
driven to 5.5 V). 28-pin TSSOP, PLCC, and HVQFN packages with23 I/O pins minimum andupto
26 I/O pins while using on-chip oscillator and reset options.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional featuresA high performance 80C51 CPU provides instruction cycle timesof 167-333nsfor
all instructions except multiply and divide when executing at 12 MHz. This is 6
times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI. Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent readingof sensitive
application programs. Serial Flash In-System Programming (ISP) allows coding while the device is
mounted in the end application. In-Application Programming of the Flash code memory. This allows changing the
code in a running application. Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values. Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt. Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical Power-down
current is 1 μA (total Power-down with analog functions disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user
programmed Flash configuration bits. Oscillator options support frequencies from kHz to the maximum operating frequency of 12 MHz. Oscillator Fail Detect. The Watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only. Port ‘input pattern match’ detect. Port0 may generatean interrupt when the value
of the pins match or do not match a programmable pattern. LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip. Controlled slew rate port outputs to reduce EMI. Outputs have approximately ns minimum ramp times. Only power and ground connections are required to operate the
P89LPC933/934/935 when internal reset and RC oscillator options are selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Ordering information
3.1 Ordering options
Table 1: Ordering informationP89LPC933FDH TSSOP28 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT361-1
P89LPC934FDH TSSOP28 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT361-1
P89LPC935FA PLCC28 plastic leaded chip carrier; 28 leads SOT261-2
P89LPC935FDH TSSOP28 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT361-1
P89LPC935FHN HVQFN28 plastic thermal enhanced very thin quad flat
package; no leads; 28 terminals;
body6×6× 0.85 mm
SOT788-1
Table 2: Part optionsP89LPC933FDH 4kB −40 °Cto+85°C 0to12 MHz
P89LPC934FDH 8kB −40 °Cto+85°C 0to12 MHz
P89LPC935FA 8kB −40 °Cto+85°C 0to12 MHz
P89LPC935FDH 8kB −40 °Cto+85°C 0to12 MHz
P89LPC935FHN 8kB −40 °Cto+85°C 0to12 MHz
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Block diagram
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Pinning information
5.1 Pinning
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
5.2 Pin description
Table 3: Pin descriptionP0.0 - P0.7 3, 26, 25,
24, 23, 22,
20, 19
27, 22, 21,
20, 19, 18,
16, 15
I/O
Port0: Port 0 is an 8-bit I/O port with a user-configurable output type.
During reset Port0 latches are configuredin the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 10 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: 27 I/O
P0.0 — Port 0 bit0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input0.
AD01 — ADC0 channel 1 analog input. (P89LPC935) 22 I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input1.
AD10 — ADC1 channel 0 analog input. 21 I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input2.
AD11 — ADC1 channel 1 analog input. 20 I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input3.
AD12 — ADC1 channel 2 analog input. 19 I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input4.
AD13 — ADC1 channel 3 analog input.
DAC1 — Digital-to-analog converter output1. 18 I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input5.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 coreP0.0 - P0.7
(continued) 16 I/O
P0.6 — Port 0 bit6.
CMP1 — Comparator 1 output.
KBI6 — Keyboard input6. 15 I/O
P0.7 — Port 0 bit7.
I/O
T1 — Timer/counter 1 external count input or overflow output.
KBI7 — Keyboard input7.
P1.0 - P1.7 18, 17, 12,
11, 10, 6,
5, 4
14, 13, 8,
7, 6, 2, 1,
I/O,I[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type,
except for three pins as noted below. During reset Port 1 latches are
configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends
upon the port configuration selected. Each of the configurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
configurations” and Table 10 “DC electrical characteristics” for details.
P1.2 - P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: 14 I/O
P1.0 — Port 1 bit0.
TXD — Transmitter output for the serial port. 13 I/O
P1.1 — Port 1 bit1.
RXD — Receiver input for the serial port. 8 I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overflow output (open-drain
when used as output).
I/O
SCL —I2 C serial clock input/output. 7 I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
INT0 — External interrupt 0 input.
I/O
SDA —I2 C serial data input/output. 6 I
P1.4 — Port 1 bit4.
INT1 — External interrupt 1 input.
62I
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins executionat address0. Also used during
a power-on sequence to force In-System Programming mode. 1 I/O
P1.6 — Port 1 bit6.
OCB — Output Compare B. (P89LPC935) 28 I/O
P1.7 — Port 1 bit7.
OCC — Output Compare C. (P89LPC935)
AD00 — ADC0 channel 0 analog input. (P89LPC935)
Table 3: Pin description…continued
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 coreP2.0 - P2.7 1, 2, 13,
14, 15, 16,
27, 28
25, 26, 9,
10, 11, 12,
23, 24
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port2 latches are configuredin the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 10 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below: 25 I/O
P2.0 — Port 2 bit0.
ICB — Input Capture B. (P89LPC935)
AD03 — ADC0 channel 3 analog input. (P89LPC935)
DAC0 — Digital-to-analog converter output0. 26 I/O
P2.1 — Port 2 bit1.
OCD — Output Compare D. (P89LPC935)
AD02 — ADC0 channel 2 analog input. (P89LPC935) 9 I/O
P2.2 — Port 2 bit2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input. 10 I/O
P2.3 — Port 2 bit3.
I/O
MISO — When configuredas master, thispinis input, when configuredas
slave, this pin is output. 11 I/O
P2.4 — Port 2 bit4.
SS — SPI Slave select. 12 I/O
P2.5 — Port 2 bit5.
I/O
SPICLK — SPI clock. When configuredas master, thispinis output; when
configured as slave, this pin is input. 23 I/O
P2.6 — Port 2 bit6.
OCA — Output Compare A. (P89LPC935) 24 I/O
P2.7 — Port 2 bit7.
ICA — Input Capture A. (P89LPC935)
Table 3: Pin description…continued
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.
P3.0 - P3.1 9, 8 5, 4 I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.
During reset Port3 latches are configuredin the input only mode with the
internal pull-up disabled. The operation of Port 3 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 10 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below: 5 I/O
P3.0 — Port 3 bit0.
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator
option is selected via the FLASH configuration.
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -
TRIM.6). It can be used if the CPU clock is the internal RC oscillator,
watchdog oscillatoror external clock input, except when XTAL1/XTAL2 are
used to generate clock source for the Real-Time clock/system timer. 4 I/O
P3.1 — Port 3 bit1.
XTAL1 — Inputto the oscillator circuit and internal clock generator circuits
(when selected via the FLASH configuration). It can be a port pin if
internal RC oscillator or watchdog oscillator is used as the CPU clock
source,
and if XT AL1/XTAL2 are not used to generate the clock for the
Real-Time clock/system timer.
VSS 73I
Ground: 0 V reference.
VDD 21 17 I
Power Supply: This is the power supply voltage for normal operation aswell as Idle and Power-Down modes.
Table 3: Pin description…continued
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Logic symbol
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
User must
not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can
only be written and read as follows:‘-’ Unless otherwise specified,
mustbe written with ‘0’, but can return any value
when read (evenifit was written with ‘0’).Itisa reservedbit and maybe usedin
future derivatives.
‘0’
must be written with ‘0’, and will return a ‘0’ when read.‘1’
must be written with ‘1’, and will return a ‘1’ when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 4:
P89LPC933/934 Special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 4:
P89LPC933/934 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 4:
P89LPC933/934 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
All por
ts are in input only (high impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is ‘0’. If an
y are wr
itten while BRGEN
1, the result is unpredic
tab
The RSTSRC register reflects the cause of the P89LPC933/934/935 reset. Upon a po
er-up reset, all reset source flags are clear
ed e
xcept POF and BOF; the po
er-on reset
alue is xx110000.
After
reset,
the
alue
111001x1,
i.e
PRE2-PRE0
are
all
‘1’,
WDR
and
WDCLK
WDT
bit
‘1’
after
atchdog
reset
and
‘0’
after
er-on
reset.
Other
resets
will
not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 4:
P89LPC933/934 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 5:
P89LPC935 Special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 5:
P89LPC935 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 5:
P89LPC935 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 5:
P89LPC935 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
le 5:
P89LPC935 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
All por
ts are in input only (high impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is ‘0’. If an
y are wr
itten while BRGEN
1, the result is unpredic
tab
The RSTSRC register reflects the cause of the P89LPC933/934/935 reset. Upon a po
er-up reset, all reset source flags are clear
ed e
xcept POF and BOF; the po
er-on reset
alue is xx110000.
After
reset,
the
alue
111001x1,
i.e
PRE2-PRE0
are
all
‘1’,
WDR
and
WDCLK
WDT
bit
‘1’
after
atchdog
reset
and
‘0’
after
er-on
reset.
Other
resets
will
not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 5:
P89LPC935 Special function register
…contin
ued
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core Functional description
Remark: Please refer to the P89LPC933/934/935 User’s Manual for a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC933/934/935 uses an enhanced 80C51 CPU which runs at 6 times the
speedof standard 80C51 devices.A machine cycle consistsof two CPU clock cycles,
and most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1 Clock definitions
The P89LPC933/934/935 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure 12) and can also be optionally divided to a slower
frequency (see Section 8.7 “CPU Clock (CCLK) modification: DIVM register”).
Note: fOSC is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executedin oneto two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
8.2.2 CPU clock (OSCCLK)
The P89LPC933/934/935 provides several user-selectable oscillator options. This
allows optimization for a range of needs from high precision to lowest possible cost.
These options are configured when the FLASH is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
8.2.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.2.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
8.2.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic
resonators are also supported in this configuration.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.2.6 Clock output
The P89LPC933/934/935 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillatoris not being used. This condition occursif
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC933/934/935. This output is enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is1 ⁄2 that of the CCLK. If the clock output is not
needed in Idle mode, it may be turned off prior to entering Idle, saving additional
power.
8.3 On-chip RC oscillator option
The P89LPC933/934/935 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed valueto adjust the oscillator frequencyto 7.373 MHz,±1%at room
temperature. End-user applications can write to the TRIM register to adjust the
on-chip RC oscillator to other frequencies.
8.4 Watchdog oscillator option
The watchdog has a separate oscillator which has a nominal frequency of 400 kHz.
This oscillator canbe usedto save power whena high clock frequencyis not needed.
8.5 External clock input option
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.6 CPU Clock (CCLK) wake-up delay
The P89LPC933/934/935 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK
cycles plus 60to 100 μs. If the clock source is either the internal RC oscillator,
watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plusto 100 μs.
8.7 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPUata lower rate, reducing power consumption.By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
modeby executingits normal programata lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC933/934/935 is designed to run at 12 MHz (CCLK) maximum. However,
if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower
the power consumption further. On any reset, CLKLP is ‘0’ allowing highest
performance access. Thisbit can thenbe setin softwareif CCLKis runningat8 MHz
or slower.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.9 A/D converter
8.9.1 General description
The P89LPC935 has two 8-bit, 4-channel multiplexed successive approximation
analog-to-digital converter modules sharing common control logic. The
P89LPC933/934 have a single 8-bit, 4-channel multiplexed analog-to-digital
converter and an additional DAC module. A block diagram of the A/D converter is
shown in Figure 13. Each A/D consists of a 4-input multiplexer which feeds a
sample-and-hold circuit providing an input signal to one of two comparator inputs.
The control logic in combination with the successive approximation register (SAR)
drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.9.2 Features Two (P89LPC935) 8-bit, 4-channel multiplexed input, successive approximation
A/D converters with common control logic (one A/D on the P89LPC933/934). Four result registers for each A/D. Six operating modes Fixed channel, single conversion mode Fixed channel, continuous conversion mode Auto scan, single conversion mode Auto scan, continuous conversion mode Dual channel, continuous conversion mode Single step mode Four conversion start modes Timer triggered start Start immediately Edge triggered Dual start immediately (P89LPC935) 8-bit conversion time of ≥3.9μs Interrupt or polled operation Boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power down mode
8.9.3 A/D operating modes
Fixed channel, single conversion mode:A single input channel canbe selectedfor
conversion. A single conversion will be performed and the result placed in the result
register which correspondsto the selected input channel. An interrupt,if enabled, will
be generated after the conversion completes.
Fixed channel, continuous conversion mode: A single input channel can be
selectedfor continuous conversion. The resultsof the conversions willbe sequentially
placed in the four result registers. An interrupt, if enabled, will be generated after
every four conversions. Additional conversion results will again cycle through the four
result registers, overwriting the previous results. Continuous conversions continue
until terminated by the user.
Auto scan, single conversion mode: Any combination of the four input channels
can be selected for conversion. A single conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. If only a single channel is selected this is equivalent
to single channel, single conversion mode.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
Auto scan, continuous conversion mode: Any combination of the four input
channels can be selected for conversion. A conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. The process will repeat starting with the first selected
channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results.Continous conversions continue until
terminated by the user.
Dual channel, continuous conversion mode: This is a variation of the auto scan
continuous conversion mode where conversion occurson two user-selectable inputs.
The resultof the conversionof the first channelis placedin result register, ADxDAT0.
The result of the conversion of the second channel is placed in result register,
ADxDAT1. The first channelis again converted andits result storedin ADxDAT2. The
second channel is again converted and its result placed in ADxDAT3. An interrupt is
generated, if enabled, after every set of four conversions (two conversions per
channel).
Single step mode: This special mode allows ‘single-stepping’ in an auto scan
conversion mode. Any combination of the four input channels can be selected for
conversion. After each channel is converted, an interrupt is generated, if enabled,
and the A/D waits for the next start condition. May be used with any of the start
modes.
8.9.4 Conversion start modes
Timer triggered start: An A/D conversionis startedby the overflowof Timer0. Once
a conversion has started, additional Timer 0 triggers are ignored until the conversion
has completed. The Timer triggered start mode is available in all A/D operating
modes.
Start immediately: Programming this mode immediately starts a conversion.This
start mode is available in all A/D operating modes.
Edge triggered: An A/D conversion is started by rising or falling edge of P1.4. Once
a conversion has started, additional edge triggers are ignored until the conversion
has completed. The edge triggered start mode is available in all A/D operating
modes.
Dual start immediately (P89LPC935): Programming this mode starts a
synchronized conversionof both A/D converters.This start modeis availableinall A/D
operating modes. Both A/D converters must be in the same operating mode. In the
continuous conversion modes, both A/D converters must select an identical number
of channels. Any trigger of either A/D will start a simultaneous conversion of both
A/Ds.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.9.5 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. After the
four MSBs have been converted, these four bits are compared with the four MSBs of
the boundary high and low registers. If the four MSBs of the conversion are outside
the limitan interrupt willbe generated,if enabled.If the conversion resultis within the
limits, the boundary limits will againbe compared afterall8 bits have been converted.
An interrupt will be generated, if enabled, if the result is outside the boundary limits.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
8.9.6 DAC output to a port pin with high output impedance
Each DAC block can be output to a port pin. In this mode, the ADxDAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC
(written to ADxDAT3), the DAC output will appear on the channel 3 pin.
8.9.7 Clock divider
The A/D converter requires thatits internal clock sourcebein the rangeof 500 kHzto MHz to maintain accuracy. A programmable clock divider that divides the clock
from1to 8 is provided for this purpose.
8.9.8 Power-down and idle mode idle mode the A/D converter,if enabled, will continueto function and can cause the
device to exit idle mode when the conversion is completed if the A/D interrupt is
enabled.In Power-down modeorT otal power-down mode, the A/D does not function.
If the A/D is enabled, it will consume power. Power can be reduced by disabling the
A/D.
8.10 Memory organization
The various P89LPC933/934/935 memory spaces are as follows: DATA
128 bytesof internal data memory space (00h:7Fh) accessed via director indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack maybein this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing. XDATA (P89LPC935)
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory
space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part
of this space could be implemented on-chip. The P89LPC935 has 512 bytes of
on-chip XDATA memory.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core CODEkBof Code memory space, accessedas partof program execution and via the
MOVC instruction. The P89LPC934/935 has 8 kB of on-chip Code memory. The
P89LPC933 has 4 kB.
The P89LPC935 also has 512 bytes of on-chip Data EEPROM that is accessed via
SFRs (see Section 8.27 “Data EEPROM (P89LPC935)”).
8.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table6.
8.12 Interrupts
The P89LPC933/934/935 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources. The
P89LPC933/934/935 supports 15 interrupt sources: external interrupts 0 and 1,
timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout
detect, watchdog/Real-Time clock, I2 C, keyboard, comparators 1 and 2, SPI, CCU,
data EEPROM write/ADC completion.
Each interrupt source canbe individually enabledor disabledby settingor clearinga
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source canbe individually programmedto oneof four priority levelsby
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but notby another interruptof the sameor lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pendingat the startofan instruction, the requestof higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.12.1 External interrupt inputs
The P89LPC933/934/935 has two external interrupt inputs as well as the Keypad
Interrupt function. The two interrupt inputs are identical to those present on the
standard 80C51 microcontrollers.
These external interrupts canbe programmedtobe level-triggeredor edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
Table 6: On-chip data memory usages
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
XDATA Auxiliary (‘External Data’) on-chip memory thatis accessed
using the MOVX instructions (P89LPC935)
512
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC933/934/935 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and
resume operation. Refer to Section 8.15 “Power reduction modes” for details.
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
8.13 I/O ports
The P89LPC933/934/935 has four I/O ports: Port 0, Port 1, Port 2, and Port3.
Ports0, 1and2 are 8-bit ports, and Port3isa 2-bit port. The exact numberof I/O pins
available depends upon the clock and reset options chosen, as shown in Table7.
8.13.1 Port configurations
All but three I/O port pinson the P89LPC933/934/935 maybe configuredby software
to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard
80C51 port outputs), push-pull, open drain, and input-only. Two configuration
registers for each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may onlybe configuredtobe either input-onlyor
open-drain.
Quasi-bidirectional output configuration: Quasi-bidirectional output type can be
used as both an input and output without the need to reconfigure the port. This is
possible because when the port outputsa logic HIGH,itis weakly driven, allowingan
external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly
and able to sink a fairly large current. These features are somewhat similar to an
open-drain output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes.
The P89LPC933/934/935 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to VDD, causing extra power consumption. Therefore, applying V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
Open-drain output configuration: The open-drain output configuration turns off all
pull-ups and only drives the pull-down transistorof the port driver when the port latch
contains a logic ‘0’. To be used as a logic output, a port configured in this manner
must have an external pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
Input-only configuration: The input-only port configuration has no output drivers. It
is a Schmitt-triggered input that also has a glitch suppression circuit.
Table 7: Number of I/O pins available
On-chip oscillator or watchdog oscillator No external reset (except during power-up) 26
External RST pin supported 25
External clock input No external reset (except during power-up) 25
External RST pin supported 24
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during power-up) 24
External RST pin supported 23
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
Push-pull output configuration: The push-pull output configuration has the same
pull-down structureas both the open-drain and the quasi-bidirectional output modes,
but provides a continuous strong pull-up when the port latch contains a logic ‘1’. The
push-pull mode maybe used when more source currentis needed froma port output.
A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
8.13.2 Port 0 analog functions
The P89LPC933/934/935 incorporates two Analog Comparators. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD[1:5] defaults to ‘0’s to enable digital functions.
8.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices. After power-up, all I/O pins except P1.5, may be configured by software. Pin P1.5is input only. Pins P1.2 and P1.3 and are configurablefor either input-only
or open-drain.
Every output on the P89LPC933/934/935 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to Table 10 “DC electrical characteristics” for
detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC933/934/935 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power lossor reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.14.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software. Brownout detectionis enabled, the operating voltage rangefor VDDis 2.7Vto 3.6V,
and the brownout condition occurs when VDD falls below the brownout trip voltage,
VBO (see Table 10 “DC electrical characteristics”), and is negated when VDD rises
Philips Semiconductors P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
above VBO. If brownout detection is disabled, the operating voltage range for VDD is
2.4Vto 3.6 V. If the P89LPC933/934/935 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the
device can operate at 2.4 V, otherwise continuous brownout reset may prevent the
device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 10 “DC electrical characteristics” for specifications.
8.14.2 Power-on detection
The Power-on Detect hasa function similarto the Brownout detect, butis designedto
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.15 Power reduction modes
The P89LPC933/934/935 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.
8.15.1 Idle mode
Idle mode leaves peripherals runningin orderto allow themto activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC933/934/935 exits Power-down mode via any reset,or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage VRAM. This retains the RAM contents at the point where
Power-down mode was entered. SFR contents are not guaranteed after VDD has
been lowered to VRAM, therefore it is highly recommended to wake up the processor
via reset in this case. VDD must be raised to within the operating range before the
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
A/D converters, Watchdog Timer, Comparators (note that Comparators can be
powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal
RC oscillator is disabled unless both the RC oscillator has been selected as the
system clock and the RTC is enabled.
8.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTCis enabled.If the internal RC oscillatoris usedto clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
