P89LPC931FDH ,8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAMP89LPC930/9318-bit microcontrollers with two-clock 80C51 core4 kB/8 kB 3 V Flash with 256-byte data ..
P89LPC9321FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROMfeatures 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Singl ..
P89LPC932A1FA ,P89LPC932A1; 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 512-byte data EEPROM
P89LPC932A1FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROMGeneral descriptionThe P89LPC932A1 is a single-chip microcontroller, available in low cost packages ..
P89LPC933FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsGeneral descriptionThe P89LPC933/934/935/936 is a single-chip microcontroller, available in low cos ..
P89LPC934FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures 4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB/2 kB sectors and 64-b ..
PCD-124D1MH , 15 Amp Low Profile Power PC Board Relay
PCD-148D1MH , 15 Amp Low Profile Power PC Board Relay
PCD3310T ,Pulse and DTMF diallers with redial
PCD3310T ,Pulse and DTMF diallers with redial
PCD3311 ,DTMF/modem/musical-tone generators
PCD3312 ,DTMF/modem/musical-tone generators
P89LPC931FDH
8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
P89LPC930/9318-bit microcontrollers with two-clock 80C51 core kB/8 kB 3 V Flash with 256-byte data RAM
Rev. 05 — 15 December 2004 Product data General descriptionThe P89LPC930/931 are single-chip microcontrollers designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC930/931 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC930/931 in order to reduce component count, board space, and system
cost.
Features A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
Thisis6 times the performanceof the standard 80C51 runningat the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI. 2.4Vto 3.6V VDD operating range. I/O pins are5V tolerant (maybe pulledupor
driven to 5.5 V).4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size. Byte-erase allowing code memory to be used for data storage. Flash program operation completes in 2 ms. Flash erase operation completes in 2 ms. 256-byte RAM data memory. Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output. Real-Time clock that can also be used as a system timer. Two analog comparators with selectable inputs and reference source. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities. 400 kHz byte-wide I2 C-bus communication port. SPI communication port. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Four interrupt priority levels. Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values. Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt. Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Configurable on-chip oscillator with frequency range and RC oscillator options
(selectedby user programmed Flash configuration bits). The RC oscillator (factory
calibrated to±1 %) option allows operation without external oscillator
components. Oscillator options support frequencies from20 kHzto the maximum
operating frequency of 18 MHz. The RC oscillator option is selectable and fine
tunable. Programmable port output configuration options: Quasi-bidirectional Open drain Push-pull Input-only Port ‘input pattern match’ detect. Port0 may generatean interrupt when the value
of the pins match or do not match a programmable pattern. Second data pointer. Schmitt trigger port inputs. LED drive capability (20 mA) on all port pins. Maximum combined I/O current of
100 mA. Controlled slew rate port outputs to reduce EMI. Outputs have approximately ns minimum ramp times. 23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip
oscillator and reset options. Only power and ground connections are required to operate the P89LPC930/931
using on-chip oscillator and on-chip reset options. Serial Flash programming allows in-circuit production coding. Flash security bits
prevent reading of sensitive programs. In-Application Programmingof the Flash code memory. This allows changing the
code in a running application. Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1 μA (total Power-down with voltage comparators disabled). 28-pin TSSOP package. Emulation support.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Ordering information
3.1 Ordering options
Table 1: Ordering informationP89LPC930FDH TSSOP28 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT361-1
P89LPC931FDH TSSOP28 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT361-1
Table 2: Part optionsP89LPC930FDH 4kB −45 °Cto+85°C 0 MHzto18 MHz
P89LPC931FDH 8kB −45 °Cto+85°C 0 MHzto18 MHz
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Block diagram
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Pinning information
5.1 Pinning
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
5.2 Pin description
Table 3: Pin descriptionP0.0 - P0.7 3, 26, 25,
24,23, 22,
20, 19
I/O
Port0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port0 latches are configuredinthe input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
8.11.1 “Port configurations” and Table 7 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: I/O
P0.0 — Port 0 bit0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input 0. I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1. I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2. I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input 3. I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input 4. I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input 5. I/O
P0.6 — Port 0 bit6.
CMP1 — Comparator 1 output.
KBI6 — Keyboard input 6. I/O
P0.7 — Port 0 bit7.
I/O
T1 — Timer/counter 1 external count input or overflow output.
KBI7 — Keyboard input 7.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 coreP1.0 - P1.7 18,17, 12,
11, 10, 6,
5, 4
I/O, I[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for
three pinsas noted below. During reset Port1 latches are configuredin the input only
mode with the internal pull-up disabled. The operationof the configurable Port1 pins
as inputs and outputs depends upon the port configuration selected. Each of the
configurable port pins are programmed independently. Refer to Section 8.11.1 “Port
configurations” and Table7 “DC electrical characteristics”for details. P1.2- P1.3 are
open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: I/O
P1.0 — Port 1 bit0.
TxD —T ransmitter output for the serial port. I/O
P1.1 — Port 1 bit1.
RXD — Receiver input for the serial port. I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter0 external count inputor overflow output (open-drain when used
as output).
I/O
SCL —I 2C serial clock input/output. I
P1.3 — Port 1 bit 3 (open-drain when used as output).
INT0 — External interrupt 0 input.
I/O
SDA —I 2C serial data input/output. I
P1.4 — Port 1 bit4.
INT1 — External interrupt 1 input.
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input during Power-on or if selected via UCFG1. When
functioningasa reset inputa LOWon thispin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.
When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage. I/O
P1.6 — Port 1 bit6. I/O
P1.7 — Port 1 bit7.
Table 3: Pin description…continued
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 coreP2.0 - P2.7 1, 2, 13,
14,15, 16,
27, 28
I/O
Port 2: Port 2 is a 8-bit I/O port with a user-configurable output type. During resetPort2 latches are configuredinthe input only mode with the internal pull-up disabled.
The operation of port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
This port is not available in 20-pin package and is configured automatically as
outputs to conserve power. The alternate functions for these pins must not be
enabled.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below. I/O
P2.0 — Port 2 bit 0. I/O
P2.1 — Port 2 bit 1. I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input. I/O
P2.3 — Port 2 bit 3.
I/O
MISO — SPI masterin slave out. When configuredas master, thispinis input, when
configured as slave, this pin is output. I/O
P2.4 — Port 2 bit 4.
SS — SPI Slave select. I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input. I/O
P2.6 — Port 2 bit 6. I/O
P2.7 — Port 2 bit 7.
Table 3: Pin description…continued
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.
P3.0 - P3.1 9, 8 I/O
Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset
Port3 latches are configuredinthe input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
8.11.1 “Port configurations” and Table 7 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below: I/O
P3.0 — Port 3 bit0.
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).
CLKOUT — CPU clock dividedby2 when enabledvia SFRbit (ENCLK- TRIM.6).It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer. I/O
P3.1 — Port 3 bit1.
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selectedvia the FLASH configuration).It canbea portpinif internal RC oscillatoror
Watchdog oscillator is used as the CPU clock source,
and if XTAL1/XTAL2 are notused to generate the clock for the real time clock/system timer.
VSS 7I
Ground: 0 V reference.
VDD 21 I
Power Supply: Thisis the power supply voltagefor normal operationas wellas Idle
and Power Down modes.
Table 3: Pin description…continued
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Logic symbol
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
User must
not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can
only be written and read as follows:‘-’ Unless otherwise specified,
mustbe written with ‘0’, but can return any value
when read (evenifit was written with ‘0’).Itisa reservedbit and maybe usedin
future derivatives.
‘0’
must be written with ‘0’, and will return a ‘0’ when read.‘1’
must be written with ‘1’, and will return a ‘1’ when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
ts are in input only (high impedance) state after po
er-up
ust only be wr
itten if BRGEN in BRGCON SFR is ‘0’. If an
y are wr
itten while BRGEN
1, the result is unpredic
tab
’-’) are X (unkno
wn) at all times
. Unless otherwise specified, ones should not be wr
itten to
these bits since the
y ma
y be used f
or other
poses in future der
ativ
. The reset v
alues sho
wn f
or these bits are
’0’
s although the
y are unkno
wn when read.
RSTSRC
register
reflects
the
cause
the
P89LPC930/931
reset.
Upon
er-up
reset,
all
reset
source
flags
are
cleared
xcept
POF
and
BOF;
the
er-on
reset
alue
reset,
the
alue
111001x1,
i.e
PRE2-PRE0
are
all
‘1’,
WDR
and
WDCLK
WDT
bit
‘1’
after
atchdog
reset
and
‘0’
after
er-on
reset.
Other
resets
will
ect WDT
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
ects these SFRs is po
er-on reset.
Special function register
…contin
ued
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core Functional description
Remark: Please refer to the P89LPC930/931 User’s Manual for a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC930/931 usesan enhanced 80C51 CPU which runsat6 times the speed
of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1 Clock definitions
The P89LPC930/931 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure4) and can alsobe optionally dividedtoa slower frequency
(see Section 8.7 “CPU CLOCK (CCLK) modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executedin oneto two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2 CPU clock (OSCCLK)
The P89LPC930/931 provides several user-selectable oscillator optionsin generating
the CPU clock. This allows optimization for a range of needs from high precision to
lowest possible cost. These options are configured when the FLASH is programmed
and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator
using an external crystal, or an external clock source. The crystal oscillator can be
optimized for low, medium, or high frequency crystals covering a range from 20 kHz
to 12 MHz.
8.2.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.2.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
8.2.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
8.2.6 Clock output
The P89LPC930/931 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillatoris not being used. This condition occursif
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC930/931. This output is enabled by the ENCLK bit in the TRIM register. The
frequencyof this clock outputis1⁄2 thatof the CCLK.If the clock outputis not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.3 On-chip RC oscillator option
The P89LPC930/931 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room
temperature. End-user applications can writeto theTrim registerto adjust the on-chip
RC oscillator to other frequencies.
8.4 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuitis requiredto hold the devicein resetat power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.6 CPU CLock (CCLK) wake-up delay
The P89LPC930/931 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK
cycles plus 60to 100 μs. If the clock source is either the internal RC oscillator,
Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plusto 100 μs.
8.7 CPU CLOCK (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 256 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPUata lower rate, reducing power consumption.By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
modeby executingits normal programata lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC930/931 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLKis8 MHzor slower, the CLKLP SFRbit (AUXR1.7) canbe setto‘1’to lower the
power consumption further. On any reset, CLKLPis‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.9 Memory organization
The various P89LPC930/931 memory spaces are as follows: DATA
128 bytesof internal data memory space (00h:7Fh) accessed via director indirect
addressing, using instruction other than MOVX and MOVC.Allor partof the Stack
may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack maybein this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing. CODE kBof Code memory space, accessedas partof program execution and via the
MOVC instruction. The P89LPC930/931 has 4 kB/ 8 kB of on-chip Code memory.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.10 Interrupts
The P89LPC930/931 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The
P89LPC930/931 supports 13 interrupt sources: external interrupts 0 and 1, timers 0
and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,
watchdog/real-time clock, I2 C, keyboard, and comparators 1 and 2, and SPI.
Each interrupt source canbe individually enabledor disabledby settingor clearinga
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source canbe individually programmedto oneof four priority levelsby
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but notby another interruptof the sameor lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pendingat the startofan instruction, the requestof higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.10.1 External interrupt inputs
The P89LPC930/931 has two external interrupt inputsas wellas the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
These external interrupts canbe programmedtobe level-triggeredor edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC930/931 is put into Power-down Idle mode, the interrupt will cause the processorto wake-up and resume operation.
Refer to Section 8.13 “Power reduction modes” for details.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.11 I/O ports
The P89LPC930/931 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1
and2 are 8-bit ports, and Port3isa 2-bit port. The exact numberof I/O pins available
depend upon the clock and reset options chosen, as shown in Table5.
[1] Required for operation above 12 MHz.
Table 5: Number of I/O pins available
On-chip oscillator or
Watchdog oscillator
No external reset (except during power-up) 26
External RST pin supported[1] 25
External clock input No external reset (except during power-up) 25
External RST pin supported[1] 24
Low/medium/high
speed oscillator
(external crystal or
resonator)
No external reset (except during power-up) 24
External RST pin supported[1] 23
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.11.1 Port configurations
All but three I/O port pins on the P89LPC930/931 may be configured by software to
oneof four typesona bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may onlybe configuredtobe either input-onlyor
open-drain.
8.11.2 Quasi-bidirectional output configuration
Quasi-bidirectional outputs canbe usedas bothan input and output without the need reconfigure the port. Thisis possible because when the port outputsa logic HIGH,
it is weakly driven, allowing an external device to pull the pin LOW. When the pin is
driven LOW,itis driven strongly and ableto sinka fairly large current. These features
are somewhat similar to an open-drain output except that there are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC930/931 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to VDD, causing extra power consumption. Therefore, applying V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.11.3 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.11.4 Input-only configuration
The input-only port configuration hasno output drivers.Itisa Schmitt-triggered input
that also has a glitch suppression circuit.
8.11.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.
8.11.6 Port 0 analog functions
The P89LPC930/931 incorporates two Analog Comparators.In orderto give the best
analog function performance andto minimize power consumption, pins that are being
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.11.4.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.11.7 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices. After power-up, all I/O pins except P1.5, may be configured by software. Pin P1.5is input only. Pins P1.2 and P1.3 and are configurablefor either input-only
or open-drain.
Every output on the P89LPC930/931 has been designed to sink typical LED drive
current. However, thereisa maximum total output currentforall ports which must not
be exceeded. Please refer to Table 7 “DC electrical characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.12 Power monitoring functions
The P89LPC930/931 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.12.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software. Brownout detectionis enabled, the brownout condition occurs when VDD falls below
the brownout trip voltage, VBO (see Table 7 “DC electrical characteristics”), and is
negated when VDD rises above VBO. If the P89LPC930/931 device is to operate with
a power supply that can be below 2.7 V, BOE should be left in the unprogrammed
state so that the device can operate at 2.4 V, otherwise continuous brownout reset
may prevent the device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 7 “DC electrical characteristics” for specifications.
8.12.2 Power-on detection
The Power-on Detect hasa function similarto the Brownout detect, butis designedto
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.13 Power reduction modes
The P89LPC930/931 supports three different power reduction modes. These modes
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.13.1 Idle mode
Idle mode leaves peripherals runningin orderto allow themto activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
8.13.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC930/931 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage maybe reducedto the RAM keep-alive
voltage VRAM. This retains the RAM contents at the point where Power-down mode
was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM,
therefore it is highly recommended to wake up the processor via reset in this case.
VDD must be raised to within the operating range before the Power-down mode is
exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selectedas the system clock and the
RTC is enabled.
8.13.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTCis enabled.If the internal RC oscillatoris usedto clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
8.14 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW duringa power-on sequenceas this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: Duringa power cycle, VDD must fall below VPOR (seeT able7 “DC electrical
characteristics”on page 42) before poweris reapplied,in orderto ensurea power-on
reset.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz.) Power-on detect Brownout detect Watchdog Timer Software reset UART break character detect reset
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set: During a power-on reset, both POF and BOF are set but the other flag bits are
cleared. For any other reset, previously set flag bits that have not been cleared will remain
set.
8.14.1 Reset vector
Following reset, the P89LPC930/931 will fetch instructions from either address 0000h the Boot address. The Boot addressis formedby using the Boot Vectoras the high
byte of the address and the low byte of the address= 00h.
The Boot address willbe usedifa UART break reset occurs,or the non-volatile Boot
Status bit (BOOTST AT.0)= 1, or the device is forced into ISP mode during power-on
(see P89LPC930/931 User’s Manual). Otherwise, instructions will be fetched from
address 0000H.
8.15 Timers/counters 0 and 1
The P89LPC930/931 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to
operate either as timers or event counter. An option to automatically toggle the T0
and/or T1 pins upon timer overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle. the ‘Counter’ function, the registeris incrementedin responsetoa 1-to-0 transition
at its corresponding external input pin, T0 or T1. In this function, the external input is
sampled once during every machine cycle.
Timer0 and Timer1 have five operating modes (modes0,1,2,3 and6). Modes0,1,
2 and 6 are the same for both Timers/Counters. Mode 3 is different.
8.15.1 Mode0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer1.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.15.3 Mode2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer1.
8.15.4 Mode3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.15.5 Mode6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
8.15.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic‘1’
prior to the first timer overflow when this mode is turned on.
8.16 Real-Time clock/system timer
The P89LPC930/931 has a simple Real-Time clock that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF
flag willbe set. The clock sourcefor this counter canbe either the CPU clock (CCLK) the XTAL oscillator, provided that the XTAL oscillatoris not being usedas the CPU
clock.If the XTAL oscillatoris usedas the CPU clock, then the RTC will use CCLKas
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.
8.17 UART
The P89LPC930/931 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud
rate source. The P89LPC930/931 does include an independent Baud Rate
Generator. The baud rate canbe selected from the oscillator (dividedbya constant),
Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud
rate generation, enhancements over the standard 80C51 UART include Framing
Error detection, automatic address recognition, selectable double buffering and
several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit
UART , 9-bit UART , and CPU clock/32 or CPU clock/16.
8.17.1 Mode0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at1 ⁄16 of the CPU clock
frequency.
Philips Semiconductors P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
8.17.2 Mode1 bits are transmitted (through TxD)or received (through RxD):a startbit (logic ‘0’), data bits (LSB first), and a stop bit (logic ‘1’). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 8.17.5 “Baud rate generator and selection”).
8.17.3 Mode2 bits are transmitted (through TxD) or received (through RxD): start bit (logic ‘0’), data bits (LSB first), a programmable 9th data bit, and a stop bit (logic ‘1’). When
datais transmitted, the9th databit (TB8in SCON) canbe assigned the valueof‘0’or
‘1’. Or, for example, the parity bit (P , in the PSW) could be moved into TB8. When
data is received, the 9th data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either1 ⁄16 or1 ⁄32 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
8.17.4 Mode3 bits are transmitted (through TxD)or received (through RxD):a startbit (logic ‘0’),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic ‘1’). In fact,
Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate
Generator (described in section Section 8.17.5 “Baud rate generator and selection”).
8.17.5 Baud rate generator and selection
The P89LPC930/931 enhanced UART has an independent Baud Rate Generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and
BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a
similar manneras Timer1.If the baud rate generatoris used, Timer1 canbe usedfor
other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 6).
Note that TimerT1is further dividedby2if the SMOD1bit (PCON.7)is cleared. The
independent Baud Rate Generator uses OSCCLK.
8.17.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
