P89LPC924FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converterapplicationsdemanding high-integration, low cost solutions over a wide range of performancerequirem ..
P89LPC924FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converterapplicationsdemanding high-integration, low cost solutions over a wide range of performancerequirem ..
P89LPC925FDH ,P89LPC924/925; 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converterP89LPC924/9258-bit microcontrollers with accelerated two-clock 80C51 core4 kB/8 kB 3 V low-power Fl ..
P89LPC925FDH ,P89LPC924/925; 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converterfeatures■ 4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable pagesize, and si ..
P89LPC925FN ,P89LPC924/925; 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converterGeneral descriptionThe P89LPC924/925 are single-chip microcontrollers designed for
P89LPC930FDH ,8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAMP89LPC930/9318-bit microcontrollers with two-clock 80C51 core4 kB/8 kB 3 V Flash with 256-byte data ..
PCD-124D1MH , 15 Amp Low Profile Power PC Board Relay
PCD-148D1MH , 15 Amp Low Profile Power PC Board Relay
PCD3310T ,Pulse and DTMF diallers with redial
PCD3310T ,Pulse and DTMF diallers with redial
PCD3311 ,DTMF/modem/musical-tone generators
PCD3312 ,DTMF/modem/musical-tone generators
P89LPC924FDH-P89LPC925FDH-P89LPC925FN
P89LPC924/925; 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
P89LPC924/9258-bit microcontrollers with accelerated two-clock 80C51 core kB/8 kB 3 V low-power Flash with 8-bit A/D converter
Rev. 03 — 15 December 2004 Product data General descriptionThe P89LPC924/925 are single-chip microcontrollers designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC924/925 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC924/925 in order to reduce component count, board space, and system
cost.
Features
2.1 Principal features4 kB/8 kB Flash code memory with1kB erasable sectors, 64-byte erasable page
size, and single byte erase. 256-byte RAM data memory. Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output. Real-Time clock that can also be used as a system timer. 4-input 8-bit multiplexed A/D converter/single DAC output. T wo analog
comparators with selectable inputs and reference source. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities. 400 kHz byte-wide I2 C-bus communication port. Configurable on-chip oscillator with frequency range and RC oscillator options
(selectedby user programmed Flash configuration bits). The RC oscillator (factory
calibrated to±1 %) option allows operation without external oscillator
components. Oscillator options support frequencies from20 kHzto the maximum
operating frequency of 18 MHz. The RC oscillator option is selectable and fine
tunable. 2.4Vto 3.6V VDD operating range. I/O pins are5V tolerant (maybe pulledupor
driven to 5.5 V). 15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset
options.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
2.2 Additional features 20-pin TSSOP package. A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is six times the performance of the standard 80C51 running at the same
clock frequency. A lower clock frequency for the same performance results in
power savings and reduced EMI. In-Application Programming of the Flash code memory. This allows changing the
code in a running application. Serial Flash programming allows simple in-circuit production coding. Flash
security bits prevent reading of sensitive application programs. Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from eight values. Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt. Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1 μA (total Power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available. Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. Port ‘input pattern match’ detect. Port0 may generatean interrupt when the value
of the pins match or do not match a programmable pattern. LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip. Controlled slew rate port outputs to reduce EMI. Outputs have approximately ns minimum ramp times. Only power and ground connections are required to operate the P89LPC924/925
when internal reset option is selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Second data pointer. Schmitt trigger port inputs. Emulation support.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core Ordering information
3.1 Ordering options
Table 1: Ordering informationP89LPC924FDH TSSOP20 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT360-1
P89LPC925FDH TSSOP20 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT360-1
Table 2: Part optionsP89LPC924FDH 4kB −40°Cto +85°C 0 MHzto18 MHz
P89LPC925FDH 8kB −40°Cto +85°C 0 MHzto18 MHz
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core Block diagram
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core Pinning information
5.1 Pinning
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
5.2 Pin description
Table 3: Pin descriptionP0.0 - P0.7 1, 20, 19,
18,17, 16,
14, 13
I/O
Port0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operationof Port0 pinsas inputs and outputs depends uponthe port configuration
selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port
configurations” and Table 8 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: I/O
P0.0 — Port 0 bit0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input 0. I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1.
AD10 — ADC1 channel 0 analog input. I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2.
AD11 — ADC1 channel 1analog input. I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input 3.
AD12 — ADC1 channel 2 analog input. I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input 4.
AD13 — ADC1 channel 3 analog input.
DAC1 — Digital-to-analog converter output 1. I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input 5. I/O
P0.6 — Port 0 bit6.
CMP1 — Comparator 1 output.
KBI6 — Keyboard input 6. I/O
P0.7 — Port 0 bit7.
I/O
T1 — Timer/counter 1 external count input or overflow output.
KBI7 — Keyboard input 7.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 coreP1.0 - P1.7 12,11, 10,
9, 8, 4, 3,
I/O,I[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three
pins as noted below. During reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operationofthe configurable Port1 pinsas inputs
and outputs depends upon the port configuration selected. Each of the configurable
port pins are programmed independently. Refer to Section 8.13.1 “Port configurations”
and Table 8 “DC electrical characteristics” for details. P1.2 - P1.3 are open drain when
used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: I/O
P1.0 — Port 1 bit0.
TXD — Transmitter output for the serial port. I/O
P1.1 — Port 1 bit1.
RXD — Receiver input for the serial port. I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter0 external count inputor overflow output (open-drain when usedas
output).
I/O
SCL —I 2C serial clock input/output. I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
INT0 — External interrupt 0 input.
I/O
SDA —I 2C serial data input/output. I/O
P1.4 — Port 1 bit4.
INT1 — External interrupt 1 input.
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input (if selected via FLASH configuration). A LOW on this pin
resets the microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address0.
When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reachedits specified level. When system poweris removed VDD will fall below the
minimum specified operating voltage. When using an oscillator frequency above MHz, in some applications, an external brownout detect circuit may be
required to hold the device in reset when VDD falls below the minimum specified
operating voltage. I/O
P1.6 — Port 1 bit6. I/O
P1.7 — Port 1 bit7.
Table 3: Pin description…continued
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.
Logic symbolP3.0 - P3.1 7, 6 I/O
Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operationof Port3 pinsas inputs and outputs depends uponthe port configuration
selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port
configurations” and Table 8 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below: I/O
P3.0 — Port 3 bit0.
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration.
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the real time clock/system timer. I/O
P3.1 — Port 3 bit1.
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
watchdog oscillatoris usedas the CPU clock source,
andif XTAL1/XTAL2 are not used
to generate the clock for the real time clock/system timer.
VSS 5I
Ground: 0 V reference.
VDD 15 I
Power Supply: This is the power supply voltage for normal operation as well as Idleand Power Down modes.
Table 3: Pin description…continued
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
User must
not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can
only be written and read as follows:‘-’ Unless otherwise specified,
mustbe written with ‘0’, but can return any value
when read (evenifit was written with ‘0’).Itisa reservedbit and maybe usedin
future derivatives.
‘0’
must be written with ‘0’, and will return a ‘0’ when read.‘1’
must be written with ‘1’, and will return a ‘1’ when read.
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Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Special function register
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Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Special function register
…contin
ued
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Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
ts are in input only (high impedance) state after po
er-up
ust only be wr
itten if BRGEN in BRGCON SFR is ‘0’. If an
y are wr
itten while BRGEN
1, the result is unpredic
tab
RSTSRC
register
reflects
the
cause
the
P89LPC924/925
reset.
Upon
er-up
reset,
all
reset
source
flags
are
cleared
xcept
POF
and
BOF;
the
er-on
reset
alue
reset,
the
alue
111001x1,
i.e
PRE2-PRE0
are
all
‘1’,
WDR
and
WDCLK
WDT
bit
‘1’
after
atchdog
reset
and
‘0’
after
er-on
reset.
Other
resets
will
ect WDT
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
ects these SFRs is po
er-on reset.
Special function register
…contin
ued
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core Functional description
Remark: Please refer to the P89LPC924/925 User’s Manual for a more detailed
functional description.
8.1 Enhanced CPU
The P89LPC924/925 usesan enhanced 80C51 CPU which runsat6 times the speed
of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1 Clock definitions
The P89LPC924/925 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure4) and can alsobe optionally dividedtoa slower frequency
(see Section 8.7 “CPU Clock (CCLK) modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executedin oneto two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2 CPU clock (OSCCLK)
The P89LPC924/925 provides several user-selectable oscillator optionsin generating
the CPU clock. This allows optimization for a range of needs from high precision to
lowest possible cost. These options are configured when the FLASH is programmed
and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator
using an external crystal, or an external clock source. The crystal oscillator can be
optimized for low, medium, or high frequency crystals covering a range from 20 kHz
to 12 MHz.
8.2.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.2.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
8.2.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
8.2.6 Clock output
The P89LPC924/925 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillatoris not being used. This condition occursif
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC924/925. This output is enabled by the ENCLK bit in the TRIM register. The
frequencyof this clock outputis1⁄2 thatof the CCLK.If the clock outputis not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.3 On-chip RC oscillator option
The P89LPC924/925 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room
temperature. End-user applications can writeto theTrim registerto adjust the on-chip
RC oscillator to other frequencies.
8.4 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuitis requiredto hold the devicein resetat power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.6 CPU Clock (CCLK) wake-up delay
The P89LPC924/925 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK
cycles plus 60to 100 μs. If the clock source is either the internal RC oscillator,
watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plusto 100 μs.
8.7 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPUata lower rate, reducing power consumption.By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
modeby executingits normal programata lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
8.8 Low power select
The P89LPC924/925 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLKis8 MHzor slower, the CLKLP SFRbit (AUXR1.7) canbe setto‘1’to lower the
power consumption further. On any reset, CLKLPis‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.9 A/D converter
8.9.1 General description
The P89LPC924/925 has an 8-bit, 4-channel multiplexed successive approximation
analog-to-digital converter module. A block diagram of the A/D converter is shown in
Figure 5. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold
circuit providing an input signal to one of two comparator inputs. The control logic in
combination with the successive approximation register (SAR) drives a
digital-to-analog converter which provides the other input to the comparator. The
output of the comparator is fed to the SAR.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.9.2 Features 8-bit, 4-channel multiplexed input, successive approximation A/D converter. Four result registers. Six operating modes Fixed channel, single conversion mode Fixed channel, continuous conversion mode Auto scan, single conversion mode Auto scan, continuous conversion mode Dual channel, continuous conversion mode Single step mode Three conversion start modes Timer triggered start Start immediately Edge triggered 8-bit conversion time of≥ 3.9 μs at an ADC clock of 3.3 MHz Interrupt or polled operation Boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power down mode
8.9.3 A/D operating modes
Fixed channel, single conversion mode:A single input channel canbe selectedfor
conversion. A single conversion will be performed and the result placed in the result
register which correspondsto the selected input channel. An interrupt,if enabled, will
be generated after the conversion completes.
Fixed channel, continuous conversion mode: A single input channel can be
selectedfor continuous conversion. The resultsof the conversions willbe sequentially
placed in the four result registers. An interrupt, if enabled, will be generated after
every four conversions. Additional conversion results will again cycle through the four
result registers, overwriting the previous results. Continuous conversions continue
until terminated by the user.
Auto scan, single conversion mode: Any combination of the four input channels
can be selected for conversion. A single conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. If only a single channel is selected this is equivalent
to single channel, single conversion mode.
Auto scan, continuous conversion mode: Any combination of the four input
channels can be selected for conversion. A conversion of each selected input will be
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
channels have been converted. The process will repeat starting with the first selected
channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results. Continous conversions continue until
terminated by the user.
Dual channel, continuous conversion mode: This is a variation of the auto scan
continuous conversion mode where conversion occurson two user-selectable inputs.
The resultof the conversionof the first channelis placedin result register, AD1DAT0.
The result of the conversion of the second channel is placed in result register,
AD1DAT1. The first channelis again converted andits result storedin AD1DAT2. The
second channel is again converted and its result placed in AD1DAT3. An interrupt is
generated, if enabled, after every set of four conversions (two conversions per
channel).
Single step mode: This special mode allows ‘single-stepping’ in an auto scan
conversion mode. Any combination of the four input channels can be selected for
conversion. After each channel is converted, an interrupt is generated, if enabled,
and the A/D waits for the next start condition. May be used with any of the start
modes.
8.9.4 Conversion start modes
Timer triggered start: An A/D conversionis startedby the overflowof Timer0. Once
a conversion has started, additional Timer 0 triggers are ignored until the conversion
has completed. The Timer triggered start mode is available in all A/D operating
modes.
Start immediately: Programming this mode immediately starts a conversion. This
start mode is available in all A/D operating modes.
Edge triggered: An A/D conversion is started by rising or falling edge of P1.4. Once
a conversion has started, additional edge triggers are ignored until the conversion
has completed. The edge triggered start mode is available in all A/D operating
modes.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.9.5 Boundary limits interrupt
The A/D converter has both a high and low boundary limit register. After the four
MSBs have been converted, these four bits are compared with the four MSBs of the
boundary high and low registers. If the four MSBs of the conversion are outside the
limit an interrupt will be generated, if enabled. If the conversion result is within the
limits, the boundary limits will againbe compared afterall8 bits have been converted.
An interrupt will be generated, if enabled, if the result is outside the boundary limits.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
8.9.6 DAC output to a port pin with high output impedance
The A/D converter’s DAC block can be output to a port pin. In this mode, the
AD1DAT3 register is used to hold the value fed to the DAC. After a value has been
written to the DAC, the DAC output will appear on the channel 3 pin.
8.9.7 Clock divider
The A/D converter requires thatits internal clock sourcebein the rangeof 500 kHzto
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from1to 8 is provided for this purpose.
8.9.8 Power-down and idle mode idle mode the A/D converter,if enabled, will continueto function and can cause the
device to exit idle mode when the conversion is completed if the A/D interrupt is
enabled.In Power-down modeor Total power-down mode, the A/D does not function.
If the A/D is enabled, it will consume power. Power can be reduced by disabling the
A/D.
8.10 Memory organization
The various P89LPC924/925 memory spaces are as follows: DATA
128 bytesof internal data memory space (00h:7Fh) accessed via director indirect
addressing, using instruction other than MOVX and MOVC.Allor partof the Stack
may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack maybein this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing. CODE kBof Code memory space, accessedas partof program execution and via the
MOVC instruction. The P89LPC924/925 has 4 kB/8 kB of on-chip Code memory.
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.11 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in Table5.
8.12 Interrupts
The P89LPC924/925 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The
P89LPC924/925 supports 13 interrupt sources: A/D converter, external interrupts 0
and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx,
brownout detect, watchdog/real-time clock, I2 C, keyboard, and comparators 1 and 2.
Each interrupt source canbe individually enabledor disabledby settingor clearinga
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source canbe individually programmedto oneof four priority levelsby
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but notby another interruptof the sameor lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pendingat the startofan instruction, the requestof higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.12.1 External interrupt inputs
The P89LPC924/925 has two external interrupt inputsas wellas the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
These external interrupts canbe programmedtobe level-triggeredor edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC924/925 is put into Power-down Idle mode, the interrupt will cause the processorto wake-up and resume operation.
Refer to Section 8.15 “Power reduction modes” for details.
Table 5: On-chip data memory usages
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.13 I/O ports
The P89LPC924/925 has three I/O ports: Port0, Port1, and Port3. Ports0 and1 are
8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depend
upon the clock and reset options chosen, as shown in Table6.
[1] Required for operation above 12 MHz.
Table 6: Number of I/O pins available
On-chip oscillator or
watchdog oscillator
No external reset (except during power-up) 18
External RST pin supported[1] 17
External clock input No external reset (except during power-up) 17
External RST pin supported[1] 16
Low/medium/high speed
oscillator (external
crystal or resonator)
No external reset (except during power-up) 16
External RST pin supported[1] 15
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
8.13.1 Port configurations
All but three I/O port pins on the P89LPC924/925 may be configured by software to
oneof four typesona bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may onlybe configuredtobe either input-onlyor
open-drain.
8.13.2 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC924/925 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to VDD, causing extra power consumption. Therefore, applying V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.13.3 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to VDD.
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
8.13.4 Input-only configuration
The input-only port configuration hasno output drivers.Itisa Schmitt-triggered input
that also has a glitch suppression circuit.
8.13.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.
8.13.6 Port 0 analog functions
The P89LPC924/925 incorporates two Analog Comparators.In orderto give the best
analog function performance andto minimize power consumption, pins that are being
Philips Semiconductors P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in Section 8.13.4.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.
8.13.7 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices. After power-up, all I/O pins except P1.5, may be configured by software. Pin P1.5is input only. Pins P1.2 and P1.3 and are configurablefor either input-only
or open-drain.
Every output on the P89LPC924/925 has been designed to sink typical LED drive
current. However, thereisa maximum total output currentforall ports which must not
be exceeded. Please refer to Table 8 “DC electrical characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC924/925 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.14.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software. Brownout detectionis enabled, the brownout condition occurs when VDD falls below
the brownout trip voltage, VBO (see Table 8 “DC electrical characteristics”), and is
negated when VDD rises above VBO. If the P89LPC924/925 device is to operate with
a power supply that can be below 2.7 V, BOE should be left in the unprogrammed
state so that the device can operate at 2.4 V, otherwise continuous brownout reset
may prevent the device from operating.
For correct activation of Brownout detect, the VDD rise and fall times must be
observed. Please see Table 8 “DC electrical characteristics” for specifications.
8.14.2 Power-on detection
The Power-on Detect hasa function similarto the Brownout detect, butis designedto
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
