P89LPC915FN-P89LPC917FDH Fast Delivery |IC PHOENIX CO.,LIMITED

P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and16- ..
P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers, available in low-cost pa ..
P89LPC920FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMFeatures2.1 Principal
P89LPC921FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMP89LPC920/921/9228-bit microcontrollers with two-clock 80C51 core2 kB/4 kB/8 kB 3 V low-power Flash ..
P89LPC922FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMP89LPC920/921/9228-bit microcontrollers with two-clock 80C51 core2 kB/4 kB/8 kB 3 V low-power Flash ..
P89LPC922FN ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMfeatures■ 2 kB/4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasablepage size, a ..
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P89LPC915FN-P89LPC917FDH
8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
General descriptionThe P89LPC915/916/917 are single-chip microcontrollers, availablein low-cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC915/916/917 in order to reduce component
count, board space, and system cost. Features
2.1 Principal features 2 kB byte-erasable ﬂash code memory organized into 256-byte sectors and 16-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 256-byte RAM data memory. Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be conﬁgured to
toggle a port output upon timer overﬂow or to become a PWM output. 23-bit system timer that can also be used as a Real-Time clock. 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog comparators
with selectable reference. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities. SPI communication port (P89LPC916). Internal RC oscillator option allows operation without external oscillator components.
The RC oscillator (factory calibrated to±1 %) option is selectable and ﬁne tunable. 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V). Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,
P89LPC917).
2.2 Additional features 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages. A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequencyfor the same performance resultsin power savings and reduced
EMI. In-Application Programming (IAP-Lite) and byte erase allows code memorytobe used
for non-volatile data storage.
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
2 kB 3 V ﬂash with 8-bit A/D converter
Rev. 05 — 15 December 2009 Product data sheet
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs. Watchdog timer with separate on-chip oscillator, requiring no external components.
The Watchdog prescaler is selectable from 8 values. Low voltage brownout detect allows a graceful system shutdown when power fails.
May optionally be conﬁgured as an interrupt. Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available. Programmable port output conﬁguration options: quasi-bidirectional, open drain,
push-pull, input-only. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern. LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the
entire chip. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns
minimum ramp times. Only power and ground connections are required to operate the P89LPC915/916/917
when internal reset option is selected. Four interrupt priority levels. Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt inputs. Second data pointer. Schmitt trigger port inputs. Emulation support. Product comparison overview
Table 1 highlights the differences between these three devices. For a complete list of
device features, please see Section 2 “Features”.
Table 1. Product comparison overview
P89LPC915 X - - - X 6
P89LPC916 - X - - - 5
P89LPC917 X - X X X 7
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Ordering information
4.1 Ordering options
[1] Please contact your local NXP sales ofﬁce for availability of extended temperature (−40°Cto +125°C)
versions of the P89LPC916 and P89LPC917 devices.
Table 2. Ordering information
P89LPC915FDH TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
P89LPC915FN DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
P89LPC915HDH TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
P89LPC916FDH TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
P89LPC917FDH TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
Table 3. Ordering options[1]
P89LPC915FDH −40°Cto +85°C 0 MHzto18 MHz
P89LPC915FN
P89LPC916FDH
P89LPC917FDH
P89LPC915HDH −40°Cto +125°C
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Block diagram
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Functional diagram
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Pinning information
7.1 Pinning
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
7.2 Pin description
Table 4. P89LPC915 pin description
P0.0 to P0.5 I/O Port0: Port 0 is a 6-bit I/O port with a user-conﬁgurable output type.
During reset Port0 latches are conﬁguredin the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port conﬁguration selected. Each port pin is
conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”
and Table 15 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/KBI0 2 I/O P0.0 — Port 0 bit0. CMP2 — Comparator 2 output. KBI0 — Keyboard input0.
P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit1. CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input1. AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/KBI2/AD11 14 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive input A. KBI2 — Keyboard input2. AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/KBI3/AD12 13 I/O P0.3 — Port 0 bit3. CIN1B — Comparator 1 positive input B. KBI3 — Keyboard input3. AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/KBI4/AD13/
DAC1 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive input A. KBI4 — Keyboard input4. AD13 — ADC1 channel 3 analog input. DAC1 — DAC1 analog output.
P0.5/CMPREF/KBI5/CLKIN 11 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5. CLKIN — External clock input.
P1.0 to P1.5 I/O,I
[1] Port 1: Port 1 is a 6-bit I/O port with a user-conﬁgurable output type,
except for three pins as noted below. During reset Port 1 latches are
conﬁgured in the input only mode with the internal pull-up disabled. The
operation of the conﬁgurable Port 1 pins as inputs and outputs depends
upon the port conﬁguration selected. Each of the conﬁgurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Input/output for P1.0 to P1.4. Input for P1.5.
P1.0/TXD 9 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for serial port.
P1.1/RXD 8 I/O P1.1 — Port 1 bit1. RXD — Receiver input for serial port.
P1.2/T0/SCL 7 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter0 external count inputor overﬂow output (open-drain
when used as output).
I/O SCL —I2 C serial clock input/output.
P1.3/INT0/SDA 6 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input.
I/O SDA —I2 C serial data input/output.
P1.4/INT1 5 I P1.4 — Port 1 bit4. INT1 — External interrupt 1 input.
P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only). RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used
during a power-on sequence to force ISP mode. When using an
oscillator frequency above 12 MHz, the reset input function of P1.5
mustbe enabled.An external circuitis requiredto hold the devicein
reset at power-up until VDD has reached its speciﬁed level. When
system power is removed VDD will fall below the minimum speciﬁed
operating voltage. When using an oscillator frequency above MHz, in some applications, an external brownout detect circuit
maybe requiredto hold the devicein reset when VDD falls below the
minimum speciﬁed operating voltage.
VSS 4I Ground: 0 V reference.
VDD 10 I Power supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes.
Table 4. P89LPC915 pin description …continued
Table 5. P89LPC916 pin description
P0.0 to P0.5 I/O Port0: Port 0 is an 6-bit I/O port with a user-conﬁgurable output type.
During reset Port 0 latches are conﬁgured in the input only mode with
the internal pull-up disabled. The operationof Port0 pinsas inputs and
outputs depends upon the port conﬁguration selected. Each port pin is
conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”
and Table 15 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit1. CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input1. AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/KBI2/AD11 16 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive input A. KBI2 — Keyboard input2. AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/KBI3/AD12 15 I/O P0.3 — Port 0 bit3. CIN1B — Comparator 1 positive input B. KBI3 — Keyboard input3. AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/KBI4/AD13/DAC1 14 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive input A. KBI4 — Keyboard input4. AD13 — ADC1 channel 3 analog input. DAC1 — DAC1 analog output.
P0.5/CMPREF/KBI5/CLKIN 13 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5. CLKIN — External clock input.
P1.0 to P1.5 I/O,I
[1] Port 1: Port 1 is an 6-bit I/O port with a user-conﬁgurable output type,
except for three pins as noted below. During reset Port 1 latches are
conﬁguredinthe input only mode with the internal pull-up disabled. The
operationof the conﬁgurable Port1 pinsas inputs and outputs depends
upon the port conﬁguration selected. Eachof the conﬁgurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 10 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for serial port.
P1.1/RXD 9 I/O P1.1 — Port 1 bit1. RXD — Receiver input for serial port.
P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overﬂow output
(open-drain when used as output).
I/O SCL —I2 C serial clock input/output.
P1.3/INT0/SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input.
I/O SDA —I2 C serial data input/output.
P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only).
Table 5. P89LPC916 pin description …continued
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Input/output for P1.0 to P1.3. Input for P1.5. RST — External Reset input during power-onorif selectedvia UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor begins execution at address 0. Also
used during a power-on sequence to force ISP mode. When using an
oscillator frequency above12 MHz, the reset input functionof P1.5
must be enabled. An external circuit is required to hold the device resetat power-up until VDD has reachedits speciﬁed level. When
system power is removed VDD will fall below the minimum
speciﬁed operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect
circuit may be required to hold the device in reset when VDD falls
below the minimum speciﬁed operating voltage.
P2.2 to P2.5 Port 2: Port 2 is a 4-bit I/O port with a user-conﬁgurable output type.
During reset Port 2 latches are conﬁgured in the input only mode with
the internal pull-up disabled. The operationof Port2 pinsas inputs and
outputs depends upon the port conﬁguration selected. Each port pin is
conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”
and Table 15 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 6 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slavein. When conﬁguredas master, thispinis
output; when conﬁgured as slave, this pin is input.
P2.3/MISO 5 I/O P2.3 — Port 2 bit3.
I/O MISO — When conﬁguredas master, thispinis input, when conﬁgured
as slave, this pin is output.
P2.4/SS 2 I/O P2.4 — Port 2 bit4.
I/O SS — SPI Slave select.
P2.5/SPICLK 11 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output;
when conﬁgured as slave, this pin is input.
VSS 4I Ground: 0 V reference.
VDD 12 I Power supply: Thisisthe power supply voltagefor normal operationas
well as Idle and Power-down modes.
Table 5. P89LPC916 pin description …continued
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 6. P89LPC917 pin description
P0.0 to P0.5, P0.7 I/O Port0: Port 0 is a 7-bit I/O port with a user-conﬁgurable output type.
During reset Port0 latches are conﬁguredin the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port conﬁguration selected. Each port pin is
conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”
and Table 15 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/KBI0 2 I/O P0.0 — Port 0 bit0. CMP2 — Comparator 2 output. KBI0 — Keyboard input0.
P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit1. CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input1. AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/KBI2/AD11 16 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive input A. KBI2 — Keyboard input2. AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/KBI3/AD12 15 I/O P0.3 — Port 0 bit3. CIN1B — Comparator 1 positive input B. KBI3 — Keyboard input3. AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/KBI4/AD13/
DAC1 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive input A. KBI4 — Keyboard input4. AD13 — ADC1 channel 3 analog input. DAC1 — DAC1 analog output.
P0.5/CMPREF/KBI5 13 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5. CLKIN — External clock input.
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P0.7/T1/KBI7/CLKOUT 11 I/O P0.7 — Port 0 bit7.
I/O T1 — Timer/counter 1 external count input or overﬂow output. KBI7 — Keyboard input7. CLKOUT — Clock output.
P1.0 to P1.5 I/O,I
[1] Port 1: Port 1 is a 6-bit I/O port with a user-conﬁgurable output type,
except for three pins as noted below. During reset Port 1 latches are
conﬁgured in the input only mode with the internal pull-up disabled. The
operation of the conﬁgurable Port 1 pins as inputs and outputs depends
upon the port conﬁguration selected. Each of the conﬁgurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 10 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for serial port.
P1.1/RXD 9 I/O P1.1 — Port 1 bit1. RXD — Receiver input for serial port.
P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter0 external count inputor overﬂow output (open-drain
when used as output).
I/O SCL —I2 C serial clock input/output.
P1.3/INT0/SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input.
I/O SDA —I2 C serial data input/output.
P1.4/INT1 6 I P1.4 — Port 1 bit4. INT1 — External interrupt 1 input.
P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only). RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used
during a power-on sequence to force ISP mode. When using an
oscillator frequency above 12 MHz, the reset input function of P1.5
mustbe enabled.An external circuitis requiredto hold the devicein
reset at power-up until VDD has reached its speciﬁed level. When
system power is removed VDD will fall below the minimum speciﬁed
operating voltage. When using an oscillator frequency above MHz, in some applications, an external brownout detect circuit
maybe requiredto hold the devicein reset when VDD falls below the
minimum speciﬁed operating voltage.
Table 6. P89LPC917 pin description …continued
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Input/output for P1.0 to P1.4. Input for P1.5.
P2.2 5 Port2: Port2isa singlebit I/O port witha user-conﬁgurable output type.
During reset Port2 latches are conﬁguredin the input only mode with the
internal pull-up disabled. The operation of this Port 2 pin as an input and
output depends upon the port conﬁguration selected. Refer to Section
8.13.1 “Port conﬁgurations” and Table 15 “Static characteristics” for
details.
This pin has a Schmitt triggered input.
VSS 4I Ground: 0 V reference.
VDD 12 I Power supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes.
Table 6. P89LPC917 pin description …continued
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Functional description
8.1 Special function registers
Remark: SFR accesses are restricted in the following ways: User must not attempt to access any SFR locations not deﬁned. Accessesto any deﬁned SFR locations mustbe strictlyfor the functionsfor the SFRs. SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives. ‘0’ must be written with ‘0’, and will return a ‘0’ when read. ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
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NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 7.
P89LPC915 special function register
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NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 7.
P89LPC915 special function register
…contin
ued
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NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 7.
P89LPC915 special function register
…contin
ued
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NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
All por
ts are in input only (high-impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a po
er-up reset, all reset source ﬂags are clear
ed e
xcept POF and BOF; the po
er-on reset
alue is xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 7.
P89LPC915 special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 8.
P89LPC916 special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 8.
P89LPC916 special function register
…contin
ued
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NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 8.
P89LPC916 special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
All por
ts are in input only (high-impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a po
er-up reset, all reset source ﬂags are clear
ed e
xcept POF and BOF; the po
er-on reset
alue is xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 8.
P89LPC916 special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 9.
P89LPC917 special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 9.
P89LPC917 special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
le 9.
P89LPC917 special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
All por
ts are in input only (high-impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a po
er-up reset, all reset source ﬂags are clear
ed e
xcept POF and BOF; the po
er-on reset
alue is xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 9.
P89LPC917 special function register
…contin
ued
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.2 Enhanced CPU
The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the
speedof standard 80C51 devices.A machine cycle consistsof two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock deﬁnitions
The P89LPC915/916/917 device has several internal clocks as deﬁned below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 11) and can also be optionally divided to a slower frequency (see
Section 8.8 “CCLK modiﬁcation: DIVM register”).
Note: fosc is deﬁned as the OSCCLK frequency.
CCLK — CPU clock; outputof the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executedin oneto two machine cycles (twoor four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
8.3.2 CPU clock (OSCCLK)
The P89LPC915/916/917 provides several user-selectable oscillator optionsin generating
the CPU clock. This allows optimizationfora rangeof needs from high precisionto lowest
possible cost. These options are conﬁgured when the ﬂashis programmed and includean
on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock source.
8.3.3 Clock output (P89LPC917)
The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin.
This allows external devices to synchronize to the P89LPC917. This output is enabled by
the ENCLK bit in the TRIM register.
The frequencyof this clock outputis1⁄2 thatof the CCLK.If the clock outputis not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.4 On-chip RC oscillator option
The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz±1 % at room
temperature. End-user applications can write to the TRIM register to adjust the on-chip
RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) canbe setto logic1to reduce power consumption. On reset, CLKLPis logic0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
8.5 Watchdog oscillator option
The watchdog hasa separate oscillator which hasa frequencyof 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.6 External clock input option
In this conﬁguration, the processor clock is derived from an external source driving the
CLKIN pin. The rate may be from 0 Hz up to 18 MHz.
When using an external clock input frequency above 12 MHz, the reset input
function of P1.5 must be enabled. An external circuit is required to hold the device resetat power-up until VDD has reachedits speciﬁed level. When system poweris
removed VDD will fall below the minimum speciﬁed operating voltage. When using
an external clock input frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when VDD falls
below the minimum speciﬁed operating voltage.
8.7 CCLK wake-up delay
The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it
stabilizes. The delay is 224 OSCCLK cycles plus 60 μsto100 μs.
8.8 CCLK modiﬁcation: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the abilityto respondto events that would not exit Idle modeby executingits normal
programata lower rate. This can also allow bypassing the oscillator start-up timein cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.9 Low power select
The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the
power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.10 Memory organization
The various P89LPC915/916/917 memory spaces are as follows: DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing. CODE kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC915/916/917 devices have 2 kB of on-chip Code
memory.
8.11 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown inT able 10.
8.12 Interrupts
The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great
ﬂexibility in controlling the handling of the many interrupt sources.
The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0 and
1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout
detect, watchdog/RTC, I2 C-bus, keyboard, comparators 1 and 2, and ADC completion.
The P89LPC916 supports 14 interrupt sources: external interrupts 0 and 1, timers 0 and
1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,
watchdog/RTC, I2 C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion.
Table 10. On-chip data memory usages
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Each interrupt source canbe individually enabledor disabledby settingor clearingabitin
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
notby another interruptof the sameor lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
8.12.1 External interrupt inputs
The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has
one external interrupt input. These external interrupt inputs are identical to those present
on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt
function.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down
or Idle mode, the interrupt will cause the processor to wake-up and resume operation.
Refer to Section 8.15 “Power reduction modes” for details.
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.13 I/O ports
The P89LPC916 and P89LPC917 devices have three I/O ports: Port0, Port1, and Port2.
The exact numberof I/O pins available depends upon the clock and reset options chosen,
as shown in Table 11.
[1] Required for operation above 12 MHz.
The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins
available depends upon the clock and reset options chosen, as shown in Table 12.
[1] Required for operation above 12 MHz.
8.13.1 Port conﬁgurations
All but three I/O port pins on the P89LPC915/916/917 may be conﬁgured by software to
oneof four typesona bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. T wo conﬁguration registers for each port
select the output type for each port pin. P1.5 (RST) can only be an input and cannot be conﬁgured. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may onlybe conﬁguredtobe either input-onlyor
open-drain.
8.13.1.1 Quasi-bidirectional output conﬁguration
Quasi-bidirectional output type canbe usedas bothan input and output without the need
to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similartoan open-drain output except that there are three pull-up transistorsin
the quasi-bidirectional output that serve different purposes.
Table 11. Number of I/O pins available (P89LPC916 and P89LPC917)
RC oscillator or watchdog
oscillator
No external reset (except during
power-up)
External RST pin supported 13
External clock input No external reset (except during
power-up)
External RST pin supported[1] 12
Table 12. Number of I/O pins available (P89LPC915)
RC oscillator or watchdog
oscillator
No external reset (except during
power-up)
External RST pin supported 11
External clock input No external reset (except during
power-up)
External RST pin supported[1] 10
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
The P89LPC915/916/917 is a 3 V device, but the pins are 5 V tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing
from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in
quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
8.13.1.2 Open-drain output conﬁguration
The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output,a port conﬁguredin this manner must havean external pull-up, typicallya resistor
tied to VDD.
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
8.13.1.3 Input-only conﬁguration
The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that
also has a glitch suppression circuit.
8.13.1.4 Push-pull output conﬁguration
The push-pull output conﬁguration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a
Schmitt triggered input that also has a glitch suppression circuit.
8.13.2 Port 0 analog functions
The P89LPC915/916/917 incorporates two Analog Comparators.In orderto give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any
reset, PT0AD bits default to ‘0’s to enable digital functions.
8.13.3 Additional port features
After power-up, all pins are in Input-Only mode. After power-up, all I/O pins except P1.5,
may be conﬁgured by software. Pin P1.5 is input only. Pins P1.2 and P1.3 are conﬁgurable for either input-only or open-drain.
Every output on the P89LPC915/916/917 has been designed to sink typical LED drive
current. However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 15 “Static characteristics” for detailed speciﬁcations.
NXP Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
All ports pins that can functionasan output have slew rate controlled outputsto limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC915/916/917 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during operation.
This is accomplished with two hardware functions: Power-on detect and brownout detect.
8.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. The default operationisfora brownout detectionto causea processor reset,
however it may alternatively be conﬁgured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If brownout detection is enabled the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (seeT able15 “Static characteristics”), andis negated when VDD
rises above Vbo. If the P89LPC915/916/917 device is to operate with a power supply that
canbe below 2.7V, BOE shouldbe leftin the unprogrammed stateso that the device can
operate at 2.4V , otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of brownout detect, the VDD rise and fall times must be observed.
Please see Table 15 “Static characteristics” for speciﬁcations.
8.14.2 Power-on detection
The Power-on detect hasa function similarto the brownout detect, butis designedto work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an
initial power-up condition. The POF ﬂag will remain set until cleared by software.
8.15 Power reduction modes
The P89LPC915/916/917 supports three different power reduction modes: Idle mode,
Power-down mode, and total Power-down mode.
8.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
8.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC915/916/917 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the data retention
voltage VDDR. This retains the RAM contents at the point where Power-down mode was
entered. SFR contents are not guaranteed after VDD has been loweredto VDDR, therefore
it is highly recommended to wake-up the processor via reset in this case. VDD must be
raised to within the operating range before the Power-down mode is exited.

Partno	Mfg	Dc	Qty	Available	Descript
P89LPC915FN	NXP	N/a	864	avai	8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
P89LPC917FDH	NXP	N/a	2500	avai	8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter