P89LPC916FDH ,P89LPC915/916/917; 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and16- ..
P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and16- ..
P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers, available in low-cost pa ..
P89LPC920FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMFeatures2.1 Principal
P89LPC921FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMP89LPC920/921/9228-bit microcontrollers with two-clock 80C51 core2 kB/4 kB/8 kB 3 V low-power Flash ..
P89LPC922FDH ,8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAMP89LPC920/921/9228-bit microcontrollers with two-clock 80C51 core2 kB/4 kB/8 kB 3 V low-power Flash ..
PCB80C562-16WP , Single-chip 8-bit microcontroller
PCB80C562-16WP , Single-chip 8-bit microcontroller
PCD-124D1MH , 15 Amp Low Profile Power PC Board Relay
PCD-148D1MH , 15 Amp Low Profile Power PC Board Relay
PCD3310T ,Pulse and DTMF diallers with redial
PCD3310T ,Pulse and DTMF diallers with redial
P89LPC915FDH-P89LPC916FDH-P89LPC917FDH
P89LPC915/916/917; 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converter
P89LPC915/916/9178-bit microcontrollers with accelerated two-clock 80C51 core kB 3 V Flash with 8-bit A/D converter
Rev. 04 — 17 December 2004 Product data General descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and
16-pin packages, based on a high performance processor architecture that executes
instructionsin twoto four clocks, six times the rateof standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC915/916/917in order
to reduce component count, board space, and system cost.
Features 2 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage. 256-byte RAM data memory. Two 16-bit counter/timers. Timer0 (and Timer1- P89LPC917) maybe configured
to toggle a port output upon timer overflow or to become a PWM output. 23-bit system timer that can also be used as a Real-Time clock. 4-input multiplexed 8-bit A/D converter/single DAC output. T wo analog
comparators with selectable reference. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities. SPI communication port (P89LPC916). Internal RC oscillator option allows operation without external oscillator
components. The RC oscillator (factory calibrated to±1 %) option is selectable
and fine tunable. 2.4Vto 3.6V VDD operating range. I/O pins are5V tolerant (maybe pulledupor
driven to 5.5 V). Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,
P89LPC917).
Additional features 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages.
A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
Thisissix times the performanceof the standard 80C51 runningat the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.
Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent readingof sensitive
application programs.
Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog prescaler is selectable from 8 values.
Low-voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.
Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
Port ‘input pattern match’ detect. Port0 may generatean interrupt when the value
of the pins match or do not match a programmable pattern.
LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
Controlled slew rate port outputsto reduce EMI. Outputs have approximately10ns
minimum ramp times.
Only power and ground connections are required to operate the
P89LPC915/916/917 when internal reset option is selected.
Four interrupt priority levels.
Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt
inputs.
Second data pointer.
Schmitt trigger port inputs.
Emulation support.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Ordering information
4.1 Ordering options[1] Please contact your local Philips sales office for availability of extended temperature
(−40°Cto +125 °C) versions of the P89LPC916 and P89LPC917 devices.
Table 1: Ordering informationP89LPC915FDH TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
P89LPC915HDH TSSOP14 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT402-1
P89LPC916FDH TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
P89LPC917FDH TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
Table 2: Ordering options[1]
P89LPC915HDH −40°Cto +125°C 0 MHzto18 MHz
P89LPC915FDH −40 °Cto+85°C
P89LPC916FDH
P89LPC917FDH
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Block diagram
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Pinning information
6.1 Pinning
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
6.2 Pin description
Table 3: P89LPC915 pin description P0.0 to P0.5 I/O
Port0: Port 0 is a 6-bit I/O port with user-configurable outputs. During reset Port0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: I/O
P0.0 — Port 0 bit0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input0. I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive inputB.
KBI1 — Keyboard input1.
AD10 — A/D channel 1, input 0 I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive inputA.
KBI2 — Keyboard input2.
AD11 — A/D channel 1, input 1 I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive inputB.
KBI3 — Keyboard input3.
AD12 — A/D channel 1, input 2. I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive inputA.
KBI4 — Keyboard input4.
AD13 — A/D channel 1, input3.
DAC1 — Digital to analog converter 1 output. I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input5.
CLKIN — External clock input.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 coreP1.0 to P1.5 I/O
(P1.2); (P1.5)
Port1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the inputs and outputs depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details. P1.2 is an open drain when used as an output. P1.5 is
input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: I/O
P1.0 — Port 1 bit0
TxD — Serial port transmitter data. I/O
P1.1 — Port 1 bit0
RxD — Serial port receiver data. I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow output, or PWM output.
I/O
SCL —I 2C-bus serial clock input/output. I/O
P1.3 — Port 1 bit 2. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA —I 2C-bus serial data input/output. I/O
P1.4 — Port 1 bit2.
I/O
INT1 — External interrupt 1input.
P1.5 — Port 1 bit 5. (Input only.)
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0.
When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.Also used during a power-on sequence to force In-System Programming mode.
VSS 4I
Ground: 0 V reference.
VDD 10 I
Power Supply: This is the power supply voltage for normal operation as well as Idleand Power-down modes.
Table 3: P89LPC915 pin description…continued
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4: P89LPC916 pin description P0.1 to P0.5 I/O
Port0: Port 0 is a 5-bit I/O port with user-configurable outputs. During reset Port0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive inputB.
KBI1 — Keyboard input1.
AD10 — A/D channel 1, input 0 I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive inputA.
KBI2 — Keyboard input2.
AD11 — A/D channel 1, input 1 I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive inputB.
KBI3 — Keyboard input3.
AD12 — A/D channel 1, input 2. I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive inputA.
KBI4 — Keyboard input4.
AD13 — A/D channel 1, input3.
DAC1 — Digital to analog converter 1 output. I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input5.
CLKIN — External clock input.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 coreP1.0 to P1.5 I/O
(P1.2); (P1.5)
Port1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port1
latches are configured in the input only mode with the internal pull-up disabled. The
operationof the P1.2 input and outputs depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details. P1.2 is an open drain when used as an output. P1.5 is
input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: I/O
P1.0 — Port 1 bit0
TxD — Serial port transmitter data. I/O
P1.1 — Port 1 bit0
RxD — Serial port receiver data. I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow output, or PWM output.
I/O
SCL —I 2C-bus serial clock input/output. I/O
P1.3 — Port 1 bit 2. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA —I 2C-bus serial data input/output.
P1.5 — Port 1 bit 5. (Input only.)
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0.
When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.Also used during a power-on sequence to force In-System Programming mode.
Table 4: P89LPC916 pin description…continued
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 coreP2.2 to P2.5 I/O
Port2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset
Port1 latches are configuredin the input only mode with the internal pull-up disabled.
The operation of the P2 input and outputs depends upon the port configuration
selected. Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below: I/O
P2.2 — Port 2 bit2.
MOSI — SPI master out slave in. When configured as a master this pin is an output.
When configured as a slave, this pin is an input. I/O
P2.3 — Port 2 bit3.
MISO — SPI master in slave out. When configured as a master this pin is an input.
When configured as a slave, this pin is an output. I/O
P2.4 — Port 2 bit4.
I/O
SS — SPI Slave select. I/O
P2.5 — Port 2 bit5.
I/O
SPICLK — When configured as a master this pin is an output. When configured as a
slave, this pin is an input.
VSS 4I
Ground: 0 V reference.
VDD 12 I
Power Supply: This is the power supply voltage for normal operation as well as Idleand Power-down modes.
Table 4: P89LPC916 pin description…continued
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 5: P89LPC917 pin description P0.0 to P0.5 I/O
Port0: Port 0 is a 7-bit I/O port with user-configurable outputs. During reset Port0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 9.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below: I/O
P0.0 — Port 0 bit0.
CMP2 — Comparator 2 output.
KBI0 — Keyboard input0. I/O
P0.1 — Port 0 bit1.
CIN2B — Comparator 2 positive inputB.
KBI1 — Keyboard input1.
AD10 — A/D channel 1, input 0 I/O
P0.2 — Port 0 bit2.
CIN2A — Comparator 2 positive inputA.
KBI2 — Keyboard input2.
AD11 — A/D channel 1, input 1 I/O
P0.3 — Port 0 bit3.
CIN1B — Comparator 1 positive inputB.
KBI3 — Keyboard input3.
AD12 — A/D channel 1, input 2. I/O
P0.4 — Port 0 bit4.
CIN1A — Comparator 1 positive inputA.
KBI4 — Keyboard input4.
AD13 — A/D channel 1, input3.
DAC1 — Digital to analog converter 1 output. I/O
P0.5 — Port 0 bit5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input5.
CLKIN — External clock input. I/O
P0.7 — Port 0 bit7.
T1 — Timer/counter 1 external count input, overflow output, or PWM output.
KBI7 — Keyboard input7.
CLKOUT — Clock output.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 coreP1.0 to P1.5 I/O
(P1.2); (P1.5)
Port1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the outputs depends upon the port configuration selected. Refer to
Section 9.12.1 “Port configurations” and Table 13 “DC electrical characteristics” for
details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below: I/O
P1.0 — Port 1 bit0.
TxD — Serial port transmitter data. I/O
P1.1 — Port 1 bit1.
RxD — Serial port receiver data. I/O
P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O
T0 — Timer/counter 0 external count input, overflow, or PWM output.
I/O
SCL —I2 C-bus serial clock input/output. I/O
P1.3 — Port 1 bit 3. (Open drain when used as an output.)
I/O
INT0 — External interrupt 0 input.
I/O
SDA —I2 C-bus serial data input/output. I/O
P1.4 — Port 1 bit4.
I/O
INT1 — External interrupt 1input.
P1.5 — Port 1 bit 5. (Input only.)
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0.
When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specified level.
When system power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.Also used during a power-on sequence to force In-System Programming mode.
P2.2 5 I/O
Port2: Port 2.2 is a single-bit I/O port with a user-configurable output. During reset
the Port 2.2 latch is configured in the input only mode with the internal pull-up
disabled. The operation of the output depends upon the port configuration selected.
Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details.
This pin has a Schmitt triggered input.
VSS 4I
Ground: 0 V reference.
VDD 12 I
Power Supply: This is the power supply voltage for normal operation as well as Idleand Power-down modes.
Table 5: P89LPC917 pin description…continued
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Logic symbols
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
7.1 Product comparisonTable6 highlights the differences between these three devices. Fora complete listof
device features, please see Section 2 “Features” on page 1.
Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
User must
not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can
only be written and read as follows:‘-’ Unless otherwise specified,
mustbe written with ‘0’, but can return any value
when read (evenifit was written with ‘0’).Itisa reservedbit and maybe usedin
future derivatives.
‘0’
must be written with ‘0’, and will return a ‘0’ when read.‘1’
must be written with ‘1’, and will return a ‘1’ when read.
Table 6: Product comparisonP89LPC915 X - - - X 6
P89LPC916 - X - - - 5
P89LPC917 X - X X X 7
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915 Special function registerxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 corets are in input only (high impedance) state after po
er-up
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
er-up reset, all reset source flags are clear
ed e
xcept POF and BOF; the po
er-on reset
reset,
the
alue
111001x1,
i.e
PRE[2:0]
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
after
er-on
reset.
Other
ect WDT
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
ects these SFRs is po
er-on reset
P89LPC915 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC916 Special function registerxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC916 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC916 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 corets are in input only (high impedance) state after po
er-up
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
er-up reset, all reset source flags are clear
ed e
xcept POF and BOF; the po
er-on reset
reset,
the
alue
111001x1,
i.e
PRE[2:0]
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
after
er-on
reset.
Other
ect WDT
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
ects these SFRs is po
er-on reset.
P89LPC916 Special function register…contin
ued
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Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC917 Special function registerxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC917 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC917 Special function register…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 corets are in input only (high impedance) state after po
er-up
ust only be wr
itten if BRGEN in BRGCON SFR is logic
0. If an
y are wr
itten while BRGEN
1, the result is unpre
dictab
er-up reset, all reset source flags are clear
ed e
xcept POF and BOF; the po
er-on reset
reset,
the
alue
111001x1,
i.e
PRE[2:0]
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
after
er-on
reset.
Other
ect WDT
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
ects these SFRs is po
er-on reset.
P89LPC917 Special function register…contin
ued
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core Functional description
Remark: Please refer to the P89LPC915/916/917 User’s Manual for a more detailed
functional description.
9.1 Enhanced CPUThe P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at 6 times the
speedof standard 80C51 devices.A machine cycle consistsof two CPU clock cycles,
and most instructions execute in one or two machine cycles.
9.2 Clocks
9.2.1 Clock definitionsThe P89LPC915/916/917 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of three
clock sources (see Figure 10) and can also be optionally divided to a slower
frequency (see Section 9.7 “CPU Clock (CCLK) modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executedin oneto two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
9.2.2 CPU clock (OSCCLK)The P89LPC915/916/917 provide user-selectable oscillator optionsin generating the
CPU clock. This allows optimizationfora rangeof needs from high precisionto lowest
possible cost. These options are configured when the FLASH is programmed and
include an on-chip Watchdog oscillator, an on-chip RC oscillator, and an external
clock input.
9.2.3 Clock output (P89LPC917)The P89LPC917 supports a user selectable clock output function on the CLKOUT
pin. This allows external devices to synchronize to the P89LPC917. This output is
enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is ⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned
off prior to entering Idle, saving additional power.
9.3 On-chip RC oscillator optionThe P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed valueto adjust the oscillator frequencyto 7.373 MHz,±1%at room
temperature. End-user applications can write to the TRIM register to adjust the
on-chip RC oscillator to other frequencies.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
9.4 Watchdog oscillator optionThe Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
9.5 External clock input optionIn this configuration, the processor clock is derived from an external source driving
the CLKIN pin. The rate maybe from0 Hzupto18 MHz.
When usingan oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuitis requiredto hold the devicein resetat power-up until VDD has
reached its specified level. When system power is removed VDD will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum
specified operating voltage.
9.6 CPU Clock (CCLK) wake-up delayThe P89LPC915/916/917 has an internal wake-up timer that delays the clock until it
stabilizes. The delay is 224 OSCCLK cycles plus 60to 100 μs.
9.7 CPU Clock (CCLK) modification: DIVM registerThe OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPUata lower rate, reducing power consumption.By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 corethe oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
9.8 Low power selectThe P89LPC915/916/917 are designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to
logic 1 to lower the power consumption further. On any reset, CLKLP is logic0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
9.9 A/D converter
9.9.1 General descriptionThe P89LPC915/916/917 has an 8-bit, 4-channel multiplexed successive
approximation analog-to-digital converter. A block diagram of the A/D converter is
shown in Figure 11. The A/D consists of a 4-input multiplexer which feeds a
sample-and-hold circuit providing an input signal to one of two comparator inputs.
The control logic in combination with the successive approximation register (SAR)
drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
9.9.2 Features An 8-bit, 4-channel multiplexed input, successive approximation A/D converter
Four A/D result registers
Six operating modes
Fixed channel, single conversion mode
Fixed channel, continuous conversion mode
Auto scan, single conversion mode
Auto scan, continuous conversion mode
Dual channel, continuous conversion mode
Single step mode
Three conversion start modes
Timer triggered start
Start immediately
Edge triggered
8-bit conversion time of ≥3.9 μs at an ADC clock of 3.3 MHz
Interrupt or polled operation
Boundary limits interrupt
DAC output to a port pin with high output impedance
Clock divider
Power-down mode
9.9.3 A/D operating modes
Fixed channel, single conversion mode:A single input channel canbe selectedfor
conversion. A single conversion will be performed and the result placed in the result
register which correspondsto the selected input channel. An interrupt,if enabled, will
be generated after the conversion completes.
Fixed channel, continuous conversion mode: A single input channel can be
selectedfor continuous conversion. The resultsof the conversions willbe sequentially
placed in the four result registers. An interrupt, if enabled, will be generated after
every four conversions. Additional conversion results will again cycle through the four
result registers, overwriting the previous results. Continuous conversions continue
until terminated by the user.
Auto scan, single conversion mode: Any combination of the four input channels
can be selected for conversion. A single conversion of each selected input will be
performed and the result placed in the result register which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after all selected
channels have been converted. If only a single channel is selected this is equivalent
to single channel, single conversion mode.
Auto scan, continuous conversion mode: Any combination of the four input
channels can be selected for conversion. A conversion of each selected input will be
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 corechannels have been converted. The process will repeat starting with the first selected
channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results. Continous conversions continue until
terminated by the user.
Dual channel, continuous conversion mode: This is a variation of the auto scan
continuous conversion mode where conversion occurson two user-selectable inputs.
The resultof the conversionof the first channelis placedin result register, AD1DAT0.
The result of the conversion of the second channel is placed in result register,
AD1DAT1. The first channelis again converted andits result storedin AD1DAT2. The
second channel is again converted and its result placed in AD1DAT3. An interrupt is
generated, if enabled, after every set of four conversions (two conversions per
channel).
Single step mode: This special mode allows ‘single-stepping’ in an auto scan
conversion mode. Any combination of the four input channels can be selected for
conversion. After each channel is converted, an interrupt is generated, if enabled,
and the A/D waits for the next start condition. May be used with any of the start
modes.
9.9.4 Conversion start modes
Timer triggered start: An A/D conversionis startedby the overflowof Timer0. Once
a conversion has started, additional Timer 0 triggers are ignored until the conversion
has completed. The Timer triggered start mode is available in all A/D operating
modes.
Start immediately: Programming this mode immediately starts a conversion. This
start mode is available in all A/D operating modes.
Edge triggered: (P89LPC915/917) An A/D conversion is started by rising or falling
edge of P1.4. Once a conversion has started, additional edge triggers are ignored
until the conversion has completed. The edge triggered start mode is available in all
A/D operating modes.
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
9.9.5 Boundary limits interruptThe A/D converters have both a high and low boundary limit register. After the four
MSBs have been converted, these four bits are compared with the four MSBs of the
boundary high and low registers. If the four MSBs of the conversion are outside the
limit an interrupt will be generated, if enabled. If the conversion result is within the
limits, the boundary limits will againbe compared afterall8 bits have been converted.
An interrupt will be generated, if enabled, if the result is outside the boundary limits.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
9.9.6 DAC output to a port pin with high output impedanceThe A/D converter’s DAC block can be output to a port pin. In this mode, the
AD1DAT3 register is used to hold the value fed to the DAC. After a value has been
written to AD1DAT3, the DAC output will appear on the channel 3 pin.
9.9.7 Clock dividerThe A/D converter requires thatits internal clock sourcebein the rangeof 500 kHzto
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from1to 8 is provided for this purpose.
9.9.8 Power-down and Idle mode Idle mode the A/D converter,if enabled, will continueto function and can cause the
device to exit Idle mode when the conversion is completed if the A/D interrupt is
enabled.In Power-down modeor Total power-down mode, the A/D does not function.
If the A/D is enabled, it will consume power. Power can be reduced by disabling the
A/D.
9.10 Memory organizationThe various P89LPC915/916/917 memory spaces are as follows:
DATA
256 bytesof internal data memory space (00h:FFh) accessed via director indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.
SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
CODE kBof Code memory space, accessedas partof program execution and via the
MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.
9.11 InterruptsThe P89LPC915/916/917 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.
The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0
and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx and Tx,
Philips Semiconductors P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 coreThe P89LPC916supports 14 interrupt sources: external interrupt 0, timers 0 and 1,
serial port Tx, serial port Rx, combined serial port Rx and Tx, brownout detect,
Watchdog/Real-Time clock, I2C, keyboard, comparators 1 and 2, SPI, and the A/D
converter.
Each interrupt source canbe individually enabledor disabledby settingor clearinga
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source canbe individually programmedto oneof four priority levelsby
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but notby another interruptof the sameor lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pendingat the startofan instruction, the requestof higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
9.11.1 External interrupt inputsThe P89LPC915 and P89LPC917 have two external interrupt inputs as well as the
Keypad Interrupt function. The P89LPC916 has one external interrupt inputas wellas
the Keypad Interrupt function These external interrupt inputs are identical to those
present on the standard 80C51 microcontrollers.
These external interrupts canbe programmedtobe level-triggeredor edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC915/916/917 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and
resume operation. Refer to Section 9.14 “Power reduction modes” for details.
