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P89LPC912FDH ,P89LPC912/913/914; 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAMfeaturesn 14-pin TSSOP packages.n A high performance 80C51 CPU provides instruction cycle times of ..
P89LPC915FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterP89LPC915/916/9178-bit microcontrollers with accelerated two-clock 80C51 core2 kB 3 V Flash with 8- ..
P89LPC915FN ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterP89LPC915/916/9178-bit microcontrollers with accelerated two-clock 80C51 core2 kB 3 V ﬂash with 8-b ..
P89LPC916FDH ,P89LPC915/916/917; 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V Flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and16- ..
P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and16- ..
P89LPC917FDH ,8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converterGeneral descriptionThe P89LPC915/916/917 are single-chip microcontrollers, available in low-cost pa ..
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P89LPC912FDH
8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM
General descriptionThe P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC912/913/914 in order to reduce component
count, board space, and system cost. Features
2.1 Principal features 1 kB byte-erasable ﬂash code memory organized into 256 B sectors and 16 B pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 128 B RAM data memory. Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output upon
timer overﬂow or to become a PWM output. 23-bit system timer that can also be used as a RTC. Two analog comparators with selectable inputs and reference source. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC913, P89LPC914). SPI communication port. Internal RC oscillator (factory calibrated to±1 %) option allows operation without
external oscillator components. The RC oscillator optionis selectable and ﬁne tunable. 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V). Up to 12 I/O pins when using internal oscillator and reset options.
2.2 Additional features 14-pin TSSOP packages. A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222ns
for all instructions except multiply and divide when executing at 18 MHz (167 ns to
333nsat12 MHz). Thisis six times the performanceof the standard 80C51 runningat
the same clock frequency.A lower clock frequencyfor the same performance resultsin
power savings and reduced EMI. In-Application Programming (IAP-Lite) and byte erase allows code memorytobe used
for non-volatile data storage.
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V
ﬂash with 128-byte RAM
Rev. 05 — 28 September 2007 Product data sheet
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs. Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values. Low voltage reset (brownout detect) allows a graceful system shutdown when power
fails. May optionally be conﬁgured as an interrupt. Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available. Conﬁgurable on-chip oscillator with frequency range options selected by user
programmed ﬂash conﬁguration bits. Oscillator options support frequencies from kHz to the maximum operating frequency of 18 MHz (P89LPC912, P89LPC913). Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Programmable port output conﬁguration options: quasi-bidirectional, open-drain,
push-pull, input-only. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern. LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the
entire chip. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns
minimum ramp times. Only power and ground connections are required to operate the P89LPC912/913/914
when internal reset option is selected. Four interrupt priority levels. Four keypad interrupt inputs. Second data pointer. Schmitt trigger port inputs. Emulation support.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Product comparison
Table 1 highlights the differences between these three devices. For a complete list of
device features, please see Section 2 “Features” on page 1. Ordering information
4.1 Ordering options
Table 1. Product comparison
P89LPC912 X X X X - - - 18
P89LPC913 X X - - X X X 18
P89LPC914 - - X X - X X 12
Table 2. Ordering information
P89LPC912FDH TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
P89LPC912HDH
P89LPC913FDH
P89LPC914FDH
Table 3. Ordering options
P89LPC912FDH −40°Cto +85°C 0 MHzto18 MHz
P89LPC912HDH −40°Cto +125°C 0 MHzto18 MHz
P89LPC913FDH −40°Cto +85°C 0 MHzto18 MHz
P89LPC914FDH −40°Cto +85°C 0 MHz to 12 MHz
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Block diagram
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Functional diagram
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Pinning information
7.1 Pinning
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
7.2 Pin description
Table 4. P89LPC912 pin description
P0.2, P0.4 to
P0.6
I/O Port0: Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset
Port 0 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port0 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.2/CIN2A/
KBI2 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive inputA. KBI2 — Keyboard input2.
P0.4/CIN1A/
KBI4 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive inputA. KBI4 — Keyboard input4.
P0.5/CMPREF/
KBI5 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5.
P0.6/CMP1/
KBI6 I/O P0.6 — Port 0 bit6. CMP1 — Comparator 1 output. KBI6 — Keyboard input6.
P1.2, P1.5 I/O
(P1.2); (P1.5)
Port1: Port1isa 2-bit I/O port with P1.2 havinga user-conﬁgurable output typeas
noted below. During reset Port1 latches are conﬁguredin the input only mode with
the internal pull-up disabled. The operation of the P1.2 input and outputs depends
upon the port conﬁguration selected. Refer to Section 8.12.1 “Port conﬁgurations”
and Table13 “Static characteristics”for details. P1.2isan open drain when usedas
an output. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.2/T0 6 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O T0 — Timer/counter 0 external count input or overﬂow output. (Open drain when
used as outputs.).
P1.5/RST 3 I P1.5 — Port 1 bit 5. (Input only.) RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When usingan oscillator frequency above12 MHz, the reset input functionof
P1.5 must be enabled. An external circuit is required to hold the device in
reset at power-up until VDD has reached its speciﬁed level. When system
power is removed VDD will fall below the minimum speciﬁed operating
voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum speciﬁed operating
voltage.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P2.2 to P2.5 I/O Port2: Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset
Port 2 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port2 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 1 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,
when conﬁgured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit3.
I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input,
when conﬁgured as slave, this pin is output.
P2.4/SS 9 I/O P2.4 — Port 2 bit4. SS — SPI Slave select.
P2.5/SPICLK 2 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when
conﬁgured as slave, this pin is input.
P3.0 to P3.1 I/O Port3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset
Port 3 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port3 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT I/O P3.0 — Port 3 bit0. XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is
selected via the ﬂash conﬁguration). CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the Real-Time clock/system timer.
P3.1/XTAL1 7 I/O P3.1 — Port 3 bit1. XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the Real-Time clock/system timer.
VSS 4I Ground: 0 V reference.
VDD 10 I Power Supply: Thisis the power supply voltagefor normal operationas wellas Idle
and Power-down modes.
Table 4. P89LPC912 pin description …continued
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 5. P89LPC913 pin description
P0.2,
P0.4to P0.6
I/O Port0: Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset
Port 0 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port0 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.2/CIN2A/
KBI2 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive inputA. KBI2 — Keyboard input 2.
P0.4/CIN1A/
KBI4 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive inputA. KBI4 — Keyboard input 4.
P0.5/CMPREF/
KBI5 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input 5.
P0.6/CMP1/
KBI6 I/O P0.6 — Port 0 bit6. CMP1 — Comparator 1 output. KBI6 — Keyboard input 6.
P1.0, P1.1,
P1.5
I/O
(P1.0,
P1.1); (P1.5)
Port1: Port1isa 3-bit I/O port witha user-conﬁgurable output type, exceptfor P1.5
noted below. During reset Port1 latches are conﬁguredin the input only mode with
the internal pull-up disabled. The operationof the conﬁgurable Port1 pinsas inputs
and outputs depends upon the port conﬁguration selected. Eachofthe conﬁgurable
port pins are programmed independently. Refer to Section 8.12.1 “Port
conﬁgurations” and Table 13 “Static characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 9 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for the serial port.
P1.1/RXD 6 I/O P1.1 — Port 1 bit1. RXD — Receiver input for the serial port.
P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only). RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When usingan oscillator frequency above12 MHz, the reset input functionof
P1.5 must be enabled. An external circuit is required to hold the device in
reset at power-up until VDD has reached its speciﬁed level. When system
power is removed VDD will fall below the minimum speciﬁed operating
voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum speciﬁed operating
voltage.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P2.2, P2.3,
P2.5
I/O Port 2: Port 2 is a 3-bit I/O port with a user-conﬁgurable output type. During reset
Port 2 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port2 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 1 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,
when conﬁgured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit3.
I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input,
when conﬁgured as slave, this pin is output.
P2.5/SPICLK 2 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when
conﬁgured as slave, this pin is input.
P3.0 to P3.1 I/O Port3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset
Port 3 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port3 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT I/O P3.0 — Port 3 bit0. XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is
selected via the ﬂash conﬁguration). CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the Real-Time clock/system timer.
P3.1/XTAL1 7 I/O P3.1 — Port 3 bit1. XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the Real-Time clock/system timer.
VSS 4I Ground: 0 V reference.
VDD 10 I Power Supply: Thisis the power supply voltagefor normal operationas wellas Idle
and Power-down modes.
Table 5. P89LPC913 pin description …continued
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 6. P89LPC914 pin description
P0.2,
P0.4to P0.6
I/O Port0: Port 0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset
Port 0 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port0 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.2/CIN2A/
KBI2 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive inputA. KBI2 — Keyboard input 2.
P0.4/CIN1A/
KBI4 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive inputA. KBI4 — Keyboard input 4.
P0.5/CMPREF
/ KBI5 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input 5.
P0.6/CMP1/
KBI6 I/O P0.6 — Port 0 bit6. CMP1 — Comparator 1 output. KBI6 — Keyboard input 6.
P1.0to P1.2,
P1.5
I/O
(P1.0to
P1.2); (P1.5)
Port 1: Port 1 is a 4-bit I/O port with a user-conﬁgurable output type, except for
three pins noted below. During reset Port 1 latches are conﬁgured in the input only
mode with the internal pull-up disabled. The operation of the conﬁgurable Port1
pins as inputs and outputs depends upon the port conﬁguration selected. Each of
the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1
“Port conﬁgurations” and Table 13 “Static characteristics” for details. P1.2 is an
open drain when used as an output. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 9 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for the serial port.
P1.1/RXD 6 I/O P1.1 — Port 1 bit1. RXD — Receiver input for the serial port.
P1.2/T0 7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O T0 — Timer/counter 0 external count input or overﬂow output. (Open drain when
used as outputs.)
P1.5/RST 3 I P1.5 — Port 1 bit 5 (input only). RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P2.2 to P2.5 I/O Port 2: Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset
Port 2 latches are conﬁgured in the input only mode with the internal pull-up
disabled. The operationof Port2 pinsas inputs and outputs depends upon the port
conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section
8.12.1 “Port conﬁgurations” andT able 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 1 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,
when conﬁgured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit3.
I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input,
when conﬁgured as slave, this pin is output.
P2.4/SS 8 I/O P2.4 — Port 2 bit 4. SS — SPI Slave select.
P2.5/SPICLK 2 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when
conﬁgured as slave, this pin is input.
VSS 4I Ground: 0 V reference.
VDD 10 I Power Supply: This is the power supply voltage for normal operation as well as
Idle and Power-down modes.
Table 6. P89LPC914 pin description …continued
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core Functional description
Remark: Please refer to the P89LPC912/913/914 User manual for a more detailed
functional description.
8.1 Special function registers
Remark: SFR accesses are restricted in the following ways: User must not attempt to access any SFR locations not deﬁned. Accessesto any deﬁned SFR locations mustbe strictlyfor the functionsfor the SFRs. SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows: ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives. ‘0’ must be written with ‘0’, and will return a ‘0’ when read. ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
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NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 7.
P89LPC912 Special function register
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NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 7.
P89LPC912 Special function register
…contin
ued
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NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
All por
ts are in input only (high impedance) state after po
er-up
The RSTSRC register reﬂects the cause of the P89LPC912 reset. Upon a po
er-up reset, all reset source ﬂags are cleared e
xcep
t POF and BOF; the po
er-on reset v
alue is
xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 7.
P89LPC912 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 8.
P89LPC913 Special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 8.
P89LPC913 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 8.
P89LPC913 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
All por
ts are in input only (high impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is logic 0. If an
y of them is wr
itten if BRGEN
1, result is unpr
edictab
The RSTSRC register reﬂects the cause of the P89LPC912 reset. Upon a po
er-up reset, all reset source ﬂags are cleared e
xcep
t POF and BOF; the po
er-on reset v
alue is
xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 8.
P89LPC913 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 9.
P89LPC914 Special function register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 9.
P89LPC914 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
le 9.
P89LPC914 Special function register
…contin
ued
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
All por
ts are in input only (high impedance) state after po
er-up
BRGR1 and BRGR0 m
ust only be wr
itten if BRGEN in BRGCON SFR is logic 0. If an
y of them is wr
itten if BRGEN
1, result is unpr
edictab
The RSTSRC register reﬂects the cause of the P89LPC912 reset. Upon a po
er-up reset, all reset source ﬂags are cleared e
xcep
t POF and BOF; the po
er-on reset v
alue is
xx11
After
reset,
the
alue
01x1,
i.e
PRE2
PRE0
are
all
logic
WDR
and
WDCLK
WDT
bit
logic
after
atchdog
reset
and
logic
aft
er-on
reset.
Other resets will not aff
ect WDT
On po
er-on reset, the TRIM SFR is initializ
ed with a f
actor
y preprog
rammed v
alue
. Other resets will not cause initializatio
n of the TRIM register
The only reset source that aff
ects these SFRs is po
er-on reset.
le 9.
P89LPC914 Special function register
…contin
ued
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.2 Enhanced CPU
The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at six times the
speedof standard 80C51 devices.A machine cycle consistsof two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock deﬁnitions
The P89LPC912/913/914 device has several internal clocks as deﬁned below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 10, 11, and 12) and can also be optionally divided to a slower
frequency (see Section 8.8 “CCLK modiﬁcation: DIVM register”).
Note: fosc is deﬁned as the OSCCLK frequency.
CCLK — CPU clock; outputof the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executedin oneto two machine cycles (twoor four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.3.2 CPU clock (OSCCLK)
The P89LPC912/913/914 provide user-selectable oscillator optionsin generating the CPU
clock. This allows optimizationfora rangeof needs from high precisionto lowest possible
cost. These options are conﬁgured when the ﬂashis programmed and includean on-chip
watchdog oscillator and an on-chip RC oscillator.
In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an external
crystal or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
8.3.3 Low-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this conﬁguration.
8.3.4 Medium-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this conﬁguration.
8.3.5 High-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supportedin this conﬁguration. When usingan oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
speciﬁed level. When system power is removed VDD will fall below the minimum
speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum speciﬁed operating voltage.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.3.6 Clock output (P89LPC912, P89LPC913)
The P89LPC912 supportsa user selectable clock output functionon the XTAL2/CLKOUT
pin when crystal oscillatoris not being used. This condition occursif another clock source
has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1)
andif the Real-Time clockis not using the crystal oscillatorasits clock source. This allows
external devicesto synchronizeto the P89LPC912. This outputis enabledby the ENCLK
bit in the TRIM register. The frequency of this clock output is1 ⁄2 that of the CCLK. If the
clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving
additional power.
8.4 On-chip RC oscillator option
The P89LPC912/913/914 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
preprogrammed value to adjust the oscillator frequency to 7.373 MHz, ± 1 % at room
temperature. End-user applications can write to the TRIM register to adjust the on-chip
RC oscillator to other frequencies.
8.5 Watchdog oscillator option
The watchdog hasa separate oscillator which hasa frequencyof 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
8.6 External clock input option (P89LPC912, P89LPC913)
In this conﬁguration, the processor clock is derived from an external source driving the
XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
speciﬁed level. When system power is removed, VDD will fall below the minimum
speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum speciﬁed operating voltage.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.7 CCLK wake-up delay
The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (P89LPC912, P89LPC913) the delayis 992 OSCCLK cycles plus60μs
to 100 μs. If the clock source is either the internal RC oscillator, watchdog oscillator, or
external clock, the delay is 224 OSCCLK cycles plus 60 μsto100 μs.
8.8 CCLK modiﬁcation: DIVM register
The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the abilityto respondto events that would not exit Idle modeby executingits normal
programata lower rate. This can also allow bypassing the oscillator start-up timein cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
8.9 Low power select
The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.
However,if CCLKis8 MHzor slower, the CLKLP SFRbit (AUXR1.7) canbe setto logic1
to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
8.10 Memory organization
The various P89LPC912/913/914 memory spaces are as follows:
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing. CODE kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.
8.11 Interrupts
The P89LPC912/913/914 uses a four priority level interrupt structure. This allows great
ﬂexibility in controlling the handling of the many interrupt sources.
The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.
The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and 1,
serial port TX, serial port RX, combined serial port RX/TX, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.
Each interrupt source canbe individually enabledor disabledby settingor clearingabitin
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
notby another interruptof the sameor lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
8.11.1 External interrupt inputs
The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the
interrupt will cause the processorto wake-up and resume operation. Referto Section 8.14
“Power reduction modes” for details.
NXP Semiconductors P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.12 I/O ports
The P89LPC912 and P89LPC913 devices have 4 I/O ports: Port 0, Port 1, Port 2 and
Port 3. The exact number of I/O pins available depends on the clock and reset options
chosen, as shown in Table 10.

Partno	Mfg	Dc	Qty	Available	Descript
P89LPC912FDH	NXP	N/a	250	avai	P89LPC912/913/914; 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM