P87LPC768BD ,Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D,and Pulse Width ModulatorELECTRICAL CHARACTERISTICS . . . . 57i2001 Aug 06Philips Semiconductors Preliminary dataLow ..
P87LPC768BN ,Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D,and Pulse Width ModulatorFUNCTIONAL DESCRIPTION . . . . . 9Enhanced CPU 9Analog Functions . . ..
P87LPC769HD ,Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D, and DACINTEGRATED CIRCUITS87LPC769Low power, low price, low pin count(20 pin) microcontroller with 4 kB OT ..
P87LPC769HD ,Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D, and DACFUNCTIONAL DESCRIPTION . . . . . 9Enhanced CPU 9Analog Functions . . ..
P87LPC778FDH ,P87LPC778; CMOS single-chip 8-bit 80C51 microcontroller with 128-byte data RAM, 8 kB OTP
P87LPC778FDH ,P87LPC778; CMOS single-chip 8-bit 80C51 microcontroller with 128-byte data RAM, 8 kB OTP
PCA9554APWR ,Remote 8-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers 16-TSSOP -40 to 85Maximum Ratingsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
PCA9554APWRG4 ,Remote 8-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers 16-TSSOP -40 to 85Features 2 Description2This 8-bit I/O expander for the two-line bidirectional1• I C to Parallel Por ..
PCA9554ARGTR ,Remote 8-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers 16-QFN -40 to 85Features... 1 8 Detailed Description........ 138.1 Functional
PCA9554ARGVR ,Remote 8-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers 16-VQFN -40 to 856 Specifications(1)6.1 Absolute
PCA9554BS ,8-bit I2C and SMBus I/O port with interruptPIN CONFIGURATION — 20-pin SSOPINT 1 20 I/O7SCL 2 19 I/O6n.c. 3 18 n.c.SDA 4 17 I/O5V 5 16 I/O4DDA0 ..
PCA9554D ,8-bit I虏C-bus and SMBus I/O port with interruptPIN CONFIGURATION — 20-pin SSOPINT 1 20 I/O7SCL 2 19 I/O6n.c. 3 18 n.c.SDA 4 17 I/O5V 5 16 I/O4DDA0 ..
P87LPC768BD-P87LPC768BN
Low power, low price, low pin count 20 pin microcontroller with 4 kB OTP 8-bit A/D,and Pulse Width Modulator
Preliminary data
Supersedes data of 2000 May 02
2001 Aug 06
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING INFORMATION 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATION, 20-PIN DIP AND SO PACKAGES 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LOGIC SYMBOL 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTIONS 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL DESCRIPTION 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced CPU 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Functions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converter 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Timing 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The A/D in Power Down and Idle Modes 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Examples for the A/D 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Comparators 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Serial Interface 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Ports 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt (KBI) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Monitoring Functions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Reduction Modes 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counters 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Features 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC ELECTRICAL CHARACTERISTICS 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMPARATOR ELECTRICAL CHARACTERISTICS 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D CONVERTER DC ELECTRICAL CHARACTERISTICS 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC ELECTRICAL CHARACTERISTICS 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
GENERAL DESCRIPTIONThe 87LPC768 is a 20-pin single-chip microcontroller designed for
low pin count applications demanding high-integration, low cost
solutions over a wide range of performance requirements. A
member of the Philips low pin count family, the 87LPC768 offers
programmable oscillator configurations for high and low speed
crystals or RC operation, wide operating voltage range,
programmable port output configurations, selectable Schmitt trigger
inputs, LED drive outputs, and a built-in watchdog timer. The
87LPC768 is based on an accelerated 80C51 processor
architecture that executes instructions at twice the rate of standard
80C51 devices.
FEATURES An accelerated 80C51 CPU provides instruction cycle times of
300–600 ns for all instructions except multiply and divide when
executing at 20 MHz. Execution at up to 20 MHz when
VDD = 4.5 V to 6.0 V, 10 MHz when VDD = 2.7 V to 6.0 V. Four-channel 10-bit Pulse Width Modulator Four-channel multiplexed 8-bit A/D converter. Conversion time of
9.3μS at fosc = 20 MHz. 2.7 V to 6.0 V operating range for digital functions. 4 kbytes EPROM code memory. 128 byte RAM data memory. 32-byte customer code EPROM allows serialization of devices,
storage of setup parameters, etc. Two 16-bit counter/timers. Each timer may be configured to toggle
a port output upon timer overflow. Two analog comparators. Full duplex UART.I2 C communication port. Eight keypad interrupt inputs, plus two additional external interrupt
inputs. Four interrupt priority levels. Watchdog timer with separate on-chip oscillator, requiring no
external components. The watchdog timeout time is selectable
from 8 values. Active low reset. On-chip power-on reset allows operation with no
external reset components. Low voltage reset. One of two preset low voltage levels may be
selected to allow a graceful system shutdown when power fails.
May optionally be configured as an interrupt. Oscillator Fail Detect. The watchdog timer has a separate fully
on-chip oscillator, allowing it to perform an oscillator fail detect
function. Configurable on-chip oscillator with frequency range and RC
oscillator options (selected by user programmed EPROM bits).
The RC oscillator option allows operation with no external
oscillator components. Programmable port output configuration options:
quasi-bidirectional, open drain, push-pull, input-only. Selectable Schmitt trigger port inputs. LED drive capability (20 mA) on all port pins. Controlled slew rate port outputs to reduce EMI. Outputs have
approximately 10 ns minimum ramp times. 15 I/O pins minimum. Up to 18 I/O pins using on-chip oscillator
and reset options. Only power and ground connections are required to operate the
87LPC768 when fully on-chip oscillator and reset options are
selected. Serial EPROM programming allows simple in-circuit production
coding. Two EPROM security bits prevent reading of sensitive
application programs. Idle and Power Down reduced power modes. Improved wakeup
from Power Down mode (a low interrupt input starts execution).
Typical Power Down current is 1 μA. 20-pin DIP and SO packages.
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
ORDERING INFORMATION
PIN CONFIGURATION, 20-PIN DIP AND SO PACKAGES
LOGIC SYMBOL
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
BLOCK DIAGRAM
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Figure 1. 87LPC768 Program and Data Memory Map
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
PIN DESCRIPTIONS
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Table 1. Special Function Registers
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
NOTES:* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
FUNCTIONAL DESCRIPTIONDetails of 87LPC768 functions will be described in the following
sections.
Enhanced CPUThe 87LPC768 uses an enhanced 80C51 CPU which runs at twice the
speed of standard 80C51 devices. This means that the performance of
the 87LPC768 running at 5 MHz is exactly the same as that of a
standard 80C51 running at 10 MHz. A machine cycle consists of 6
oscillator cycles, and most instructions execute in 6 or 12 clocks. A
user configurable option allows restoring standard 80C51 execution
timing. In that case, a machine cycle becomes 12 oscillator cycles.
In the following sections, the term “CPU clock” is used to refer to the
clock that controls internal instruction execution. This may
sometimes be different from the externally applied clock, as in the
case where the part is configured for standard 80C51 timing by
means of the CLKR configuration bit or in the case where the clock
is divided down via the setting of the DIVM register. These features
are described in the Oscillator section.
Analog FunctionsThe 87LPC768 incorporates analog peripheral functions: an Analog
to Digital Converter and two Analog Comparators. In order to give
the best analog function performance and to minimize power
consumption, pins that are being used for analog functions must
have the digital outputs and inputs disabled.
Digital outputs are disabled by putting the port output into the Input
Only (high impedance) mode as described in the I/O Ports section.
Digital inputs on port 0 may be disabled through the use of the
PT0AD register. Each bit in this register corresponds to one pin of
Port 0. Setting the corresponding bit in PT0AD disables that pin’s
digital input. Port bits that have their digital inputs disabled will be
read as 0 by any instruction that accesses the port.
Analog to Digital ConverterThe 87LPC768 incorporates a four channel, 8-bit A/D converter. The
A/D inputs are alternate functions on four port 0 pins. Because the
device has a very limited number of pins, the A/D power supply and
references are shared with the processor power pins, VDD and VSS.
The A/D converter operates down to a VDD supply of 3.0V.
The A/D converter circuitry consists of a 4-input analog multiplexer
and an 8-bit successive approximation ADC. The A/D employs a
ratiometric potentiometer which guarantees DAC monotonicity.
The A/D converter is controlled by the special function register
ADCON. Details of ADCON are shown in Figure 2. The A/D must be
enabled by setting the ENADC bit at least 10 microseconds before a
conversion is started, to allow time for the A/D to stabilize. Prior to
the beginning of an A/D conversion, one analog input pin must be
selected for conversion via the AADR1 and AADR0 bits. These bits
cannot be changed while the A/D is performing a conversion.
An A/D conversion is started by setting the ADCS bit, which remains
set while the conversion is in progress. When the conversion is
complete, the ADCS bit is cleared and the ADCI bit is set. When
ADCI is set, it will generate an interrupt if the interrupt system is
enabled, the A/D interrupt is enabled (via the EAD bit in the IE1
register), and the A/D interrupt is the highest priority pending
interrupt.
When a conversion is complete, the result is contained in the
register DAC0. This value will not change until another conversion is
started. Before another A/D conversion may be started, the ADCI bit
must be cleared by software. The A/D channel selection may be
changed by the same instruction that sets ADCS to start a new
conversion, but not by the same instruction that clears ADCI.
The connections of the A/D converter are shown in Figure 3.
The ideal A/D result may be calculated as follows:
Result�(VIN–VSS)x 256DD–VSS
(round resulttothe nearest integer)
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Figure 2. A/D Control Register (ADCON)
A/D TimingThe A/D may be clocked in one of two ways. The default is to use
the CPU clock as the A/D clock source. When used in this manner,
the A/D completes a conversion in 31 machine cycles. The A/D may
be operated up to the maximum CPU clock rate of 20 MHz, giving a
conversion time of 9.3 μs. The formula for calculating A/D
conversion time when the CPU clock runs the A/D is: 186 μs / CPU
clock rate (in MHZ). To obtain accurate A/D conversion results, the
CPU clock must be at least 1 MHz.
The A/D may also be clocked by the on-chip RC oscillator, even if
the RC oscillator is not used as the CPU clock. This is accomplished
by setting the RCCLK bit in ADCON. This arrangement has several
advantages. First, the A/D conversion time is faster at lower CPU
with other peripheral functions, in order to obtain the best possible
A/D accuracy. This should not be used if the MCU uses an external
clock source greater than 4 MHz.
When the A/D is operated from the RCCLK while the CPU is running
from another clock source, 3 or 4 machine cycles are used to
synchronize A/D operation. The time can range from a minimum of 3
machine cycles (at the CPU clock rate) + 108 RC clocks to a
maximum of 4 machine cycles (at the CPU clock rate) + 112 RC
clocks.
Example A/D conversion times at various CPU clock rates are
shown in Table 2. In Table 2, maximum times for RCCLK = 1 use an
RC clock frequency of 4.5 MHz (6 MHz - 25%). Minimum times for
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Table 2. Example A/D Conversion TimesNote: Do not clock ADC from the RC oscillator when MCU clock is greater than 4 MHz.
Figure 3. A/D Converter Connections
The A/D in Power Down and Idle ModesWhile using the CPU clock as the A/D clock source, the Idle mode
may be used to conserve power and/or to minimize system noise
during the conversion. CPU operation will resume and Idle mode
terminate automatically when a conversion is complete if the A/D
interrupt is active. In Idle mode, noise from the CPU itself is
eliminated, but noise from the oscillator and any other on-chip
peripherals that are running will remain.
The CPU may be put into Power Down mode when the A/D is
clocked by the on-chip RC oscillator (RCCLK=1). This mode gives
the best possible A/D accuracy by eliminating most on-chip noise
sources.
If the Power Down mode is entered while the A/D is running from the
CPU clock (RCCLK=0), the A/D will abort operation and will not
wake up the CPU. The contents of DAC0 will be invalid when
operation does resume.
When an A/D conversion is started, Power Down or Idle mode must
be activated within two machine cycles in order to have the most
accurate A/D result. These two machine cycles are counted at the
CPU clock rate. When using the A/D with either Power Down or Idle
mode, care must be taken to insure that the CPU is not restarted by
another interrupt until the A/D conversion is complete. The possible
causes of wakeup are different in Power Down and Idle modes.
A/D accuracy is also affected by noise generated elsewhere in the
application, power supply noise, and power supply regulation. Since
the 87LPC768 power pins are also used as the A/D reference and
supply, the power supply has a very direct affect on the accuracy of
A/D readings. Using the A/D without Power Down mode while the
clock is divided through the use of CLKR or DIVM has an adverse
effect on A/D accuracy.
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Code Examples for the A/DThe first piece of sample code shows an example of port configuration for use with the A/D. This example sets up the pins so that all four A/D
channels may be used. Port configuration for analog functions is described in the section Analog Functions.
; Set up port pins for A/D conversion, without affecting other pins.
mov PT0AD,#78h ; Disable digital inputs on A/D input pins.
anl P0M2,#87h ; Disable digital outputs on A/D input pins.
orl P0M1,#78h ; Disable digital outputs on A/D input pins.
Following is an example of using the A/D with interrupts. The routine ADStart begins an A/D conversion using the A/D channel number supplied
in the accumulator. The channel number is not checked for validity. The A/D must previously have been enabled with sufficient time to allow for
stabilization.
The interrupt handler routine reads the conversion value and returns it in memory address ADResult. The interrupt should be enabled prior to
starting the conversion.
; Start A/D conversion.
ADStart:
orl ADCON,A ; Add in the new channel number.
setb ADCS ; Start an A/D conversion. orl PCON,#01h ; The CPU could be put into Idle mode here. orl PCON,#02h ; The CPU could be put into Power Down mode here if RCCLK = 1.
ret
; A/D interrupt handler.
ADInt:
push ACC ; Save accumulator.
mov A,DAC0 ; Get A/D result,
mov ADResult,A ; and save it in memory.
clr ADCI ; Clear the A/D completion flag.
anl ADCON,#0fch ; Clear the A/D channel number.
pop ACC ; Restore accumulator.
reti
Following is an example of using the A/D with polling. An A/D conversion is started using the channel number supplied in the accumulator. The
channel number is not checked for validity. The A/D must previously have been enabled with sufficient time to allow for stabilization. The
conversion result is returned in the accumulator.
ADRead:
orl ADCON,A ; Add in the new channel number.
setb ADCS ; Start A/D conversion.
ADChk:
jnb ADCI,ADChk ; Wait for ADCI to be set.
mov A,DAC0 ; Get A/D result.
clr ADCI ; Clear the A/D completion flag.
anl ADCON,#0fch ; Clear the A/D channel number.
ret
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Analog ComparatorsTwo analog comparators are provided on the 87LPC768. Input and
output options allow use of the comparators in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be
configured to cause an interrupt when the output value changes.
Comparator ConfigurationEach comparator has a control register, CMP1 for comparator 1 and
CMP2 for comparator 2. The control registers are identical and are
shown in Figure 4.
The overall connections to both comparators are shown in Figure 5.
There are eight possible configurations for each comparator, as
determined by the control bits in the corresponding CMPn register:
CPn, CNn, and OEn. These configurations are shown in Figure 6.
The comparators function down to a VDD of 3.0V.
When each comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The corresponding comparator interrupt should not be enabled
during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate
interrupt service.
Figure 4. Comparator Control Registers (CMP1 and CMP2)
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Figure 5. Comparator Input and Output Connections
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Internal Reference VoltageAn internal reference voltage generator may supply a default
reference when a single comparator input pin is used. The value of
the internal reference voltage, referred to as Vref, is 1.28 V ±10%.
Comparator InterruptEach comparator has an interrupt flag CMFn contained in its
configuration register. This flag is set whenever the comparator
output changes state. The flag may be polled by software or may be
used to generate an interrupt. The interrupt will be generated when
the corresponding enable bit ECn in the IEN1 register is set and the
interrupt system is enabled via the EA bit in the IEN0 register.
Comparators and Power Reduction ModesEither or both comparators may remain enabled when Power Down
or Idle mode is activated. The comparators will continue to function
in the power reduction mode. If a comparator interrupt is enabled, a
change of the comparator output state will generate an interrupt and
wake up the processor. If the comparator output to a pin is enabled,
the pin should be configured in the push-pull mode in order to obtain
fast switching times while in power down mode. The reason is that
with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin
does not take place.
Comparators consume power in Power Down and Idle modes, as
well as in the normal operating mode. This fact should be taken into
account when system power consumption is an issue.
Comparator Configuration ExampleThe code shown in Figure 7 is an example of initializing one
comparator. Comparator 1 is configured to use the CIN1A and
CMPREF inputs, outputs the comparator result to the CMP1 pin,
and generates an interrupt when the comparator output changes.
The interrupt routine used for the comparator must clear the
interrupt flag (CMF1 in this case) before returning.
Figure 7.
Pulse Width ModulatorThe 87LPC768 contains four Pulse Width Modulated (PWM)
channels which generate pulses of programmable length and
interval. The output for PWM0 is on P0.1, PWM1 on P1.6, PWM2
on P1.7 and PWM3 on P0.1. After chip reset the internal output of
the each PWM channel is a “1.” Note that the state of the pin will
not reflect this if UCFG1.5, PRHI, is set to a zero. In this case
before the pin will reflect the state of the internal PWM output a “1”
must be written to each port bit that serves as a PWM output. A
block diagram is shown in Figure 8.
The interval between successive outputs is controlled by a 10–bit
down counter which uses the internal microcontroller clock as its
input. When bit 3 in the UCFG1 register is a “1” the microcontroller
clock, and therefore the PWM counter clock, has the same
frequency as the clock source defined by the FOSC bits in UCFG1.
When bit 3 in the UCFG1 register is a “0” the microcontroller and
PWM counter clocks operate at half the frequency of clock source
defined by the FOSC bits in UCFG1. When the counter reaches
underflow it is reloaded with a user selectable value. This
mechanism allows the user to set the PWM frequency at any integer
sub–multiple of the microcontroller clock frequency. The repetition
frequency of the PWM is given by:
fPWM = FC / (CNSW+1)
where CNSW is contained in CNSW0 and CNSW1 as described in
the following tables.
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The word “Shadow” in the above refers to the fact that writes are not
into the register that controls the counter; rather they are into a
holding register. As described below the transfer of data from this
holding register, into the register which contains the actual reload
value, is controlled by the user’s program.
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The width of each PWM output pulse is determined by the value in
the appropriate compare shadow registers, CPSW0 through
CPSW4, CPSW0–3 for bits 0–7 and CPSW4 for bits 7 and 8. When
the counter described above reaches underflow the PWM output is
forced high. It remains high until the compare value is reached at
which point it goes low until the next underflow. The number of
microcontroller clock pulses that the PWMn output is high is given
by:
tHI = (CNSW – CPSWn+1)
A compare value greater than the counter reload value results in the
PWM output being permanently high. In addition there are two
special cases. A compare value of all zeroes, 000, causes the
output to remain permanently high. A compare value of all ones,
3FF, results in the PWM output remaining permanently low. Again
the compare value is loaded into a shadow register. The transfer
from this holding register to the actual compare register is under
program control.
The register assignments are shown below where the number
immediately following “CPSW” identifies the PWM output. Thus
CPSW0 controls the width of PWM0, CPSW1 the width of PWM1
etc. In the case of two digits following “CPSW,” e.g. CPSW00, the
second digit refers to the bit of the compare value. Thus CPSW00
represents the value loaded into bit 0 of the PWM0 compare register
The overall functioning of the PWM module is controlled by the
contents of the PWMCON0 register. The operation of most of the
control bits is straightforward. For example there is an invert bit for
each output which causes results in the output to have the opposite
value compared to its non-inverted output. The transfer of the data
from the shadow registers to the control registers is controlled by the
PWMCON0.6 while PWMCON0.7 allows the PWM to be either in
the run or idle state. The user can monitor when underflow causes
the transfer to occur by monitoring the Transfer bit, PWCON0.6.
When the transfer takes place the PWM logic automatically resets
this bit.
PWMCON1 is written with Transfer set without Run being enabled
the transfer will never take place. Thus if a subsequent write sets
Run without Transfer the compare and counter values will not be
those expected. If Transfer and Run are set, and prior to underflow
there is a subsequent load of PWMCON0 which sets Run but not
Transfer, the transfer will never take place. Again the compare and
counter values that existed prior to the update attempt will be used.
As outlined above the Transfer bit can be polled to determine when
the transfer occurs. Unless there is a compelling reason to do
otherwise, it is recommended that both Run, PWMCON0.7, and
Transfer, PWMCON0.7, be set when PWMCON0 is written.
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state when Run is cleared the Compare registers can be written to
either the “always 1” or “always 0” so the output will have the output
desired when the counter is halted. After this PWMCON0 should be
written with the Transfer and Run bits are enabled. After this is
done PWMCON0 to is polled to find that the Transfer has taken
place. Once the transfer has occurred the Run bit in PWMCON0
can be cleared. The outputs will retain the state they had just prior
to the Run being cleared. If the Brake pin (see discussion below in
section concerning the operation of PWMCON1) is not used to
control the brake function, the “Brake when not running” function can
be used to cause the outputs to have a given state when the PWM
is halted. This approach should be used only in time critical
situations when there is not sufficient time to use the approach
outlined above since going from the Brake state to run without
causing an undefined state on the outputs is not straightforward. A
discussion on this topic is included in the section on PWMCON1.
The Brake function, which is controlled by the contents of the
PWMCON1 register, is somewhat unique. In general when Brake is
asserted the four PWM outputs are forced to a user selected state,
namely the state selected by PWMCON1 bits 0 to 3.
As shown in the description of the operation of the PWMCON1
register if PWMCON1.4 is a “1” brake is asserted under the control
PWMCON1.7, BKCH, and PWMCON1.5, BPEN. As shown if both
are a “0” Brake is asserted. If PWMCON1.7 is a “1” brake is
asserted when the run bit, PWMCON0.7, is a “0.” If PWMCON1.6 is
a “1” brake is asserted when the Brake Pin, P0.2, has the same
polarity as PWMCON1.6. When brake is asserted in response to
this pin the RUN bit, PWMCON0.7, is automatically cleared. The
combination of both PWMCON1.7 and PWMCON1.5 being a “1” is
not allowed.
Since the Brake Pin being asserted will automatically clear the Run
bit, PWMCON0.7, the user program can poll this bit to determine
needed if the Brake signal can be of insufficient length to ensure
that it can be captured by a polling routine.
When, after being asserted, the condition causing the brake is
removed, the PWM outputs go to whatever state that had
immediately prior to the brake. This means that in order to go from
brake being asserted to having the PWM run without going through
an indeterminate state care must be taken. If the Brake Pin causes
brake to be asserted the following prototype code will allow the
PWM to go from brake to run smoothly. Rewrite PWMCON1 to change from Brake Pin enabled to S/W
Brake Write CPSW.(0:4) to always “1”, 11 h, or always “0” 00 h, to give
brake pattern Set PWMCON0 to enable Run and Transfer.
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with 4 kB OTP 8-bit A/D, Pulse Width Modulator Poll PWMCON0 to find that Transfer Bit PWMCON0.6 is “0”.
When “0”: Write CNSW.(0:1) and CPSW.(0:4) for desired pulse widths and
counter reload values Set PWMCON0 to Run and Transfer
Note that if a narrow pulse on the Brake Pin causes brake to be
asserted, it may not be possible to go through the above code
before the end of the pulse. In this case, in addition to the code
shown, an external latch on the Brake Pin may be required to
ensure that there is a smooth transition in going from brake to run.
The details for PWMCON1 are shown in the following table.
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2 C Serial InterfaceThe I2 C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the
bus are: Bidirectional data transfer between masters and slaves. Serial addressing of slaves (no added wiring). Acknowledgment after each transferred byte. Multimaster bus. Arbitration between simultaneously transmitting masters without
corruption of serial data on bus.
The I2C subsystem includes hardware to simplify the software required
to drive the I2C bus. The hardware is a single bit interface which in
addition to including the necessary arbitration and framing error
checks, includes clock stretching and a bus timeout timer. The
interface is synchronized to software either through polled loops
or interrupts.
Refer to the application note AN422, entitled “Using the 8XC751
Microcontroller as an I2C Bus Master” for additional discussion of
the 8xC76x I2C interface and sample driver routines.
The 87LPC768 I2C implementation duplicates that of the 87C751
and 87C752 except for the following details: The interrupt vector addresses for both the I2C interrupt and the
Timer I interrupt. The I2C SFR addresses (I2CON, !2CFG, I2DAT). The location of the I2C interrupt enable bit and the name of the
SFR it is located within (EI2 is Bit 0 in IEN1). The location of the Timer I interrupt enable bit and the name of the
SFR it is located within (ETI is Bit 7 in IEN1). The I2 C and Timer I interrupts have a settable priority.
Timer I is used to both control the timing of the I2 C bus and also to
detect a “bus locked” condition, by causing an interrupt when
nothing happens on the I2 C bus for an inordinately long period of
time while a transmission is in progress. If this interrupt occurs, the
program has the opportunity to attempt to correct the fault and
resume I2 C operation.
Six time spans are important in I2 C operation and are insured by timer I: The MINIMUM HIGH time for SCL when this device is the master. The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I2C flags. The software response time normally
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met. The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition. The MINIMUM SDA HIGH TO SDA LOW time between I2C stop
and start conditions (4.7ms, see I2C specification). The MINIMUM SDA LOW TO SCL LOW time in a start condition.
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
the I2C bus caused all masters to withdraw from I2C arbitration.
The first five of these times are 4.7 ms (see I2C specification) and
are covered by the low order three bits of timer I. Timer I is clocked
by the 87LPC768 CPU clock. Timer I can be pre-loaded with one of
four values to optimize timing for different oscillator frequencies. At
lower frequencies, software response time is increased and will
degrade maximum performance of the I2C bus. See special function
register I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I2C operation is enabled, this counter is
cleared by transitions on the SCL pin. The timer does not run
between I2C frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the I2C interface
and generates an interrupt if the Timer I interrupt is enabled. In
cases where the bus hang-up is due to a lack of software response
by this device, the reset releases SCL and allows I2C operation
among other devices to continue.
Timer I is enabled to run, and will reset the I2C interface upon
overflow, if the TIRUN bit in the I2CFG register is set. The Timer I
interrupt may be enabled via the ETI bit in IEN1, and its priority set
by the PTIH and PTI bits in the Ip1H and IP1 registers respectively.
2 C InterruptsIf I2C interrupts are enabled (EA and EI2 are both set to 1), an I2C
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of ATN
following). In practice, it is not efficient to operate the I2 C interface in
this fashion because the I2 C interrupt service routine would somehow
have to distinguish between hundreds of possible conditions. Also,
since I2 C can operate at a fairly high rate, the software may execute
faster if the code simply waits for the I2 C interface.
Typically, the I2 C interrupt should only be used to indicate a start
condition at an idle slave device, or a stop condition at an idle master
device (if it is waiting to use the I2 C bus). This is accomplished by
enabling the I2 C interrupt only during the aforementioned conditions.
Reading I2CONRDAT The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and
there is that reading I2DAT clears DRDY, allowing the2 C to proceed on to another bit. Typically, the first
seven bits of a received byte are read from
I2DAT, while the 8th is read here. Then I2DAT can be
written to send the Acknowledge bit and clear DRDY.
ATN “ATteNtion” is 1 when one or more of DRDY , ARL, STR, or
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I2 C service routine from a “wait loop.”
DRDY “Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared
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Figure 9. I2C Control Register (I2CON)
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Checking ATN and DRDYWhen a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I2C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
and STP.
ARL “Arbitration Loss” is 1 when transmit Active was set, but
this device lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are
four separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the rising
edge of SCL. (If the other device sent a stop, the setting
of ARL will be followed shortly by STP being set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before SCL
could be driven low. (This type of ARL is always
accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this device could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
STR “STaRt” is set to a 1 when an I2 C start condition is
detected at a non-idle slave or at a master. (STR is not
set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising
edge of SCL sets DRDY.)
STP “SToP” is set to 1 when an I2 C stop condition is
detected at a non-idle slave or at a master. (STP is not
set for a stop condition at an idle slave.)
MASTER “MASTER” is 1 if this device is currently a master on
the I2 C. MASTER is set when MASTRQ is 1 and the
bus is not busy (i.e., if a start bit hasn’t been
received since reset or a “Timer I” time-out, or if a stop
has been received since the last start). MASTER is
cleared when ARL is set, or after the software writes
MASTRQ = 0 and then XSTP = 1.
Writing I2CONTypically, for each bit in an I2 C message, a service routine waits for
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does this.)
Regarding Transmit ActiveTransmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I2 C interface will only drive
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with CXA
= 1. Transmit Active is automatically cleared when ARL is 1.
IDLE Writing 1 to “IDLE” causes a slave’s I2C hardware to
ignore the I2C until the next start condition (but if
MASTRQ is 1, then a stop condition will cause this
device to become a master).
CDR Writing a 1 to “Clear Data Ready” clears DRDY.
(Reading or writing the I2DAT register also does this.)
CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
CSTR Writing a 1 to “Clear STaRt” clears the STR bit.
CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that
if one or more of DRDY, ARL, STR, or STP is 1, the low
time of SCL is stretched until the service routine
responds by clearing them.
XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the
I2C hardware to send a repeated start condition. This
should only be at a master. Note that XSTR need not
and should not be used to send an “initial”
(non-repeated) start; it is sent automatically by the I2C
hardware. Writing XSTR = 1 includes the effect of
writing I2DAT with XDAT = 1; it sets Transmit Active
and releases SDA to high during the SCL low time.
After SCL goes high, the I2 C hardware waits for the
suitable minimum time and then drives SDA low to
make the start condition.
XSTP Writing 1s to “Xmit SToP” and CDR tells the I2C
hardware to send a stop condition. This should only be
done at a master. If there are no more messages to
initiate, the service routine should clear the MASTRQ
bit in I2CFG to 0 before writing XSTP with 1. Writing
XSTP = 1 includes the effect of writing I2DAT with
XDAT = 0; it sets Transmit Active and drives SDA low
during the SCL low time. After SCL goes high, the I2C
hardware waits for the suitable minimum time and then
releases SDA to high to make the stop condition.
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Figure 11. I2C Configuration Register (I2CFG)
Regarding Software Response TimeBecause the 87LPC768 can run at 20 MHz, and because the I2C
interface is optimized for high-speed operation, it is quite likely that
an I2C service routine will sometimes respond to DRDY (which is set
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I2C protocol violation. The programmer need not worry
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I2 C service routine may take
a long time to respond to DRDY. Typically, an I2 C routine operates
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I2 C service routine. The programmer need not worry
about this very much either, because the I2 C hardware stretches the
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out.
Values to be used in the CT1 and CT0 bits are shown in Table 2. To
allow the I2 C bus to run at the maximum rate for a particular
oscillator frequency, compare the actual oscillator rate to the f OSC
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where CPU clock max is greater than or equal
to the actual frequency.
Table 2 also shows the machine cycle count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high�low time(in microseconds)�6* Min Time Count
CPU clock(in MHz)
For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the
minimum SCL high and low times will be 5.25 μs.
Table 2 also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I2 C interface is operating, Timer I is pre-loaded
at every SCL transition with a value dependent upon CT1/CT0. The
pre-load value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
pre-loaded into Timer I is 8 minus the machine cycle count).
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Table 3. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
Table 4. CT1, CT0 Values
InterruptsThe 87LPC768 uses a four priority level interrupt structure. This
allows great flexibility in controlling the handling of the 87LPC768’s many
interrupt sources. The 87LPC768 supports up to 13 interrupt sources.
Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in registers IEN0 or IEN1. The IEN0
register also contains a global disable bit, EA, which disables all
interrupts at once.
Each interrupt source can be individually programmed to one of four
priority levels by setting or clearing bits in the IP0, IP0H, IP1, and
IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt
of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two
requests of different priority levels are received simultaneously, the
request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is serviced. This
is called the arbitration ranking. Note that the arbitration ranking is
only used to resolve simultaneous requests of the same priority level.
Table 3 summarizes the interrupt sources, flag bits, vector
addresses, enable bits, priority bits, arbitration ranking, and whether
each interrupt may wake up the CPU from Power Down mode.
Table 5. Summary of Interrupts
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External Interrupt InputsThe 87LPC768 has two individual interrupt inputs as well as the
Keyboard Interrupt function. The latter is described separately
elsewhere in this section. The two interrupt inputs are identical to
those present on the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITn = 0, external interrupt n is triggered by a detected low
at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In
this mode if successive samples of the INTn pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEn in TCON
is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 6 CPU Clocks to
ensure proper sampling. If the external interrupt is
transition-activated, the external source has to hold the request pin
high for at least one machine cycle, and then hold it low for at least
one machine cycle. This is to ensure that the transition is seen and
that interrupt request flag IEn is set. IEn is automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must
hold the request active until the requested interrupt is actually
generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is
not necessary to clear the interrupt flag IEn when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the 87LPC768 is put into
Power Down or Idle mode, the interrupt will cause the processor to
wake up and resume operation. Refer to the section on Power
Reduction Modes for details.
Figure 12. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources
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I/O PortsThe 87LPC768 has 3 I/O ports, port 0, port 1, and port 2. The exact
number of I/O pins available depend upon the oscillator and reset
options chosen. At least 15 pins of the 87LPC768 may be used as
I/Os when a two-pin external oscillator and an external reset circuit
are used. Up to 18 pins may be available if fully on-chip oscillator
and reset configurations are chosen.
All but three I/O port pins on the 87LPC768 may be software
configured to one of four types on a bit-by-bit basis, as shown in
Table 4. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input only. Two configuration
registers for each port choose the output type for each port pin.
Table 6. Port Output Configuration Settings
Quasi-Bidirectional Output ConfigurationThe default port output configuration for standard 87LPC768 I/O
ports is the quasi-bidirectional output that is common on the 80C51
and most of its derivatives. This output type can be used as both an
input and output without the need to reconfigure the port. This is
possible because when the port outputs a logic high, it is weakly
driven, allowing an external device to pull the pin low. When the pin
is pulled low, it is driven strongly and able to sink a fairly large
current. These features are somewhat similar to an open drain
output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on
whenever the port latch for the pin contains a logic 1. The very weak
pull-up sources a very small current that will pull the pin high if it is
left floating.
A second pull-up, called the “weak” pull-up, is turned on when the
port latch for the pin contains a logic 1 and the pin itself is also at a
logic 1 level. This pull-up provides the primary source current for a
quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1
on it is pulled low by an external device, the weak pull-up turns off,
and only the very weak pull-up remains on. In order to pull the pin
low under these conditions, the external device has to sink enough
current to overpower the weak pull-up and take the voltage on the
port pin below its input threshold.
The third pull-up is referred to as the “strong” pull-up. This pull-up is
used to speed up low-to-high transitions on a quasi-bidirectional port
pin when the port latch changes from a logic 0 to a logic 1. When this
occurs, the strong pull-up turns on for a brief time, two CPU clocks, in
order to pull the port pin high quickly. Then it turns off again.
The quasi-bidirectional port configuration is shown in Figure 13.
Figure 13. Quasi-Bidirectional Output
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Open Drain Output ConfigurationThe open drain output configuration turns off all pull-ups and only
drives the pull-down transistor of the port driver when the port latch
contains a logic 0. To be used as a logic output, a port configured in
this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the
quasi-bidirectional mode.
The open drain port configuration is shown in Figure 14.
Push-Pull Output ConfigurationThe push-pull output configuration has the same pull-down structure
as both the open drain and the quasi-bidirectional output modes, but
provides a continuous strong pull-up when the port latch contains a
logic 1. The push-pull mode may be used when more source current
is needed from a port output.
The push-pull port configuration is shown in Figure 15.
The three port pins that cannot be configured are P1.2, P1.3, and
P1.5. The port pins P1.2 and P1.3 are permanently configured as
open drain outputs. They may be used as inputs by writing ones to
their respective port latches. P1.5 may be used as a Schmitt trigger
input if the 87LPC768 has been configured for an internal reset and
is not using the external reset input function RST.
Additionally, port pins P2.0 and P2.1 are disabled for both input and
output if one of the crystal oscillator options is chosen. Those
options are described in the Oscillator section.
The value of port pins at reset is determined by the PRHI bit in the
UCFG1 register. Ports may be configured to reset high or low as
needed for the application. When port pins are driven high at reset,
they are in quasi-bidirectional mode and therefore do not source
large amounts of current.
Every output on the 87LPC768 may potentially be used as a 20 mA
sink LED drive output. However, there is a maximum total output
current for all ports which must not be exceeded.
All ports pins of the 87LPC768 have slew rate controlled outputs. This
is to limit noise generated by quickly switching output signals. The
slew rate is factory set to approximately 10 ns rise and fall times.
The bits in the P2M1 register that are not used to control
configuration of P2.1 and P2.0 are used for other purposes. These
bits can enable Schmitt trigger inputs on each I/O port, enable
toggle outputs from Timer 0 and Timer 1, and enable a clock output
if either the internal RC oscillator or external clock input is being
used. The last two functions are described in the Timer/Counters
and Oscillator sections respectively. The enable bits for all of these
functions are shown in Figure 16.
Each I/O port of the 87LPC768 may be selected to use TTL level
inputs or Schmitt inputs with hysteresis. A single configuration bit
determines this selection for the entire port. Port pins P1.2, P1.3,
and P1.5 always have a Schmitt trigger input.
Figure 14. Open Drain Output
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Figure 16. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the 87LPC768, as
shown in Figure 17. This interrupt may be used to wake up the CPU
from Idle or Power Down modes. This feature is particularly useful in
handheld, battery powered systems that need to carefully manage
power consumption yet also need to be convenient to use.
The 87LPC768 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 18. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Figure 17. Keyboard Interrupt
Figure 18. Keyboard Interrupt Register (KBI)
Philips Semiconductors Preliminary data
87LPC768Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
OscillatorThe 87LPC768 provides several user selectable oscillator options,
allowing optimization for a range of needs from high precision to
lowest possible cost. These are configured when the EPROM is
programmed. Basic oscillator types that are supported include: low,
medium, and high speed crystals, covering a range from 20 kHz to
20 MHz; ceramic resonators; and on-chip RC oscillator.
Low Frequency Oscillator OptionThis option supports an external crystal in the range of 20 kHz to 100 kHz.
Table 7 shows capacitor values that may be used with a quartz crystal in this mode.
Table 7. Recommended oscillator capacitors for use with the low frequency oscillator option
Medium Frequency Oscillator OptionThis option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
Table 8 shows capacitor values that may be used with a quartz crystal in this mode.
Table 8. Recommended oscillator capacitors for use with the medium frequency oscillator option
High Frequency Oscillator OptionThis option supports an external crystal in the range of 4 to 20 MHz. Ceramic resonators are also supported in this configuration.
Table 9 shows capacitor values that may be used with a quartz crystal in this mode.
Table 9. Recommended oscillator capacitors for use with the high frequency oscillator option
On-Chip RC Oscillator OptionThe on-chip RC oscillator option has a typical frequency of 6 MHz
and can be divided down for slower operation through the use of the
DIVM register. Note that the on-chip oscillator has a ±25% frequency
tolerance and for that reason may not be suitable for use in some
applications. A clock output on the X2/P2.0 pin may be enabled
when the on-chip RC oscillator is used.
External Clock Input OptionIn this configuration, the processor clock is input from an external
source driving the X1/P2.1 pin. The rate may be from 0 Hz up to
pin may be used as a standard port pin. A clock output on the X2/P2.0
pin may be enabled when the external clock input is used.
Clock OutputThe 87LPC768 supports a clock output function when either the
on-chip RC oscillator or external clock input options are selected.
This allows external devices to synchronize to the 87LPC768. When
enabled, via the ENCLK bit in the P2M1 register, the clock output
appears on the X2/CLKOUT pin whenever the on-chip oscillator is
running, including in Idle mode. The frequency of the clock output is
1/6 of the CPU clock rate. If the clock output is not needed in Idle
