P87LPC764BD ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPINTEGRATED CIRCUITSP87LPC764Low power, low price, low pin count(20 pin) microcontroller with 4 kbyt ..
P87LPC764BD. ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPFEATURES • Selectable Schmitt trigger port inputs.• An accelerated 80C51 CPU provides instruction c ..
P87LPC764BDH ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPFEATURES . . . . . 1ORDERING INFORMATION . . . . . . . 1
P87LPC764BDH ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPELECTRICAL CHARACTERISTICS . 46AC
P87LPC764BN ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPPIN CONFIGURATION, 20-PIN DIP, SO, AND TSSOP PACKAGES . . . . 2LOGIC SYMBOL . 2
P87LPC764FD ,Low power, low price, low pin count 20 pin microcontroller with 4 kbyte OTPGENERAL DESCRIPTIONselected to allow a graceful system shutdown when power fails.The P87LPC764 is a ..
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P87LPC764BD-P87LPC764BD.-P87LPC764FD-P87LPC764FDH
Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP
Product data
Supersedes data of 2001 Oct 26
2003 Sep 03
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
GENERAL DESCRIPTIONThe P87LPC764 is a 20-pin single-chip microcontroller designed for
low pin count applications demanding high-integration, low cost
solutions over a wide range of performance requirements. A
member of the Philips low pin count family, the P87LPC764 offers
programmable oscillator configurations for high and low speed
crystals or RC operation, wide operating voltage range,
programmable port output configurations, selectable Schmitt trigger
inputs, LED drive outputs, and a built-in watchdog timer. The
P87LPC764 is based on an accelerated 80C51 processor
architecture that executes instructions at twice the rate of standard
80C51 devices.
FEATURES An accelerated 80C51 CPU provides instruction cycle times of
300–600 ns for all instructions except multiply and divide when
executing at 20 MHz. Execution at up to 20 MHz when
VDD = 4.5 V to 6.0 V, 10 MHz when VDD = 2.7 V to 6.0 V. 4.5 V to 5.5 V for P87LPC764HDH. 2.7 V to 6.0 V operating range for digital functions. 4 kbytes EPROM code memory. 128 byte RAM data memory. 32 byte customer code EPROM allows serialization of devices,
storage of setup parameters, etc. Two 16-bit counter/timers. Each timer may be configured to toggle
a port output upon timer overflow. Two analog comparators. Full duplex UART.I2 C communication port. Eight keypad interrupt inputs, plus two additional external interrupt
inputs. Four interrupt priority levels. Watchdog timer with separate on-chip oscillator, requiring no
external components. The watchdog timeout time is selectable
from 8 values. Active low reset. On-chip power-on reset allows operation with no
external reset components. Low voltage reset. One of two preset low voltage levels may be
selected to allow a graceful system shutdown when power fails.
May optionally be configured as an interrupt. Oscillator Fail Detect. The watchdog timer has a separate fully
on-chip oscillator, allowing it to perform an oscillator fail detect
function. Configurable on-chip oscillator with frequency range and RC
oscillator options (selected by user programmed EPROM bits).
The RC oscillator option allows operation with no external
oscillator components. Programmable port output configuration options:
quasi-bidirectional, open drain, push-pull, input-only. Selectable Schmitt trigger port inputs. LED drive capability (20 mA) on all port pins. Controlled slew rate port outputs to reduce EMI. Outputs have
approximately 10 ns minimum ramp times. 15 I/O pins minimum. Up to 18 I/O pins using on-chip oscillator
and reset options. Only power and ground connections are required to operate the
P87LPC764 when fully on-chip oscillator and reset options are
selected. Serial EPROM programming allows simple in-circuit production
coding. Two EPROM security bits prevent reading of sensitive
application programs. Idle and Power Down reduced power modes. Improved wakeup
from Power Down mode (a low interrupt input starts execution).
Typical Power Down current is 1 μA. 20-pin DIP, SO, and TSSOP packages.
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
ORDERING INFORMATION
DEVICE COMPARISON TABLE1
NOTE: Please see AC and DC characteristics for more details.
PIN CONFIGURATION, 20-PIN DIP , SO, AND TSSOP PACKAGES
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
LOGIC SYMBOL
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
BLOCK DIAGRAM
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
Figure 1. P87LPC764 Program and Data Memory Map
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
PIN DESCRIPTIONS
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
SPECIAL FUNCTION REGISTERS
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
NOTES:* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
Philips Semiconductors Product data
P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
FUNCTIONAL DESCRIPTIONDetails of P87LPC764 functions will be described in the following
sections.
Enhanced CPUThe P87LPC764 uses an enhanced 80C51 CPU which runs at twice
the speed of standard 80C51 devices. This means that the
performance of the P87LPC764 running at 5 MHz is exactly the same
as that of a standard 80C51 running at 10 MHz. A machine cycle
consists of 6 oscillator cycles, and most instructions execute in 6 or 12
clocks. A user configurable option allows restoring standard 80C51
execution timing. In that case, a machine cycle becomes 12 oscillator
cycles.
In the following sections, the term “CPU clock” is used to refer to the
clock that controls internal instruction execution. This may
sometimes be different from the externally applied clock, as in the
case where the part is configured for standard 80C51 timing by
means of the CLKR configuration bit or in the case where the clock
is divided down via the setting of the DIVM register. These features
are described in the Oscillator section.
Analog FunctionsThe P87LPC764 incorporates two Analog Comparators. In order to
give the best analog function performance and to minimize power
consumption, pins that are actually being used for analog functions
must have the digital outputs and the digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input
Only (high impedance) mode as described in the I/O Ports section
(see page 17).
Digital inputs on port 0 may be disabled through the use of the
PT0AD register. Each bit in this register corresponds to one pin of
Port 0. Setting the corresponding bit in PT0AD disables that pin’s
digital input. Port bits that have their digital inputs disabled will be
read as 0 by any instruction that accesses the port.
Analog ComparatorsTwo analog comparators are provided on the P87LPC764. Input and
output options allow use of the comparators in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be
configured to cause an interrupt when the output value changes.
Comparator ConfigurationEach comparator has a control register, CMP1 for comparator 1 and
CMP2 for comparator 2. The control registers are identical and are
shown in Figure 2.
The overall connections to both comparators are shown in Figure 3.
There are eight possible configurations for each comparator, as
determined by the control bits in the corresponding CMPn register:
CPn, CNn, and OEn. These configurations are shown in Figure 4.
The comparators function down to a VDD of 3.0V.
When each comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The corresponding comparator interrupt should not be enabled
during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate
interrupt service.
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
Figure 3. Comparator Input and Output Connections
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
Internal Reference VoltageAn internal reference voltage generator may supply a default
reference when a single comparator input pin is used. The value of
the internal reference voltage, referred to as Vref, is 1.28 V ±10%.
Comparator InterruptEach comparator has an interrupt flag CMFn contained in its
configuration register. This flag is set whenever the comparator
output changes state. The flag may be polled by software or may be
used to generate an interrupt. The interrupt will be generated when
the corresponding enable bit ECn in the IEN1 register is set and the
interrupt system is enabled via the EA bit in the IEN0 register.
Comparators and Power Reduction ModesEither or both comparators may remain enabled when Power Down
or Idle mode is activated. The comparators will continue to function
in the power reduction mode. If a comparator interrupt is enabled, a
change of the comparator output state will generate an interrupt and
wake up the processor. If the comparator output to a pin is enabled,
the pin should be configured in the push-pull mode in order to obtain
fast switching times while in power down mode. The reason is that
with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin
does not take place.
Comparators consume power in Power Down and Idle modes, as
well as in the normal operating mode. This fact should be taken into
account when system power consumption is an issue.
Comparator Configuration ExampleThe code shown in Figure 5 is an example of initializing one
comparator. Comparator 1 is configured to use the CIN1A and
CMPREF inputs, outputs the comparator result to the CMP1 pin,
and generates an interrupt when the comparator output changes.
The interrupt routine used for the comparator must clear the
interrupt flag (CMF1 in this case) before returning.
Figure 5.
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2 C Serial InterfaceThe I2 C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the
bus are: Bidirectional data transfer between masters and slaves. Serial addressing of slaves (no added wiring). Acknowledgment after each transferred byte. Multimaster bus. Arbitration between simultaneously transmitting masters without
corruption of serial data on bus.
The I2C subsystem includes hardware to simplify the software required
to drive the I2C bus. The hardware is a single bit interface which in
addition to including the necessary arbitration and framing error
checks, includes clock stretching and a bus timeout timer. The
interface is synchronized to software either through polled loops
or interrupts.
Refer to the application note AN422, entitled “Using the 8XC751
Microcontroller as an I2C Bus Master” for additional discussion of
the 8xC76x I2C interface and sample driver routines.
The P87LPC764 I2C implementation duplicates that of the 87C751
and 87C752 except for the following details: The interrupt vector addresses for both the I2C interrupt and the
Timer I interrupt. The I2C SFR addresses (I2CON, I2CFG, I2DAT). The location of the I2C interrupt enable bit and the name of the
SFR it is located within (EI2 is Bit 0 in IEN1). The location of the Timer I interrupt enable bit and the name of the
SFR it is located within (ETI is Bit 7 in IEN1). The I2 C and Timer I interrupts have a settable priority.
Timer I is used to both control the timing of the I2 C bus and also to
detect a “bus locked” condition, by causing an interrupt when
nothing happens on the I2 C bus for an inordinately long period of
time while a transmission is in progress. If this interrupt occurs, the
program has the opportunity to attempt to correct the fault and
resume I2 C operation.
Six time spans are important in I2 C operation and are insured by timer I: The MINIMUM HIGH time for SCL when this device is the master. The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
responds to the I2C flags. The software response time normally
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met. The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition. The MINIMUM SDA HIGH TO SDA LOW time between I2C stop
and start conditions (4.7ms, see I2C specification). The MINIMUM SDA LOW TO SCL LOW time in a start condition.
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
the I2C bus caused all masters to withdraw from I2C arbitration.
The first five of these times are 4.7 ms (see I2C specification) and
are covered by the low order three bits of timer I. Timer I is clocked
by the P87LPC764 CPU clock. Timer I can be pre-loaded with one
of four values to optimize timing for different oscillator frequencies.
At lower frequencies, software response time is increased and will
degrade maximum performance of the I2C bus. See special function
register I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I2C operation is enabled, this counter is
cleared by transitions on the SCL pin. The timer does not run
between I2C frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
on SCL. A carry out causes a hardware reset of the I2C interface
and generates an interrupt if the Timer I interrupt is enabled. In
cases where the bus hang-up is due to a lack of software response
by this device, the reset releases SCL and allows I2C operation
among other devices to continue.
Timer I is enabled to run, and will reset the I2C interface upon
overflow, if the TIRUN bit in the I2CFG register is set. The Timer I
interrupt may be enabled via the ETI bit in IEN1, and its priority set
by the PTIH and PTI bits in the IP1H and IP1 registers respectively.
2 C InterruptsIf I2C interrupts are enabled (EA and EI2 are both set to 1), an I2C
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of ATN
following). In practice, it is not efficient to operate the I2 C interface in
this fashion because the I2 C interrupt service routine would somehow
have to distinguish between hundreds of possible conditions. Also,
since I2 C can operate at a fairly high rate, the software may execute
faster if the code simply waits for the I2 C interface.
Typically, the I2 C interrupt should only be used to indicate a start
condition at an idle slave device, or a stop condition at an idle master
device (if it is waiting to use the I2 C bus). This is accomplished by
enabling the I2 C interrupt only during the aforementioned conditions.
Reading I2CONRDAT The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and
there is that reading I2DAT clears DRDY, allowing the2 C to proceed on to another bit. Typically, the first
seven bits of a received byte are read from
I2DAT, while the 8th is read here. Then I2DAT can be
written to send the Acknowledge bit and clear DRDY.
ATN “ATteNtion” is 1 when one or more of DRDY , ARL, STR, or
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I2 C service routine from a “wait loop.”
DRDY “Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
Figure 6. I2C Control Register (I2CON)
Figure 7. I2 C Data Register (I2DAT)
Checking ATN and DRDYWhen a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I2 C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
ARL “Arbitration Loss” is 1 when transmit Active was set, but
this device lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are
four separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the rising
edge of SCL. (If the other device sent a stop, the setting
of ARL will be followed shortly by STP being set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before SCL
could be driven low. (This type of ARL is always
accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this device could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
STR “STaRt” is set to a 1 when an I2C start condition is
detected at a non-idle slave or at a master. (STR is not
set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising
edge of SCL sets DRDY.)
STP “SToP” is set to 1 when an I2 C stop condition is
detected at a non-idle slave or at a master. (STP is not
set for a stop condition at an idle slave.)
MASTER “MASTER” is 1 if this device is currently a master on
the I2 C. MASTER is set when MASTRQ is 1 and the
bus is not busy (i.e., if a start bit hasn’t been
received since reset or a “Timer I” time-out, or if a stop
has been received since the last start). MASTER is
cleared when ARL is set, or after the software writes
MASTRQ = 0 and then XSTP = 1.
Writing I2CONTypically, for each bit in an I2 C message, a service routine waits for
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does this.)
Regarding Transmit ActiveTransmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I2 C interface will only drive
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with CXA
= 1. Transmit Active is automatically cleared when ARL is 1.
IDLE Writing 1 to “IDLE” causes a slave’s I2C hardware to
ignore the I2C until the next start condition (but if
MASTRQ is 1, then a stop condition will cause this
device to become a master).
CDR Writing a 1 to “Clear Data Ready” clears DRDY.
(Reading or writing the I2DAT register also does this.)
CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
CSTR Writing a 1 to “Clear STaRt” clears the STR bit.
CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that
if one or more of DRDY, ARL, STR, or STP is 1, the low
time of SCL is stretched until the service routine
responds by clearing them.
XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the
I2C hardware to send a repeated start condition. This
should only be at a master. Note that XSTR need not
and should not be used to send an “initial”
(non-repeated) start; it is sent automatically by the I2C
hardware. Writing XSTR = 1 includes the effect of
writing I2DAT with XDAT = 1; it sets Transmit Active
and releases SDA to high during the SCL low time.
After SCL goes high, the I2 C hardware waits for the
suitable minimum time and then drives SDA low to
make the start condition.
XSTP Writing 1s to “Xmit SToP” and CDR tells the I2C
hardware to send a stop condition. This should only be
done at a master. If there are no more messages to
initiate, the service routine should clear the MASTRQ
bit in I2CFG to 0 before writing XSTP with 1. Writing
XSTP = 1 includes the effect of writing I2DAT with
XDAT = 0; it sets Transmit Active and drives SDA low
during the SCL low time. After SCL goes high, the I2C
hardware waits for the suitable minimum time and then
releases SDA to high to make the stop condition.
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
Figure 8. I2C Configuration Register (I2CFG)
Regarding Software Response TimeBecause the P87LPC764 can run at 20 MHz, and because the I2C
interface is optimized for high-speed operation, it is quite likely that
an I2C service routine will sometimes respond to DRDY (which is set
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I2C protocol violation. The programmer need not worry
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I2 C service routine may take
a long time to respond to DRDY. Typically, an I2 C routine operates
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I2 C service routine. The programmer need not worry
about this very much either, because the I2 C hardware stretches the
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out.
Values to be used in the CT1 and CT0 bits are shown in Table 2. To
allow the I2 C bus to run at the maximum rate for a particular
oscillator frequency, compare the actual oscillator rate to the f OSC
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where CPU clock max is greater than or equal
to the actual frequency.
Table 2 also shows the machine cycle count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high�low time(in microseconds)�6* Min Time Count
CPU clock(in MHz)
For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the
minimum SCL high and low times will be 5.25 μs.
Table 2 also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I2 C interface is operating, Timer I is pre-loaded
at every SCL transition with a value dependent upon CT1/CT0. The
pre-load value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
pre-loaded into Timer I is 8 minus the machine cycle count).
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Table 1. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
Table 2. CT1, CT0 Values
InterruptsThe P87LPC764 uses a four priority level interrupt structure. This
allows great flexibility in controlling the handling of the P87LPC764’s
many interrupt sources. The P87LPC764 supports up to 12 interrupt
sources.
Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in registers IEN0 or IEN1. The IEN0
register also contains a global disable bit, EA, which disables all
interrupts at once.
Each interrupt source can be individually programmed to one of four
priority levels by setting or clearing bits in the IP0, IP0H, IP1, and
IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt
of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two
requests of different priority levels are received simultaneously, the
request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is serviced. This
is called the arbitration ranking. Note that the arbitration ranking is
only used to resolve simultaneous requests of the same priority level.
Table 3 summarizes the interrupt sources, flag bits, vector
addresses, enable bits, priority bits, arbitration ranking, and whether
each interrupt may wake up the CPU from Power Down mode.
Table 3. Summary of Interrupts
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
External Interrupt InputsThe P87LPC764 has two individual interrupt inputs as well as the
Keyboard Interrupt function. The latter is described separately
elsewhere in this section. The two interrupt inputs are identical to
those present on the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITn = 0, external interrupt n is triggered by a detected low
at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In
this mode if successive samples of the INTn pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEn in TCON
is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 6 CPU Clocks to
ensure proper sampling. If the external interrupt is
transition-activated, the external source has to hold the request pin
high for at least one machine cycle, and then hold it low for at least
one machine cycle. This is to ensure that the transition is seen and
that interrupt request flag IEn is set. IEn is automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must
hold the request active until the requested interrupt is actually
generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is
not necessary to clear the interrupt flag IEn when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the P87LPC764 is put into
Power Down or Idle mode, the interrupt will cause the processor to
wake up and resume operation. Refer to the section on Power
Reduction Modes for details.
Figure 9. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources
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P87LPC764Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
I/O Ports18The P87LPC764 has 3 I/O ports, port 0, port 1, and port 2. The
exact number of I/O pins available depend upon the oscillator and
reset options chosen. At least 15 pins of the P87LPC764 may be
used as I/Os when a two-pin external oscillator and an external
reset circuit are used. Up to 18 pins may be available if fully on-chip
oscillator and reset configurations are chosen.
All but three I/O port pins on the P87LPC764 may be software
configured to one of four types on a bit-by-bit basis, as shown in
Table 4. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input only. Two configuration
registers for each port choose the output type for each port pin.
Table 4. Port Output Configuration Settings
Quasi-Bidirectional Output ConfigurationThe default port output configuration for standard P87LPC764 I/O
ports is the quasi-bidirectional output that is common on the 80C51
and most of its derivatives. This output type can be used as both an
input and output without the need to reconfigure the port. This is
possible because when the port outputs a logic high, it is weakly
driven, allowing an external device to pull the pin low. When the pin
is pulled low, it is driven strongly and able to sink a fairly large
current. These features are somewhat similar to an open drain
output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on
whenever the port latch for the pin contains a logic 1. The very weak
pull-up sources a very small current that will pull the pin high if it is
left floating.
A second pull-up, called the “weak” pull-up, is turned on when the
port latch for the pin contains a logic 1 and the pin itself is also at a
logic 1 level. This pull-up provides the primary source current for a
quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1
on it is pulled low by an external device, the weak pull-up turns off,
and only the very weak pull-up remains on. In order to pull the pin
low under these conditions, the external device has to sink enough
current to overpower the weak pull-up and take the voltage on the
port pin below its input threshold.
The third pull-up is referred to as the “strong” pull-up. This pull-up is
used to speed up low-to-high transitions on a quasi-bidirectional port
pin when the port latch changes from a logic 0 to a logic 1. When this
occurs, the strong pull-up turns on for a brief time, two CPU clocks, in
order to pull the port pin high quickly. Then it turns off again.
The quasi-bidirectional port configuration is shown in Figure 10.
Figure 10. Quasi-Bidirectional Output
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Open Drain Output ConfigurationThe open drain output configuration turns off all pull-ups and only
drives the pull-down transistor of the port driver when the port latch
contains a logic 0. To be used as a logic output, a port configured in
this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the
quasi-bidirectional mode.
The open drain port configuration is shown in Figure 11.
Push-Pull Output ConfigurationThe push-pull output configuration has the same pull-down structure
as both the open drain and the quasi-bidirectional output modes, but
provides a continuous strong pull-up when the port latch contains a
logic 1. The push-pull mode may be used when more source current
is needed from a port output.
The push-pull port configuration is shown in Figure 12.
The three port pins that cannot be configured are P1.2, P1.3, and
P1.5. The port pins P1.2 and P1.3 are permanently configured as
open drain outputs. They may be used as inputs by writing ones to
their respective port latches. P1.5 may be used as a Schmitt trigger
input if the P87LPC764 has been configured for an internal reset
and is not using the external reset input function RST.
Additionally, port pins P2.0 and P2.1 are disabled for both input and
output if one of the crystal oscillator options is chosen. Those
options are described in the Oscillator section.
The value of port pins at reset is determined by the PRHI bit in the
UCFG1 register. Ports may be configured to reset high or low as
needed for the application. When port pins are driven high at reset,
they are in quasi-bidirectional mode and therefore do not source
large amounts of current.
Every output on the P87LPC764 may potentially be used as a 20
mA sink LED drive output. However, there is a maximum total output
current for all ports which must not be exceeded.
All ports pins of the P87LPC764 have slew rate controlled outputs.
This is to limit noise generated by quickly switching output signals.
The slew rate is factory set to approximately 10 ns rise and fall times.
The bits in the P2M1 register that are not used to control
configuration of P2.1 and P2.0 are used for other purposes. These
bits can enable Schmitt trigger inputs on each I/O port, enable
toggle outputs from Timer 0 and Timer 1, and enable a clock output
if either the internal RC oscillator or external clock input is being
used. The last two functions are described in the Timer/Counters
and Oscillator sections respectively. The enable bits for all of these
functions are shown in Figure 13.
Each I/O port of the P87LPC764 may be selected to use TTL level
inputs or Schmitt inputs with hysteresis. A single configuration bit
determines this selection for the entire port. Port pins P1.2, P1.3,
and P1.5 always have a Schmitt trigger input.
Figure 11. Open Drain Output
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Figure 13. Port 2 Mode Register 1 (P2M1)
Keyboard Interrupt (KBI)The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the P87LPC764,
as shown in Figure 14. This interrupt may be used to wake up the
CPU from Idle or Power Down modes. This feature is particularly
useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
The P87LPC764 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
the KBI register, as shown in Figure 15. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
Due to human time scales and the mechanical delay associated with
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
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Figure 14. Keyboard Interrupt
Figure 15. Keyboard Interrupt Register (KBI)
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OscillatorThe P87LPC764 provides several user selectable oscillator options,
allowing optimization for a range of needs from high precision to
lowest possible cost. These are configured when the EPROM is
programmed. Basic oscillator types that are supported include: low,
medium, and high speed crystals, covering a range from 20 kHz to
20 MHz; ceramic resonators; and on-chip RC oscillator.
Low Frequency Oscillator OptionThis option supports an external crystal in the range of 20 kHz to 100 kHz.
Table 5 shows capacitor values that may be used with a quartz crystal in this mode.
Table 5. Recommended oscillator capacitors for use with the low frequency oscillator option
Medium Frequency Oscillator OptionThis option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
Table 6 shows capacitor values that may be used with a quartz crystal in this mode.
Table 6. Recommended oscillator capacitors for use with the medium frequency oscillator option
High Frequency Oscillator OptionThis option supports an external crystal in the range of 4 to 20 MHz. Ceramic resonators are also supported in this configuration.
Table 7 shows capacitor values that may be used with a quartz crystal in this mode.
Table 7. Recommended oscillator capacitors for use with the high frequency oscillator option
On-Chip RC Oscillator OptionThe on-chip RC oscillator option has a typical frequency of 6 MHz
and can be divided down for slower operation through the use of the
DIVM register. For on-chip oscillator tolerance see AC Electrical
Characteristics table. A clock output on the X2/P2.0 pin may be
enabled when the on-chip RC oscillator is used.
External Clock Input OptionIn this configuration, the processor clock is input from an external
source driving the X1/P2.1 pin. The rate may be from 0 Hz up to
20 MHz when VDD is above 4.5 V and up to 10 MHz when VDD is
Clock OutputThe P87LPC764 supports a clock output function when either the
on-chip RC oscillator or external clock input options are selected.
This allows external devices to synchronize to the P87LPC764.
When enabled, via the ENCLK bit in the P2M1 register, the clock
output appears on the X2/CLKOUT pin whenever the on-chip
oscillator is running, including in Idle mode. The frequency of the
clock output is 1/6 of the CPU clock rate. If the clock output is not
needed in Idle mode, it may be turned off prior to entering Idle,
saving additional power. The clock output may also be enabled
when the external clock input option is selected.
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Figure 16. Using the Crystal Oscillator
Figure 17. Using an External Clock Input
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Figure 18. Block Diagram of Oscillator Control
CPU Clock Modification: CLKR and DIVMFor backward compatibility, the CLKR configuration bit allows
setting the P87LPC764 instruction and peripheral timing to match
standard 80C51 timing by dividing the CPU clock by two. Default
timing for the P87LPC764 is 6 CPU clocks per machine cycle while
standard 80C51 timing is 12 clocks per machine cycle. This
division also applies to peripheral timing, allowing 80C51 code that
is oscillator frequency and/or timer rate dependent. The CLKR bit
is located in the EPROM configuration register UCFG1, described
under EPROM Characteristics
In addition to this, the CPU clock may be divided down from the
oscillator rate by a programmable divider, under program control.
This function is controlled by the DIVM register. If the DIVM register
is set to zero (the default value), the CPU will be clocked by either
the unmodified oscillator rate, or that rate divided by two, as
determined by the previously described CLKR function.
When the DIVM register is set to some value N (between 1 and 255),
the CPU clock is divided by 2 * (N + 1). Clock division values from 4
through 512 are thus possible. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption,
in a manner similar to Idle mode. By dividing the clock, the CPU can
retain the ability to respond to events other than those that can cause
interrupts (i.e. events that allow exiting the Idle mode) by executing its
normal program at a lower rate. This can allow bypassing the
oscillator startup time in cases where Power Down mode would
Power Monitoring FunctionsThe P87LPC764 incorporates power monitoring functions designed
to prevent incorrect operation during initial power up and power loss
or reduction during operation. This is accomplished with two
hardware functions: Power-On Detect and Brownout Detect.
Brownout DetectionThe Brownout Detect function allows preventing the processor from
failing in an unpredictable manner if the power supply voltage drops
below a certain level. The default operation is for a brownout
detection to cause a processor reset, however it may alternatively
be configured to generate an interrupt by setting the BOI bit in the
AUXR1 register (AUXR1.5).
The P87LPC764 allows selection of two Brownout levels: 2.5 V or
3.8 V. When VDD drops below the selected voltage, the brownout
detector triggers and remains active until VDD is returns to a level
above the Brownout Detect voltage. When Brownout Detect causes
a processor reset, that reset remains active as long as VDD remains
below the Brownout Detect voltage. When Brownout Detect
generates an interrupt, that interrupt occurs once as VDD crosses
from above to below the Brownout Detect voltage. For the interrupt
to be processed, the interrupt system and the BOI interrupt must
both be enabled (via the EA and EBO bits in IEN0).
When Brownout Detect is activated, the BOF flag in the PCON
register is set so that the cause of processor reset may be determined
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For correct activation of Brownout Detect, the VDD fall time must be
no faster than 50 mV/μs. When VDD is restored, is should not rise
faster than 2 mV/μs in order to insure a proper reset.
The brownout voltage (2.5 V or 3.8 V) is selected via the BOV bit in
the EPROM configuration register UCFG1. When unprogrammed
(BOV = 1), the brownout detect voltage is 2.5 V. When programmed
(BOV = 0), the brownout detect voltage is 3.8 V.
If the Brownout Detect function is not required in an application, it
may be disabled, thus saving power. Brownout Detect is disabled by
setting the control bit BOD in the AUXR1 register (AUXR1.6).
Power On DetectionThe Power On Detect has a function similar to the Brownout Detect,
but is designed to work as power comes up initially, before the
power supply voltage reaches a level where Brownout Detect can
work. When this feature is activated, the POF flag in the PCON
register is set to indicate an initial power up condition. The POF flag
will remain set until cleared by software.
Power Reduction ModesThe P87LPC764 supports Idle and Power Down modes of power
reduction.
Idle ModeThe Idle mode leaves peripherals running in order to allow them to
activate the processor when an interrupt is generated. Any enabled
interrupt source or Reset may terminate Idle mode. Idle mode is
entered by setting the IDL bit in the PCON register (see Figure 19).
Power Down ModeThe Power Down mode stops the oscillator in order to absolutely
minimize power consumption. Power Down mode is entered by
setting the PD bit in the PCON register (see Figure 19).
The processor can be made to exit Power Down mode via Reset or
one of the interrupt sources shown in Table 5. This will occur if the
interrupt is enabled and its priority is higher than any interrupt
currently in progress.
In Power Down mode, the power supply voltage may be reduced to
the RAM keep-alive voltage VRAM. This retains the RAM contents
at the point where Power Down mode was entered. SFR contents
are not guaranteed after VDD has been lowered to VRAM, therefore
it is recommended to wake up the processor via Reset in this case.
VDD must be raised to within the operating range before the Power
Down mode is exited. Since the watchdog timer has a separate
oscillator, it may reset the processor upon overflow if it is running
during Power Down.
Note that if the Brownout Detect reset is enabled, the processor will
be put into reset as soon as VDD drops below the brownout voltage.
If Brownout Detect is configured as an interrupt and is enabled, it will
wake up the processor from Power Down mode when VDD drops
below the brownout voltage.
When the processor wakes up from Power Down mode, it will start
the oscillator immediately and begin execution when the oscillator is
stable. Oscillator stability is determined by counting 1024 CPU
clocks after start-up when one of the crystal oscillator configurations
is used, or 256 clocks after start-up for the internal RC or external
clock input configurations.
Some chip functions continue to operate and draw power during
Power Down mode, increasing the total power used during Power
Down. These include the Brownout Detect, Watchdog Timer, and
Comparators.
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Table 8. Sources of Wakeup from Power Down Mode
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Low Voltage EPROM OperationThe EPROM array contains some analog circuits that are not
required when VDD is less than 4 V, but are required for a VDD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with VDD less than 4 V.
ResetThe P87LPC764 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The P87LPC764 can additionally be configured to use P1.5 as an
external active-low reset pin RST by programming the RPD bit in the
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the P87LPC764 is held in reset until the signal goes high.
The watchdog timer on the LPC764 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin
Figure 21. Block Diagram Showing Reset Sources
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Timer/CountersThe P87LPC764 has two general purpose counter/timers which are
upward compatible with the standard 80C51 Timer 0 and Timer 1.
Both can be configured to operate either as timers or event counters
(see Figure 22). An option to automatically toggle the T0 and/or T1
pins upon timer overflow has been added.
In the “Timer” function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 6 CPU clock periods, the count rate is 1/6
of the CPU clock frequency. Refer to the section Enhanced CPU for
a description of the CPU clock.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition at its corresponding external input pin, T0 or T1.
In this function, the external input is sampled once during every
machine cycle. When the samples of the pin state show a high in
one cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during the cycle following
the one in which the transition was detected. Since it takes 2
machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the
maximum count rate is 1/6 of the CPU clock frequency. There are no
restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes,
it should be held for at least one full machine cycle.
The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. In addition to the “Timer” or
“Counter” selection, Timer 0 and Timer 1 have four operating
modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0,
1, and 2 are the same for both Timers/Counters. Mode 3 is different.
The four operating modes are described in the following text.
Figure 22. Timer/Counter Mode Control Register (TMOD)
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Mode 0Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 24
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to the Timer when TRn = 1 and
either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INTn, to facilitate pulse width
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 23). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See
Figure 24. There are two different GATE bits, one for Timer 1
(TMOD.7) and one for Timer 0 (TMOD.3).
Figure 23. Timer/Counter Control Register (TCON)
Figure 24. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
