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P87C591VFA
Single-chip 8-bit microcontroller with CAN controller
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
CONTENTS FEATURES
1.1 80C51 Related Features of the 8xC591
1.2 CAN Related Features of the 8xC591 GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION
6.1 Pinning diagram
6.2 Pin description MEMORY ORGANIZATION
7.1 Program Memory
7.2 Addressing
7.3 Expanded Data RAM addressing
7.4 Dual DPTR I/O FACILITIES OSCILLATOR CHARACTERISTICS RESET LOW POWER MODES
11.1 Stop Clock Mode
11.2 Idle Mode
11.3 Power-down Mode CAN, CONTROLLER AREA NETWORK
12.1 Features of the PeliCAN controller
12.2 PeliCAN structure
12.3 Communication between PeliCAN controller
and CPU
12.4 Register and Message Buffer description
12.5 CAN Registers SERIAL I/O SIO0 STANDARD SERIAL INTERFACE UART
14.1 Multiprocessor Communications
14.2 Serial Port Control Register
14.3 Baud Rate Generation
14.4 More about UART Modes
14.5 Enhanced UART SIO1, I2C SERIAL IO
15.1 Modes of Operation
15.2 SIO1 Implementation and Operation
15.3 Software Examples of SIO1 Service Routines TIMER 2
16.1 Features of Timer 2 WATCHDOG TIMER (T3) PULSE WIDTH MODULATED OUTPUTS
18.1 Prescaler Frequency Control Register (PWMP)
18.2 Pulse Width Register 0 (PWM0)
18.3 Pulse Width Register 1 (PWM1) PORT 1 OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC)
20.1 ADC features
20.2 ADC functional description
20.3 10-Bit Analog-to-Digital Conversion
20.4 10-Bit ADC Resolution and Analog Supply
20.5 Power Reduction Modes INTERRUPTS
21.1 Interrupt Enable Registers
21.2 Interrupt Enable and Priority Registers
21.3 Interrupt priority
21.4 Interrupt Vectors INSTRUCTION SET
22.1 Addressing Modes LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS
25.1 Timing symbol definitions EPROM CHARACTERISTICS
26.1 Program verification
26.2 Security bits PACKAGE OUTLINES SOLDERING
28.1 Plastic leaded-chip carriers/quad flat-packs DEFINITIONS LIFE SUPPORT APPLICATIONS
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
FEATURES
1.1 80C51 Related Features of the 8xC591 Full static 80C51 Central Processing Unit available as
OTP, ROM and ROMless 16 Kbytes internal Program Memory expandable
externally to 64 Kbytes 512 bytes on-chip Data RAM expandable externally to Kbytes Three 16-bit timers/counters T0, T1 (standard 80C51)
and additional T2 (capture & compare) 10-bit ADC with 6 multiplexed analog inputs with fast
8-bit ADC option Two 8-bit resolution, Pulse Width Modulated outputs 32 I/O port pins in the standard 80C51 pinoutI2 C-bus serial I/O port with byte oriented master and
slave functions On-chip Watchdog Timer T3 Extended temperature range: −40to +85°C Accelerated (prescaler 1:1) instruction cycle time
500ns@12 MHz Operation voltage range: 5V± 5% Security bits: ROM version has 2 bits OTP/EPROM version has 3 bits 32 bytes Encryption array 4 level priority interrupt, 15 interrupt sources Full-duplex enhanced UART with programmable
Baudrate Generator Power Control Modes: Clock can be stopped and resumed Idle Mode Power-down Mode ADC active in Idle Mode Second DPTR register ALE inhibit for EMI reduction Programmable I/O port pins (pseudo bi-directional,
push-pull, high impedance, open drain) Wake-up from Power-down by external interrupts Software reset bit (AUXR1.5) Low active reset pin Power-on detect reset Once mode
1.2 CAN Related Features of the 8xC591 CAN 2.0B active controller, supporting 11-bit Standard
and 29-bit Extended indentifiers 1 Mbit/s CAN bus speed with 8 MHz clock achievable 64 byte receive FIFO (can capture sequential Data
Frames from the same source as required by the
Transport Layerof higher protocols suchas DeviceNet,
CANopen and OSEK) 13 byte transmit buffer EnhancedPeliCAN core (from the SJA1000 stand-alone
CAN2.0B controller)
1.2.1 PELICAN FEATURES Four independently configurable Screeners
(Acceptance Filters) Each Screener has two 32-bit specifies: 32-bit Match and 32-bit Mask 32-bits of Mask per Screener allows unique Group
addressing per Screener Higher layer protocols especially supportedin Standard
CAN format with: Up to four, 11-bit ID Screeners that also Screen the
two (2) Data Bytes i.e., Data Frames are Screened bytheCAN IDandby
Data Byte content Up to eight, 11-bit ID Screeners half of which also
Screen the first Data Byte All Screeners are changeable “on the fly” Listen Only Mode, Self Test Mode Error Code Capture, Arbitration Lost Capture, readable
Error Counters
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
GENERAL DESCRIPTIONThe P8xC591 is a single-chip 8-bit-high-performance
microcontroller, with on-chip CAN-controller, derived from
the 80C51 microcontroller family. uses the powerful 80C51 instruction set and includes the
successful PeliCAN functionality of the SJA1000 CAN
controller from Philips Semiconductors.
The fully static core provides extended power save
provisions as the oscillator can be stopped and easily
restarted without lossof data. The improved internal clock
prescalerof 1:1 achievesa 500ns instruction cycle timeat MHz external clock rate.
Figure 1 shows a Block Diagram of the P8xC591. The
microcontroller is manufactured in an advanced CMOS
process, and is designed for use in automotive and
general industrial applications. In addition to the 80C51
standard features, the device provides a number of
dedicated hardware functions for these applications.
Two versions of the P8xC591 will be offered: P83C591 (with ROM) P87C591 (with OTP)
Hereafter these versions will be referred to as P8xC591.
The temperature range includes (max. fCLK = 12 MHz): -40 to +85 °C version, for general applications
The P8xC591 combines the functions of the P87C554
(microcontroller) and the SJA1000 (stand-alone
CAN-controller) with the following enhanced features: Enhanced CAN receive interrupt (level sensitive) Extended acceptance filter Acceptance filter changeable “on the fly”.
The main differences between P8xC591 and P87C554
are: CAN-controller on chip 6-input ADC Low active Reset 44 leads.
ORDERING INFORMATION
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
BLOCK DIAGRAM
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
FUNCTIONAL DIAGRAM
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 PINNING INFORMATION
6.1 Pinning diagram
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
6.2 Pin description
Table 1 Pin description for QFP44/PLCC44, see Note1.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Notes To avoid“latch-up” effectas power-on, the voltageon any pin atany time must notbe higheror lower than VDD +0.5V
or VSS −0.5 V. Not implemented for P1.6 and P1.7.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands in three memory spaces as follows (see Fig.5): 16 Kbytes internal resp. 64 Kbytes external Program Memory 512 bytes internal Data Memory Main-and Auxiliary RAM up to 64 Kbytes external Data Memory (with 256 bytes residing in the internal Auxiliary RAM).
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
7.1 Program Memory
The P8xC591 contains 16 Kbytes of on-chip Program
Memory which canbe extendedto64 Kbytes with external
memories. When EA pin is held HIGH, the P8xC591
fetches instructions from internal ROM unless the address
exceeds 3FFFh. Locations 4000h to FFFFh are fetched
from external Program Memory. When the EA pin is held
LOW, all instruction fetches are from external memory.
The EA pinis latched during reset andis “don’t care” after
reset.
Both, for the ROM and EPROM version of the P8xC591,
precautions are implementedto protect the device against
illegal Program Memory code reading.
7.2 Addressing
The P8xC591 has five methods for addressing the
Program and Data memory: Register Direct Register-Indirect Immediate Base-Register plus Index-Register-Indirect.
For more details about Addressing modes please referto
Section 22.1 “Addressing Modes”.
7.3 Expanded Data RAM addressing
The P8xC591 has internal data memory that is mapped
into four separate segments: the lower 128 bytesof RAM,
upper 128 bytes of RAM, 128 bytes Special Function
Register (SFR), and 256 bytes Auxiliary RAM (AUX-RAM)
as shown in Figure5.
The four segments are: The Lower 128 bytesof RAM (addresses 00Hto 7FH)
are directly and indirectly addressable (see Fig.6). The Upper 128 bytesof RAM (addresses 80Hto FFH)
are indirectly addressable. The Special Function Registers, SFRs, (addresses
80H to FFH) are directly addressable only. All these
SFRs are described in Table4. The 256-bytes AUX-RAM (00H - FFH) are indirectly
accessed by move external instruction, MOVX, and
within the EXTRAM bit cleared, see Table 3.
The Lower 128 bytes can be accessed by either direct or
indirect addressing. The Upper 128 bytes can be
accessed by indirect addressing only. The Upper 128
bytes occupy the same address space as the SFR. That
means they have the same address, but are physically
separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the CPU knows whether the accessisto the
upper 128 bytes of data RAM or to SFR space by the
addressing mode usedin the instruction. Instructions that
use direct addressing access SFR space.
For example:
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2).
Instructions that use indirect addressing access the Upper
128 bytes of data RAM.
For example:
MOV @ R0,#data
where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
The AUX-RAM can be accessed by indirect addressing,
with EXTRAM bit cleared and MOVX instructions. This
part of memory is physically located on-chip, logically
occupies the first 256-bytes of external data memory.
With EXTRAM=0, the AUX-RAMis indirectly addressed,
using the MOVX instructionin combination with anyof the
registers R0,R1of the selected bankor DPTR.An access AUX-RAM will not affect ports P0, P3.6 (WR#) and P3.7
(RD#). P2 SFR is output during external addressing. For
example, with EXTRAM = 0,
MOV @ R0,#data
where R0 contains 0A0h, access the AUX-RAM at
address 0A0H rather than external memory.An accessto
external data memory locations higher than FFH (i.e.,
0100Hto FFFFH) willbe performed with the MOVX DPTR
instructionsin the same wayasin the standard 80C51,so
with P0 and P2 as data/address bus, and P3.6 and P3.7
as write and read timing signals. Refer to Table4.
With EXTRAM=1, MOVX@Ri and MOVX@ DPTR will similarto the standard 80C51. MOVX@Ri will provide
an 8-bit address multiplexed with data on Port 0 and any
output port pins can be used to output higher order
address bits. This is to provide the external paging
capability. MOVX@ DPTR will generatea 16-bit address.
Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order
eight addressbits (DPL)with data. MOVX@Ri and MOVX DPTR will generate either reador write signalson P3.6
(#WR) and P3.7 (#RD).
The stack pointer (SP) may be located anywhere in the
256 bytes RAM (lower and upper RAM) internal data
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Table 2 AUX-RAM Page Register (address 8EH)
Table 3 Description of AUX-RAM bits
Notes User software should not write ‘1’sto reserved bits. These bits maybe usedin future 80C51 family productsto invoke
new features.In that case, the resetor inactiveof the newbit willbe0, andits active value willbe‘1’. The value read
from a reserved bit is indeterminate. Reset value is ‘xxxxxx10B’.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
7.3.1 SPECIAL FUNCTION REGISTERS
Table 4 Special Function Register Bit Address, Symbol or Alternate Port Function
* = SFRs are bit addressable; # = SFRs are modified from or added to the 80C51 SFRs.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
7.4 Dual DPTR
The dual DPTR structure (see Figure7)isa wayby which
the chip will specify the address of an external data
memorylocation. There are two16-bit DPTR registers that
address the external memory, anda singlebit called DPS
= AUXR1/bit0 that allows the program code to switch
between them.
The DPS bit status should be saved by software when
switching between DPTR0 and DPTR1.
Note thatbit2is not writable andis always readasa zero.
This allows the DPS bit to be quickly toggled simply by
executingan INC AUXR1 instruction without affecting the
other bits.
DPTR Instructions
The instructions that referto DPTRreferto the data pointer
that is currently selected using the AUXR1/bit 0 register.
The six instructions that use the DPTR are as follows:
INC DPTRIncrements the data pointer by 1
MCV DPTR, #data 16 Loads the DPTR witha 16-bit
constant
MOV A, @ A+DPTR Move code byte relative to
DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit
address) to ACC
MOVX @ DPTR, A Move ACC to external RAM
(16-bit address)
JMP @ A + DPTR Jump indirect relative to
DPTR
The data pointer canbe accessedona byte-by-byte basis
by specifying the low or high byte in an instruction which
accesses the SFRs. See application note AN458for more
details.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
7.4.1 AUXR1 PAGE REGISTER
Table 5 AUXR1 Page Register (address A2H)
Table 6 Description of AUXR1 of bits
User software should not write 1s to reserved bits. Theses bits may be used in future 8051 family products to invoke
new features.In that case, the resetor inactive valueof the newbit willbe logic0, andits active value willbe logic1. The
value read from a reserved bit is indeterminate. The reset value of AUXR1 is (000000xB).
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 I/O FACILITIES
The P8xC591 consists of 32 I/O Port lines with partly
multiple functions. The I/O’s are held HIGH during reset
(asynchronous, before oscillator is running).
Ports0,1, 2 and 3 perform the following alternative
functions:
Port 0 is the same as in the 80C51. After reset the Port
Special Function Registeris setto ‘FFh’as known
from other 80C51 derivatives. Port0 also provides
the multiplexed low-order address and data bus
used for expanding the P8xC591 with standard
memories and peripherals.
Port 1 supports several alternative functionalities. For this
reason it has different I/O stages. Note, port P1.0
and P1.1 are Driven-High and P1.2 to P1.7 are
High-Impedance (Tri-state) after reset.
Port 2 is the same as in the 80C51. After reset the Port
Special Function Registeris setto ‘FFh’as known
from other 80C51 derivatives. Port2 also provides
the high-order address bus when the P8xC591 is
expanded with external Program Memory and/or
external Data Memory.
Port 3is the sameasin the 80C51. During reset the Port Special Function Registerissetto ‘FFh’ asknown
from other 80C51 derivatives. OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier. The pins can be configured for
useasan on-chip oscillator,as shownin the logic symbol. drive the device froman external clock source, XTAL1
should be driven while XTAL2 is left unconnected. There
areno requirementson the duty cycleof the external clock
signal. However, minimum and maximum high and low
times specified in the data sheet must be observed. RESET
A reset is accomplished by holding the RST pin LOW for
at least two machine cycles (12 oscillator periods), while
the oscillatoris running.To insurea good power-on reset,
theRST pin mustbe low long enoughto allowtheoscillator
time to start up (normally a few milliseconds) plus two
machine cycles.
The RST line can also be pulled LOW internally by a
pull-down transistor activated by the watchdog timer T3.
The lengthof the output pulse fromT3is3 machine cycles.
A pulse of such short duration is necessary in order to
recover from a processor or system fault as fast as
possible.
Note that the short reset pulse from Timer T3 cannot
discharge the power-on reset capacitor (see Figure8).
Consequently, whenthewatchdog timeris alsoused toset
external devices, this capacitorarrangement should notbe
connectedto the RST pin, anda different circuit shouldbe
usedto perform the power-on reset operation.A timerT3
overflow, if enabled, will force a reset condition to the
P8xC591 by an internal connection, whether the output
RST is pulled-up HIGH or not.
A reset may be performed in software by setting the
software reset bit, SRST (AUXR1.5).
This device also has a Power-on Detect Reset circuit as
VCC transitions from VCC past VRST.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 LOW POWER MODES
11.1 Stop Clock Mode
The static design enables the clock speed to be reduced
downto0 MHz (stopped). When the oscillatoris stopped,
the RAM and Special Function Registers retain their
values. This mode allows step-by-step utilization and
permits reduced system power consumption by lowering
the clock frequency down to any value. For lowest power
consumption the Power-down mode is suggested.
11.2 Idle Mode the Idle mode (see Table7), the CPU puts itselfto sleep
while all of the on-chip peripherals stay active. The
instruction to invoke the idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM,
andallof the special function registers remain intactduring
this mode. The Idle mode canbe terminated eitherby any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
11.3 Power-down Mode
To save even more power, a Power-down mode (see
Table 7) can be invoked by software. In this mode, the
oscillator isstopped andtheinstruction that invoked Power
Down is the last instruction executed. The on-chip RAM
and Special Function Registers retain their values downto
2.0V and care must betakento return VCCto the minimum
specified operating voltages before the Power-down Mode
is terminated. hardware resetor external interrupt canbe usedto exit
from Power-down. The Wake-up from Power-down bit,
WUPD (AUXR1.3) must be set in order for an interrupt to
cause a Wake-up from Power-down. Reset redefines all
the SFRs but does not change the on-chip RAM. A
Wake-up allows both the SFRs and the on-chip RAM to
retain their values.
To properly terminate Power-down the reset or external
interrupt should notbe executed before VCCis restoredto
its normal operating level and must be held active long
enough for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 7 Status of external pins during Idle and Power-down modes
Withan external interrupt, INT0 and INT1 mustbe enabled and configuredas level-sensitive. Holding the pin low restarts
the oscillator but bringing the pin back high completes the exit. Once the interruptis serviced, the next instructiontobe
executed after RETI will be the one following the instruction that put the device into Power-down.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
11.3.1 POWER OFF FLAG
The Power Off Flag (POF)is setby on-chip circuitry when
theVCC levelon the P8xC591 risesfrom 0to5V. The POF
bit can be set or cleared by software allowing a user to
determine if the reset is the result of a power-on or warm
after Power-down. The VCC level must remain above 3V
for the POF to remain unaffected by the VCC level.
11.3.2 DESIGN CONSIDERATION When the Idle modeis terminatedbya hardware reset,
the device normally resumes program execution, from
where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits accessto internal RAMin this event, but access
to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is
terminated by reset, the instruction following the one
that invokes Idle should notbe one that writestoa port
pin or to external memory.
11.3.3 ONCETM MODE
The ONCETM (“On-Circuit Emulation”) Mode facilities
testing and debugging of systems without the device
havingtobe removed from the circuit. The ONCE Modeis
invoked by: Pull ALE low while the device is in reset an PSEN is
high, Hold ALE low as RST is deactivated.
While the deviceisin ONCE Mode, the Port0 pinsgo into
a float state, and the other port pins and ALE and PSEN
are weakly pulled high. The oscillator circuit remains
active. While the deviceisin this mode,an emulatoror test
CPU can be used to drive the circuit. Normal operation is
restored when a normal reset is applied.
11.3.4 REDUCED EMI MODE
The ALE-Off bit, AO (AUXR.0) canbe setto0 disable the
ALE output. It will automatically become active when
requiredfor external memory accesses and resumeto the
OFF state after completing the external memory access.
11.3.5 POWER CONTROL REGISTER (PCON)
Table 8 Power Control Register (address 87H)
Table 9 Description of PCON bits
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000).
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 CAN, CONTROLLER AREA NETWORK
Controller Area Network is the definition of a high
performance communication protocol for serial data
communication.TheCAN controller circuitryis designedto
provide a full implementation of the CAN-Protocol
according to the CAN Specification Version 2.0B.
Microcontroller including this on-chip CAN controller are
used to build powerful local networks, both for general
industrial and automotive environments. The result is a
strongly reduced wiring harness and enhanced diagnostic
and supervisory capabilities.
The P8xC591 includes the same functions known from the
SJA1000 stand-alone CAN controller from Philips
Semiconductors with the following improvements: Enhanced receive interrupt Enhanced acceptance filter 8 filter for standard frame formats 4 filter for extended formats “change on the fly” feature.
12.1 Features of the PeliCAN controller
12.1.1 GENERAL CAN FEATURES CAN 2.0B protocol compatibility Multi-master architecture Bus access priority determined by the message
identifier (11 bit or 29 bit) Non destructive bit-wise arbitration Guaranteed latency time for high priority messages Programmable transfer rate (up to 1Mbit/s) Multicast and broadcast message facility Data length from 0 up to 8 bytes Powerful error handling capability Non-return-to-zero (NRZ) coding/decoding with
bit-stuffing Suitable for use in a wide range of networks including
SAE’s network classes A, B, C.
12.1.2 P8XC591 PELICAN FEATURES (ADDITIONALTO
CAN 2.0B) Supports 11-bit identifier as well as 29-bit identifier Bit rates up to 1 Mbit/s Error Counters with read / write access Programmable Error Warning Limit Error Code Capture with detailed bit position Arbitration Lost Interrupt with detailed bit position Single Shot Transmission (no re-transmission) Listen Only Mode (no acknowledge, no active error
flags) Hot Plugging support (software drivenbit rate detection) Extended receive buffer (FIFO, 64 byte) Receive Buffer level sensitive Receive Interrupt High Priority Acceptance Filters for Receive Interrupt Acceptance Filters with “change on the fly” feature Receptionof “own” messages (Self Reception Request) Programmable CAN output driver configuration.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.2 PeliCAN structure
A 80C51 CPU Interface connects the PeliCAN to the internal bus of the P8xC591 microcontroller. Via five Special
Function Registers CANADR, CANDAT, CANMOD, CANSTA and CANCON the CPU has access to the PeliCAN. The
SFR will described later on.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.2.1 INTERFACE MANAGEMENT LOGIC (IML)
The Interface Management Logic interprets commands
from the CPU, controls addressing of the CAN Registers
and provides interrupts and status informationto the CPU.
Additionallyit drives the universal interfaceof the PeliCAN.
12.2.2 TRANSMIT BUFFER (TXB)
The Transmit Bufferisan interface between the CPU and
the Bit Stream Processor (BSP) and is able to store a
complete CAN message which shouldbe transmitted over
the CAN network. The buffer is 13 bytes long, written by
the CPU and read out by the BSP or the CPU itself.
12.2.3 RECEIVE BUFFER (RXB, RXFIFO)
The Receive Buffer is an interface between the
Acceptance Filter and the CPU and stores the received
and accepted messages from the CAN Bus line. The
Receive Buffer (RXB) represents a CPU-accessible
13-byte-windowof the ReceiveFIFO (RXFIFO), whichhas
a total length of 64 bytes. With the help of this FIFO the
CPU is able to process one message while other
messages are being received.
12.2.4 ACCEPTANCE FILTER (ACF)
The Acceptance Filter compares the received identifier
with the Acceptance Filter Table contents and decides
whether this message shouldbe acceptedor not.In case
of a positive acceptance test, the complete message is
stored in the RXFIFO. The ACF contains 4 independent
Acceptance Filter banks supporting extended and
standard CAN frames with “change on the fly” feature.
12.2.5 BIT STREAM PROCESSOR (BSP)
The Bit Stream Processor is a sequencer, controlling the
data streambetween the Transmit Buffer,RXFIFO and the
CAN-Bus.It also performs the error detection, arbitration,
stuffing and error handling on the CAN bus.
12.2.6 ERROR MANAGEMENT LOGIC (EML)
The EML is responsible for the error confinement of the
transfer-layer modules.It gets error announcements from
the BSP and then informs the BSP and IML about error
statistics.
12.2.7 BIT TIMING LOGIC (BTL)
TheBit Timing Logic monitors the serial CAN bus line and
handles the Bus line-related bit timing. It synchronizes to
the bit stream on the CAN Bus on a “recessive” to
“dominant” Bus line transition at the beginning of a
message (hard synchronization) and resynchronizes on
further transitions during the receptionofa message (soft
synchronization). The BTL also provides programmable
time segments to compensate for the propagation delay
times and phase shifts (e.g., dueto oscillator drifts) andto
define the sampling time and the numberof samplestobe
taken within a bit time.
12.2.8 TRANSMIT MANAGEMENT LOGIC (TML)
The Transmit Management Logic provides the driver
signals for the push-pull CAN TX transistor stage.
Depending on the programmable output driver
configuration the external transistors are switched on or
off. Additionally a short circuit protection and the
asynchronous float on hardware reset is performed here.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.3 Communication between PeliCAN controller
and CPU
A 80C51 CPU Interface connects the PeliCAN to the
internal busofan 80C51 microcontroller. Special Function
Registers, allowsa smart and fast accessto the PeliCAN
registers and RAM area. Becauseof thebig address range
to be supported, an indirect pointer based addressing is
included allowing a fast register access with address
autoincrement mode. This reduces the needed numberof
Special Function Registers to an amount of 5. Five Special Function Registers (SFRs) Register address generation in auto-increment mode Access to the complete address range of the PeliCAN
12.3.1 SPECIAL FUNCTION REGISTERS
Via the five Special Function Registers CANADR,
CANDAT, CANMOD, CANSTA and CANCON the CPU
has accessto the PeliCAN Block. Note that CANCON and
CANSTA have different registers mapped depending on
the direction of the access.
The PeliCAN registers may be accessed in two different
ways. The most important registers, which should support
software pollingor are controlling major CAN functions are
accessible directly as separate SFRs. Other parts of the
PeliCAN Block are accessible using an indirect pointer
mechanism. In order to achieve a high data throughput
even if the indirect access is used, an address
auto-increment feature is included here.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Table 10 CAN Special Function Registers
12.3.2 CANADR
This read/write register defines the address of one of the
PeliCAN internal registerstobe accessed via CANDAT.It
could be interpreted as a pointer to the PeliCAN.
The read and writeaccessto the PeliCAN Block registeris
performed using the CANDAT register.
With the implemented auto address increment modea fast
stack-like reading and writing of CAN controller internal
registers is provided. If the currently defined address
within CANADR is above or equal to 32 decimal, the
contentof CANADRis incremented automatically after any
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
the first Transmit Buffer Address (112 decimal) into
CANADR and then moving byteby byteof the messageto
CANDAT. Incrementing CANADR beyond FFh resets
CANADR to 00h.
In case CANADR is below 32 decimal, there is no
automatic address incrementation performed. CANADR
keepsits value evenif CANDATis accessedfor readingor
writing. This is to allow polling of registers in the lower
address space of the PeliCAN controller.
12.3.3 CANDAT REGISTER
CANDAT is implemented as a read/write register.
The Special Function Register CANDAT appearsasa port the CAN controller’s internal register (memory location)
being selectedby CANADR. Readingor writing CANDAT
is effectively an access to that PeliCAN internal register,
which is selected by CANADR. CANDAT is implemented
as a read/write register.
Note that any access to this register automatically
increments CANADR if the current address within
CANADR is above or equal to 32 decimal.
12.3.4 CANMOD
With a read or write access to CANMOD the Mode
Register of the PeliCAN is accessed directly. The Mode
register is located at address 00h within the PeliCAN
Block.
12.3.5 CANSTA
The CANSTA SFR providesa direct accessto the Status
Registerof the PeliCANas wellasto the Interrupt Enable
Register, depending on the direction of the access.
Reading CANSTA is an access to the Status Register of
the PeliCAN (address 2). When writing to CANSTA the
Interrupt Enable Register is accessed (address 4).
12.3.6 CANCON
The CANCON SFR provides a direct access to the
Interrupt Register of the PeliCAN as well as to the
Command register, depending on the direction of the
access.
When reading CANCON the Interrupt Register of the
PeliCAN is accessed (address 3), while writing to
CANCON means an access to the Command Register
(address1).
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.4 Register and Message Buffer description
12.4.1 ADDRESS LAYOUT
The PeliCAN internal registers appear to the host CPU as on-chip memory mapped peripheral registers. Because the
PeliCAN can operatein different modes (Operating/ Reset, see also Mode Register), one haveto distinguish between
different internal address definitions. Starting from CAN Address 128 the complete internal FIFO RAMis mappedto the
CPU Interface.
Table 11 Address allocation
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Notes These address locations reflect the FIFO RAM space behind the current message. The contents are randomly after
power-up and contain the beginningof the next message thatis received after the current one.Ifno further message
is received, parts of old messages may occur here. Register at address 8 performs NO system function; reserved for future use.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5 CAN Registers
12.5.1 RESET VALUES
Detection of a set Reset Mode bit results in aborting the current transmission / reception of a message and entering the
Reset Mode. On the ‘1’-to-’0’ transition of the Reset Mode bit, the CAN controller returns to the mode defined within the
Mode Register.
Table 12 Reset mode configuration
“X” means that the values of these registers or bits are not influenced.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Notes On Bus-Off the Error Warning Interrupt is set, if enabled.If the Reset Mode was entered duetoa Bus-off condition, the Receive Error Counteris cleared and the Transmit Error
Counter is initialized to 127 to count-down the CAN-defined Bus-off recovery time consisting of 128 occurrences of consecutive recessive bits. Internal read/write pointersof the RXFIFO are resetto their initial values.A subsequent read accessto the RXB would
show undefined data values (parts of old messages). If a message is transmitted, this message is written in parallel to
the Receive Buffer.A Receive Interruptis generated only,if this transmission was forcedby the Self Reception Request.
So, even if the Receive Buffer is empty, the last transmitted message may be read from the Receive Buffer until it is
overriddenby the next receivedor transmitted message. Upona Hardware Reset, the RXFIFO pointers are resetto the
physical RAM address “0”. Setting MOD.0by softwareor dueto the Bus-Off event will reset the RXFIFO pointersto the
currently valid FIFO Start Address (RBSA Register) whichis different from the RAM address”0” after the first Release
Receive Buffer command.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.2 MODE REGISTER (MOD)
The contentsof the Mode Register are usedto change the behaviourof the CAN controller. Bits maybe setor resetby
the CPU that uses the Mode Register as a read / write memory. Reserved Bits are read as “0”.
Table 13 Mode Register (MOD) CAN Addr. 0 bit interpretation
Notes A write accessto the bits MOD.1, MOD.2, MOD.5, MOD.6 and MOD.7is possible only,if the Reset Modeis entered
previously. The PeliCAN Block will enter Sleep Mode, if the Sleep Mode bit is set ‘1’ (sleep), there is no bus activity and no
interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a
wake-up interrupt. The CAN controller will wakeupif SMis set LOW (wake-up)or thereis bus activity. On wake-up,
a Wake-up Interrupt is generated. A sleeping CAN controller which wakes up due to bus activity will not be able to
receive this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is
not possiblein Reset Mode. After clearingof Reset Mode, settingof SMis possible first, when Bus-Freeis detected
again. This mode of operation forces the CAN controller to be error passive. Message Transmission is not possible. The
Listen Only Mode can be used e.g. for software driven bit rate detection and “hot plugging”.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 Duringa Hardware resetor when the Bus Statusbitis set‘1’ (Bus-Off), the Reset Modebitis set‘1’ (present). After
the Reset Mode bit is set ‘0’ the CAN controller will wait for: one occurrenceof Bus-Free signal (11 recessive bits),if the preceding reset has been causedby Hardware reset
or a CPU-initiated reset. 128 occurrencesof Bus-Free,if the preceding reset has been caused bya CANcontroller initiated Bus-Off, before
re-entering the Bus-On mode
12.5.3 COMMAND REGISTER (CMR)
The contentsof the Command Register are usedto change the behaviourof the CAN controller. Control bits maybe set
or reset by the CPU which uses the Command Register as a write only memory.
Table 14 Command Register (CMR) CAN Addr. 1, bit interpretation
Notes Upon Self Reception Requesta messageis transmitted and simultaneously receivedif the acceptance filterissetto
the corresponding identifier.A receive anda transmit interrupt will indicate correct self reception. (see also Self Test
Mode in Mode Register). This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as
the Data Overrun Status bit is set no further Data Overrun Interrupt is generated. After reading the contentsof the Receive Buffer, the CPU can release this memory spaceof the RXFIFOby setting
the Release Receive Buffer bit ‘1’. This may result in another message becoming immediately available within the
Receive Buffer.If thereisno other message available, the Receive Interruptbitis reset. The Receive Interruptis also
resetin case thereisno “high priority” message available within the FIFO (see acceptance filter description) and the
available message bytes are equaltoor lessto the specified value within the Receive Interrupt Level Register.If the
RRB command is given, it will take at least 2 internal clock cycles before a new receive interrupt is generated and
Rx Buffer Start Address is updated. The Abort Transmissionbitis used when the CPU requires the suspensionof the previously requested transmission,
e.g.to transmita more urgent message before.A transmission alreadyin progressis not stopped.In orderto seeif
the original message had been either transmitted successfully or aborted, the Transmission Complete Status bit
shouldbe checked. This shouldbe done after the Transmit Buffer Statusbit has been set‘1’ora Transmit Interrupt
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 If the Transmission Request or the Self Reception Request bit was set ‘1’ in a previous command, it cannot be
cancelledby resetting the bits. The requested transmission may onlybe cancelledby setting the Abort Transmission
bits. Setting the command bits CMR.0 and CMR.1 simultaneously results in transmitting a message once. No
re-transmission will be performed in case of an error or arbitration lost (single shot transmission). Setting the
command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the self
reception feature. No re-transmission will be performed in case of an error or arbitration lost. Setting the command
bits CMR.0, CMR.1 and CMR.4 simultaneously resultsin transmittinga message onceas describedfor CMR.0 and
CMR.1. The moment the Transmit Statusbitis set within the Status Register, the internal Transmission RequestBit
is cleared automatically. Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
12.5.4 STATUS REGISTER (SR)
The contentof the Status Register reflects the statusof the CAN controller. The Status Register appearsto the CPUas
a read only memory.
Table 15 Status Register (SR) CAN Addr. 2, bit interpretation
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Notes to Table 15: When the Transmit Error Counter exceeds the limitof 255, the Bus Statusbitis set‘1’ (Bus-Off), the CAN controller
will set the Reset Mode bit ‘1’ (present), an Error Warning and a Bus Error Interrupt is generated, if enabled. The
Transmit Error Counteris setto ‘127’.It will stayin this mode until the CPU clears the Reset Request bit. Once this completed the CAN controller will wait the minimum protocol-defined time (128 occurrencesof the Bus-Free signal)
counting down the Transmit Error Counter. After that the Bus Status bit is cleared (Bus-On), the Error Status bit is
set‘0’ (ok), the Error Counters are reset andan Error Interruptis generated,if enabled. Reading theTX Error Counter
during this time gives information about the status of the Bus-Off recovery. Errors detected during receptionor transmission will effect the error counters accordingto the CAN specification. The
Error Statusbitis set whenat least oneof the error counters has reachedor exceeded the CPU warning limitof 96.
An Error Interrupt is generated, if enabled. If both the Receive Status and the Transmit Status bits are ‘0’ (idle) the CAN-Bus is idle. The Transmission Complete Status bit is set ‘0’ (incomplete) whenever the Transmission Request bit or the Self
Reception Requestbitis set‘1’. The Transmission Complete Statusbit will remain‘0’ untila messageis transmitted
successfully.If the CPU triesto writeto the Transmit Buffer when the Transmit Buffer Statusbitis‘0’ (locked), the written byte will
not be accepted and will be lost without this being signalled. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
spacein the RXFIFOto store the message descriptor andfor each data byte which has been received.If thereis not
enough spaceto store the massage, that messageis dropped and the data overrun conditionis indicatedto the CPU the moment this message becomes valid.If this messageis not completed (e.g. becauseofan error),no overrun
condition is indicated. After readingall messageswithin the RXFIFO and releasing their memory space with the command Release Receive
Buffer this bit is cleared.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.5 INTERRUPT REGISTER (IR)
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt willbe indicatedto the CPU. After this registeris readby the CPUall bits are reset exceptof the Receive
Interrupt bit.
The Interrupt Register appears to the CPU as a read only memory.
Table 16 Interrupt Register (IR) CAN Addr. 3, bit interpretation
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Notes to Table 16: A Wake-Up Interruptis also generated,if the CPU triesto set the Sleepbit while the CAN controlleris involvedin bus
activities or a CAN Interrupt is pending. In order to support high priority messages, the Receive Interrupt is forced immediately upon a received message,
which has passed successfullyan acceptance filter with high priority (see acceptance filter section).As longas only
messages are received via low priority acceptance filters, the receive interrupt is not forced until the FIFO is filled
with more bytes than programmed in the Rx Interrupt Level Register.
The Receive InterruptBitis not cleared upona read accessto the Interrupt Register. Giving the Command “Release
Receive Buffer” will clear RI temporarily. If there is another message available within the FIFO after the release
command, RI is set again. Otherwise RI keeps cleared.
12.5.6 INTERRUPT ENABLE REGISTER (IER)
The register allows to enable different types of interrupt sources which are signalled to the CPU. The Interrupt Enable
Register appears to the CPU as a read / write memory.
Table 17 Interrupt Enable Register (IER) CAN Addr. 4, bit interpretation
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.7 RX INTERRUPT LEVEL (RIL)
The RIL registeris usedto define the receive interrupt levelfor the RXFIFO.A receive interruptis generatedif the number valid CAN message bytesin the RXFIFO exceeds the level specifiedin this register. Note that receive interrupts are
only generated if complete messages have been received. If RIL is set to 00 the PeliCAN functions like the receive
interrupt behaviour of the SJA1000.
Table 18 Bit interpretation of the Rx Interrupt Level (RIL)
12.5.8 BUS TIMING REGISTER0 (BTR0)
The contentsof the Bus Timing Register0 defines the valuesof the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW). This register can be accessed (read/write) if the Reset Mode is active. In Operating Mode, this
register is read only.
Table 19 Bus Timing Register 0 (BTR0) (CAN address 6)
12.5.8.1 Baud Rate Prescaler (BRP)
The periodof the CAN system clock tsclis programmable and determines the individualbit timing. The CAN system clock
is calculated using the following equation:
12.5.8.2 Synchronization Jump Width (SJW)
To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must
resynchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened or lengthened by one resynchronization:
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.9 BUS TIMING REGISTER1 (BTR1)
The contentsof Bus TimingRegister1 defines the length ofthe bitperiod, the location ofthesample point and the number
of samples to be taken at each bit time. This register can be accessed (read/write) if the Reset Mode is active. In
Operating Mode, this register is read only.
Table 20 Bus Timing Register 1 (BTR1) (CAN address 7)
12.5.9.1 Sampling (SAM)
Table 21 Sampling (SAM)
12.5.9.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2)
TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point:
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.10 RX MESSAGE COUNTER (RMC)
The RMC Register (CAN Address 9) reflects the number of messages available within the RXFIFO. The value is
incremented with each receive event and decrementedby the Release Receive Buffer command. After any reset event,
this register is cleared.
Table 22 RX Message Counter (RMC) (CAN address 9)
12.5.11 RX BUFFER START ADDRESS (RBSA)
The RBSA register(CANAddress 10) reflects thecurrently
valid internal RAM address, where the first byte of the
received message, whichis mappedto the Receive Buffer
Window, is stored. With the help of this information it is
possible to interpret the internal RAM contents. The
internal RAM address area beginsat CAN address32 and
may be accessed by the CPU for reading and writing
(writing in Reset Mode only).
Example: RBSAissetto24 (decimal), the current message visible
in the Receive Buffer Window (CAN Address 96 -108) is
stored within the internal RAM beginningat RAM address
24. Because the RAMis also mapped directlyto the CAN
address space beginning at CAN address 128 (equal to
RAM address 0) this message may also be accessed
using CAN address 152 and the following bytes
(CAN Address = RBSA + 128--> 24 + 128= 152).
Always, the Release Receive Buffer Command is given
while thereisat least one more message available within
the FIFO, RBSA is updated to the beginning of the next
message.
On Hardware Reset, this pointer is initialised to “00h”.
Upon a Software Reset (setting of Reset Mode) this
pointer keeps its old value, but the FIFO is cleared, what
means, that the RAM contents are not changed, but the
next received (or transmitted) message will override the
currently visible message within the Receive Buffer
Window.
The RX Buffer Start Address Register appearsto the CPU
as a read only memory in Operating Mode and as read /
write memory in Reset Mode.
Table 23 RX Buffer Start Address (RBSA) (CAN address 10)
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.12 ARBITRATION LOST CAPTURE (ALC)
This register contains information about the bit position of losing arbitration. The Arbitration Lost Capture Register
appears to the CPU as a read only memory. Reserved Bits are read as “0”.
Table 24 Arbitration Lost Capture (ALC) (CAN address 11)
Table 25 Description of Arbitration Lost Capture (ALC) Register bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.13 ERROR CODE CAPTURE (ECC)
This register contains information about the type and location of errors on the bus. The Error Code Capture Register
appears to the CPU as a read only memory.
Table 26 Error Code Capture (ECC) (CAN address 12)
Table 27 Description of Error Code Capture (ECC) Register bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Always if a bus error occurs, the corresponding bus error interrupt is forced, if enabled. In the same time, the current
positionof theBit Stream Processoris captured into the Error Code Capture Register. The content within this registeris
fixed until the users software has read out its content once. From now on the capture mechanism is activated again.
The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt
Register. A new Bus Error Interrupt is not possible until the Capture Register is read out once.
12.5.14 ERROR WARNING LIMIT REGISTER (EWLR)
The Error Warning Limit could be defined within this register. The default value (after hardware reset) is 96d. In Reset
Mode this register appears to the CPU as a read / write memory.
Table 28 Error Warning Limit Register (EWLR) (CAN address 13)
Note that a content change of the EWL-Register is possible only, if the Reset Mode was entered previously. An Error
Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur, until
the Reset Mode is cancelled again.
12.5.15 RX ERROR COUNTER REGISTER (RXERR)
The RX Error Counter Register reflects the current valueof the Receive Error Counter. After hardware reset this register
is initialised to “0”. In Operating Mode this register appears to the CPU as a read only memory. A write access to this
register is possible only in Reset Mode.a Bus Off event occurs, the RX Error counteris initialisedto “0”.As longas Bus Offis valid, writingto this register has
no effect.
Table 29 RX Error Counter Register (RXERR) (CAN address 14)
Note that a CPU-forced content change of the RX Error Counter is possible only, if the Reset Mode was entered
previously.An Error Status change (Status Register),an Error Warningoran Error Passive Interrupt forcedby the new
register content will not occur, until the Reset Mode is cancelled again.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.16 TX ERROR COUNTER REGISTER (TXERR)
TheTX Error Counter Register reflects the current valueof
the Transmit Error Counter. In Operating Mode this
register appears to the CPU as a read only memory. A
write accessto this registeris possibleonlyin ResetMode.
After hardware reset this register is initialised to “0”. If a
bus-off event occurs, theTX Error Counteris initialisedto
127 to count the minimum protocol-defined time (128
occurrencesof the Bus-Free signal). Reading theTX Error
Counter during this time gives information about the status
of the Bus-Off recovery. Bus Offis active,a write accessto TXERRin the range
of 0 to 254 clears the Bus Off Flag and the controller will
wait for one occurrence of 11 consecutive recessive bits
(bus free) after clearing of Reset Mode.
Writing 255to TXERR allowsto initiatea CPU-driven Bus
Off event. Note, that a CPU-forced content change of the
TX Error Counter is possible only, if the Reset Mode was
entered previously.An Erroror Bus Status change (Status
Register), an Error Warning or an Error Passive Interrupt
forced by the new register content will not occur, until the
Reset Mode is cancelled again. After leaving the Reset
Mode, the new TX Counter content is interpreted and the
Bus Off event is performed in the same way, as if it was
forced by a bus error event. That means, that the Reset
Mode is entered again, the TX Error Counter is initialised 127, the RX Counteris cleared andall concerned Status
and Interrupt Register Bits are set.
Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128
occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus
Off recovery (TXERR > 0), Bus Off keeps active and
TXERR is frozen.
Table 30 TX Error Counter Register (TXERR) (CAN address 15)
12.5.17 ACCEPTANCE FILTER
With the help of the Acceptance Filter the CAN controller
is able to allow passing of received messages to the
RXFIFO only when the identifier bits and the Frame Type the received message are equalto the predefined ones
within the Acceptance Filter Registers.Ifat least one filter
matches, the message is copied to the receive FIFO.
The Acceptance Filteris definedby the Acceptance Code
Registers (ACRn) and the Acceptance Mask Registers
(AMRn). Within the Acceptance Code Registers the bit
patterns of messages to be received are defined. The
corresponding Acceptance Mask Registers allow defining
certain bit positions to be “don‘t care”.
The PeliCAN is designed to support four of so called
Acceptance Filter Banks. Each bank has the functionality
known from the SJA1000 with the extension, that a filter
change is possible “on the fly”. Additionally the used
Frame Format of each filter bank is programmable now.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.17.1 Acceptance Filter Mode Register
The current operating mode is defined within the Acceptance Filter Mode Register located at CAN Address 29. A write
access to this register is possible only within Reset Mode (Mode Register).
Table 31 Acceptance Filter Mode Register (ACF Mode) (CAN address 29)
Table 32 Acceptance Filter Mode Register (ACF Mode) 1 bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.17.2 Acceptance Filter Enable Register
Each defined Acceptance Filter is enabled or disabled by a certain bit located within the Acceptance Filter Enable
Register. This allowsto change the Acceptance Filter Contents “on the fly” during normal operationif the corresponding
filteris disabled previously.A disabled Acceptance Filter does not allow passingof messagesto the receive buffer.Ifall
Acceptance Filters are disabled (default after hardware reset) no messages will pass to the receive buffer at all.
Table 33 Acceptance Filter Enable Register (ACF Enable) (CAN address 30)
Table 34 Acceptance Filter Enable Register (ACF Enable)
Note,if the Single Filter Modeis selectedforan Acceptance Filter Bank, this single filteris relatedto the corresponding
Filter 1 Enable Bit. The Filter 2 Enable Bits have no influence within Single Filter Mode.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.17.3 Acceptance Filter Priority Register
For each available Acceptance Filterit couldbe defined, whethera receive interruptis forced immediatelyifa message
passesa certain Acceptance Filteror whether the programmed Receive Interrupt Level shouldbe usedfor interruption.
This allows to use certain Acceptance Filters for alarm message recognition interrupting the host CPU immediately.
Table 35 Acceptance Filter Priority Register (ACF Priority) (CAN address 31)
Table 36 Acceptance Filter Priority Register (ACF Priority)
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.17.4 Single Filter Configuration
In this filter configuration one long filter (4-byte) could be
defined. Thebit correspondences between the filter bytes
and the Message bytes depends on the programmed
Frame Format (see ACF Mode Register).
Single Filter Standard Frame:
If the Standard Frame Format is selected, the complete
Identifier including the RTRbit and the first two data bytes
are used for acceptance filtering. Messages may also be
accepted if there are no data bytes existing due to a set
RTR bit or if there is no or only one data byte because of
the corresponding data length code.
For a successful reception of a message, all single bit
comparisons have to signal acceptance. Note that the 4
least significant bits of AMR1 and ACR1 are not used. In
order to keep compatible with future products these bits
should be programmed to be “don‘t care” by setting
AMR1.3, AMR1.2, AMR1.1 and AMR1.0 to “1”.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Single Filter Extended Frame:
If the Extended Frame Format is selected, the complete
Identifier including the RTR bit is used for acceptance
filtering.
For a successful reception of a message, all single bit
comparisons have to signal acceptance. Note that the 2
least significant bits of AMR3 and ACR3 are not used. In
order to keep compatible with future products these bits
should be programmed to be “don‘t care” by setting
AMR3.1 and AMR3.0 to “1”.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.17.5 Dual Filter Configuration this filter configuration two short filters couldbe defined.
A received message is compared with both filters to
decide, whether this message should be copied into the
Receive Bufferor not.Ifat least oneof the filters signalsan
acceptance, the received message becomes valid. Thebit
correspondences between the filter bytes and the
message bytes dependson the currently received Frame
Format.
Dual Filter Standard Frame: the Standard Frame Formatis selected, the two defined
filters are different. The first filter compares the complete
Standard Identifier including the RTRbit and the first Data
Byteof the message. The second filter just compares the
complete Standard Identifier including the RTR bit.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
For a successful reception of a message, all single bit
comparisons of at least one complete filter have to signal
acceptance.In caseofa set RTRbitora data length code
of “0” no data byte is existing. Nevertheless, a message
may pass Filter1,if the first partupto the RTRbit signals
acceptance.no data byte filteringis requiredfor Filter1, the four least
significant bits of AMR1 and AMR3 have to be set “1”
(don‘t care). Then both filters are working identically using
the standard identifier range including the RTR bit.
Dual Filter Extended Frame: the Extended Frame Formatis selected, the two defined
filters are looking identically. Both filters are comparing the
first two bytes of the Extended Identifier range only.
For a successful reception of a message, all single bit
comparisons of at least one complete filter have to signal
acceptance.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.18 TRANSMIT BUFFER
The global layoutof the Transmit Bufferis shownin Fig.19.
One has to distinguish between the Standard Frame
Format (SFF) and the Extended Frame Format (EFF)
configuration. The transmit buffer allows the definition of
one transmit message with up to eight data bytes.
12.5.18.1T ransmit Buffer Layout
It is subdivided into Descriptor and Data Field where the
first byte of the Descriptor Field is the Frame Information
Byte (Frame Info).It describes the Frame Format (SFFor
EFF), Remote or Data Frame and the Data Length. Two
identifier bytes for SFF and four bytes for EFF messages
follow. The Data Field containsupto eight data bytes. The
Transmit Buffer hasa lengthof13 bytes andis locatedin
the CAN address range from 112to 124.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.18.2 Descriptor Field of the T ransmit Buffer
This configuration is chosen to be compatible with the Receive Buffer Layout (see Section 12.5.19.1).
The values marked with“()”in the Transmit Buffer shouldbe setto the values expectedin the Receive Bufferforan easy
comparison, only when using the Self Reception facility, otherwise they are don’t care.
Table 37 Frame Format (FF) and Remote Transmission Request (RTR) bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.18.3 Data Length Code (DLC)
The number of bytes in the Data Field of a message is
codedby the Data Length Code.At the startofa Remote
Frame transmission the Data Length Code is not
considered due to the RTR bit being ‘1’ (remote). This
forces the numberof transmitted/received data bytestobe Nevertheless, the Data Length Code mustbe specified
correctlyto avoid bus errors,if two CAN controllers starta
Remote Frame transmission with the same identifier
simultaneously.
The rangeof the Data Byte Countis0to8 bytes andis
coded as follows:`
For reasons of compatibility no Data Length Code > 8
should be used. If a value greater than 8 is selected, 8
bytes are transmitted in the data frame with the Data
Length Code specified in DLC.
12.5.18.4 Identifier (ID) Standard Frame Format (SFF) the Identifier consistsof
11 bits (ID.28 to ID.18) and in Extended Frame Format
(EFF) messages the identifier consistsof29 bits (ID.28to
ID.0). ID.28is the most significant bit, whichis transmitted
first on the bus during the arbitration process. The
Identifier actsas the message’s name, usedina receiver
for acceptance filtering, and also determines the bus
access priority during the arbitration process. The lower
thebinary valueof theIdentifier the higher the priority. This dueto the larger numberof leading dominant bits during
arbitration.
12.5.18.5 Data Field
The number of transferred data bytes is defined by the
Data Length Code. The first bit transmitted is the most
significant bit of data byte 1 at address 115 (SFF) or
address 117 (EFF).
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.19 RECEIVE BUFFER
The global layout of the Receive Buffer is very similar to the Transmit Buffer described in the previous chapter. The
Receive Bufferis the accessible partof the RXFIFO andis locatedin the range between CAN Address96 and 108. Each
message is subdivided into a Descriptor and a Data Field.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
12.5.19.1 Descriptor File of the Receive Buffer
Identifier, FrameFormat, Remote Transmission Requestbit andData Length Code have the same meaningas described
in the Transmit Buffer.
Note:
The received Data Length Code located in the Frame
Information Byte represents the real sent Data Length
Code, which may be greater than 8 (depends on
transmitting CAN node). Nevertheless, the maximum
number of received data bytes is 8. This should be taken
into account by reading a message from the Receive
Buffer.
It depends on the data length how many CAN messages
can fit in the RXFIFO at one time. If there is not enough
space for a new message within the RXFIFO, the CAN
controller generatesa Data Overrun condition the moment
this message becomes valid and the acceptance test was
positive.A message thatis partly written into the RXFIFO,
when the Data Overrun situation occurs, is deleted. This
situation is signalled to the CPU via the Status Register
and the Data Overrun Interrupt, if enabled.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 SERIAL I/O
The P8xC591 is equipped with three independent serial
ports: CAN, SIO0 and SIO1. SIO0 is a Standard Serial
Interface UART with enhanced functionality. In following
there will be one Section describing the Standard UART
functionality and an extra Section for Enhanced UART.
SIO1 accommodates the I2 C bus. SIO0 STANDARD SERIAL INTERFACE UART
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
beforea previously received byte has been read from the
register. (However,if the first byte still hasn’t been readby
the time reception of the second byte is complete, one of
the bytes willbe lost.) The serial port receive and transmit
registers are both accessed at Special Function Register
transmit registers are both accessed at Special Function
Register S0BUF. Writing to S0BUF loads the transmit
register, and reading S0BUF accesses a physically
separate receive register.
The serial port can operatein4 modes (one synchronous
mode, three asynchronous modes). The baud rate clock
for the serial port is derived from the oscillator frequency
(mode0,2)or generated eitherby timer1orby dedicated
baud rate generator (mode 1, 3).
Mode 0 Shift Register (Synchronous) Mode:
Serial data enters and exits through RxD. TxD
outputs the shift clock. 8 bits are transmitted/
received (LSB first). The baud rateis fixed1⁄6 the
oscillator frequency.
Mode 1 8-bit UART, Variable Baud Rate: bits are transmitted (through TxD)or received
(through RxD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit
goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Mode 2 9-bit UART, Fixed Baud Rate: bits are transmitted (through TxD)or received
(through RxD): startbit (0),8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1). Transmit, the9th databit (TB8in SCON) can assigned the valueof0or1. Or,for example,
the paritybit(P,in the PSW) couldbe moved into
TB8. On receive, the9th databit goes into RB8in
Special Function Register SCON, while the stop
bit ignored. The baud rate is programmable to
either1 ⁄16 or1 ⁄32 the oscillator frequency.
Mode 3 9-bit UART, Variable Baud Rate: bits are transmitted (through TxD)or received
(through RxD): startbit (0),8 data bits (LSB first), programmable9th data bit, anda stopbit (1).In
fact, Mode3 isthesameas Mode2inall respects
except baud rate. The baud rate in Mode 3 is
variable.
In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Receptionis initiatedin Mode0by the conditionRI=0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
14.1 Multiprocessor Communications
Modes2 and3 havea special provisionfor multiprocessor
communications. Inthese modes,9 data bits are received.
The 9th one goes into RB8. Then comes a stop bit. The
port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if
RB8 = 1. This feature is enabled by setting bit SM2 in
SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first send out an address
byte which indentifies the target slave. An address byte
differs froma data bytein that the9thbitis1inan address
byte and 0 in a data byte. With SM2 = 1, no slave will be
interruptedbya data byte.An address byte, however, will
interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The
addressed slave will clear its SM2 bit and prepare to
receive the data bytes that willbe coming. The slaves that
weren’t being addressed leave their SM2s set and go on
about their business, ignoring the coming data bytes.
SM2 hasno effectin Mode0, andin Mode1 canbe used check the validityof the stop bit.Ina Mode1 reception, SM2=1, the receive interrupt will notbe activated unless
a valid stop bit is received.
14.2 Serial Port Control Register
The serial port control and status register is the Special
Function Register SCON, shown in Table 38, 40 and 41.
This register contains not only the mode selection bits, but
also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
S0BUF is the receive and transmit buffer of serial
interface. Writingto S0BUF loads the transmit register and
initiates transmission. Reading out S0BUF accesses a
physically separate receive register.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
14.3 Baud Rate Generation
There are several possibilities to generate the baud rate
clockfor the serial port dependingon the modein whichit
is operating.
For clarification some terms regarding the difference
between “baud rate clock” and “baud rate” should be
mentioned. The serial interface requiresa clock rate which
is 16 times the baud rate for internal synchronization.
Therefore, the baud rate generators have to provide a
“baud rate clock” to the serial interface which - there
dividedby16- resultsin the actual “baud rate”. However,
all formulas given in the following section already include
the factor and calculate the final baud rate. Further, the
abbreviation fCLK refers to the external clock frequency
(oscillator or external input clock operation).
The baud rateof the serial portis controlledby the two bits
SPS and SMOD1 which are located in the Special
Function Registers S0PSH and PCON. In SFRs S0PSH
and S0PSL the prescaler load value of the internal baud
rate generator can be programmed (see Table 38 to 43).
14.3.1 INTERNAL BAUD RATE GENERATOR PRESCALER S0PSH, S0PSL
Table 38 Internal Baud Rate Generator Prescaler Low Register S0PSL (address FAH)
Prescaler load value
Table 39 Description of S0PSL bits
Table 40 Internal Baud Rate Generator Prescaler High Register S0PSH (address FBH)
Prescaler higher nibble load value
Table 41 Description of S0PSH bits
14.3.2 PCON FOR THE INTERNAL BAUD RATE GENERATOR
Table 42 PCON (address 87H)
Prescaler load value
Table 43 Description of SMOD1 and SMOD0 bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
14.3.3 BAUD RATE GENERATION OVERVIEW OF OPTIONS
Dependingon the programmed operating mode different paths are selectedfor the baud rate clock generation. Figure23
shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which
is selected in the Special Function Register SCON:
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
14.3.4 BAUD RATEIN MODE0
The baud rate in Mode 0 is fixed to:
14.3.5 BAUD RATEIN MODE2
The baud rate in Mode 2 depends on the value of bit
SMOD1in Special Function Register PCON.If SMOD1=
0 (which is the value after reset), the baud rate is1 ⁄32 of
oscillator frequency.If SMOD1=1, the baud rateis1⁄16of
the oscillator frequency:
14.3.6 BAUD RATEIN MODE1 AND3
In these modes the baud rate is variable and can be
generated alternatively by a baud rate generator or by
Timer 1.
Mode 0 baud rate oscillator frequency -------------------------------------------------------=
Mode 2 baud rate 2 SMOD1-------------------- oscillator frequency×=
14.3.7 USING THE INTERNAL BAUD RATE GENERATOR Modes1 and3, the P8xC591 can usean internal baud
rate generatorfor the serial port.To enable this feature,bit
SPS (bit 7 of Special Function Register S0PSH) must be
set. Bit SMOD1 (PCON.7) controls a divide-by-2 circuit
which affect the input and output clock signal of the baud
rate generator. After reset the divide-by-2 circuit is active
and the resulting overflow output clock willbe dividedby2.
The input clock of the baud rate generator is fCLK.
The baud rate generator consists of its own free running
upward counting 12-bit timer. On overflow of this timer
(next count step after counter value FFFH) there is an
automatic 12-bit reload from the registers S0PSL and
S0PSH. The lower 8 bits of the timer are reloaded from
S0PSL, while the upper four bits are reloaded frombit0to
3 of register S0PSH. The baud rate timer is reloaded by
writing to S0PSH.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
With the baud rate generatoras clock sourcefor the serial
port in Mode 1 and Mode 3, the baud rate of can be
determined as follows:
Mode 1, 3 baud rate =
Baud rate generator overflow rate =12 - S0PS with S0PS = S0PSH.3 - 0, S0PSL.7 - 0.
S0PS: Baud Rate Generator Prescaler load value
Table 47 lists baud rates and how they can be obtained
from the Internal Baud Rate Generator.
14.3.8 USING TIMER1TO GENERATE BAUD RATES Mode1 and3of the serial port also timer1 canbe used
for generating baud rates. Then the baud rate is
determined by the timer 1 overflow rate and the value of
SMOD1 as follows: SMOD1 osciillator frequency× (baud rate generator overflow rate)× ---------------------------------------------------------------------------------------------------------
The Timer1 interruptis usually disabledin this application.
Timer 1 itself can be configured for either “timer” or
“counter” operation, and in any of its operating modes. In
most typical applications, it is configured for “timer”
operation in the auto-reload (high nibble of TMOD =
0010B).In this case the baud rateis givenby the formula:
Very low baud rates can be achieved with Timer 1 if
leaving theTimer 1interrupt enabled, configuring the timer runas 16-bit timer (high nibbleof TMOD= 0001B), and
using the Timer 1 interrupt for a 16-bit software reload.
Table 49 lists lower baud rates and how they can be
obtained from Timer1.
Mode 1, 3 baud rate 2 SMOD1-------------------- (timer 1 overflow rate)×=
Mode1 3 baud rate =2 SMOD1 oscillator frequency× 6 256 TH1()– ()×× -------------------------------------------------------------------------------,
Table 44 Serial Port Control Register SCON (address)
Table 45 Description of S0PSH and S0PSL bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Table 46 Serial port mode select
Table 47 Internal baud rate timer generated baud rates
Table 48 Timer 1 generated baud rates
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
14.4 More about UART Modes
More About Mode 0
Serial data enters and exits through RxD. TxD outputs the
shift clock.8 bitsare transmitted/received:8 data bits (LSB
first). The baud rate is fixed a1 ⁄6 the oscillator frequency.
Figure 25 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to
commencea transmission. The internal timingis such that
one full machine cycle will elapse between “write to
S0BUF” and activation of SEND.
SEND enables the output of the shift register to the
alternate output function line of P3.0 and also enable
SHIFT CLOCKto the alternate output function lineof P3.1.
SHIFT CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6,S1 and S2.At S6P2of
every machine cyclein which SENDis active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the
left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9th position, is just to the left of the MSB,
and all positions to the left of that contain zeros. This
condition flags theTX Control blocktodo one last shift and
then deactivate SEND and set T1. Both of these actions
occur at S1P1 of the 10th machine cycle after “write to
S0BUF”.
Reception is initiated by the condition REN= 1 and=0.At S6P2of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register,
and in the next clock phase activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1of every machine cycle.At S6P2of every
machine cycle. At S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift
register are shiftedto the left one position. The value that
comes in from the right is the value that was sampled at
the P3.0 pin at S5P2 of the same machine cycle. data bits comein from the right,1s shift outto the left.
When the 0 that was initially loaded into the weightiness
position arrivesat the left most positionin the shift register,
it flags the RX Control block to do one last shift and load
S0BUF. At S1P1 of the 10th machine cycle after the write SCON that clearedRI, RECEIVEis clearedasRIis set.
More About Mode 1
Ten bits are transmitted (through TxD), or received
(through RxD):a startbit (0),8 data bits (LSB first), anda
stop bit (1). On receive, the stop bit goes into RB8 in
SCON. In the 80C51 the baud rate is determined by the
Timer 1 overflow rate.
Figure 25 shows a simplified functional diagram of the
serial port in Mode1, and associated timings for transmit
receive.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal also loadsa1 into the9thbit positionof the transmit
shift register and flags the TX Control unit that a
transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the
next rollover in the divide-by-16 counter. (Thus, the bit
times are synchronizedto the divide-by-16 counter, notto
the “write to S0BUF” signal.)
The transmission begins with activation of SEND which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the outputbitof the transmit shift
register to TxD. The first shift pulse occurs one bit time
after that. data bits shift outto the right, zeros are clockedin from
the left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain zeros. The
condition flags theTX Control unittodo one last shift and
then deactivate SEND and set TI. This occurs at the 10th
divide-by-16 rollover after “write to S0BUF”.
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxDis sampledata rateof16 times
whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and1 FFHis written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The16 statesof the counter divide eachbit time into16ths.
At the 7th, 8th , and 9th counter states of each bit time, the
bit detector samples the valueof RxD. The value accepted
is the value that was seen in at least 2 of the 3 samples.
This is done for noise rejection. If the value accepted
during the first bit time is not 0, the receive circuits are
reset and the unit goes back to looking for another 1-to-0
transition. This is to provide rejection of false start bits. If
the start bit proves valid, it shifted into the input shift
register, and receptionof the restof the frame will proceed.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591 data bits comein from the right,1s shift outto the left.
When the start bit arrives at the left most position in the
shift register (which in Mode 1 is a 9-bit register), it flags
the RX Control blocktodo one last shift, load S0BUF and
RB8, and setRI. The signalto load S0BUF and RB8, and
to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is
generated: RI = 0, and Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stopbit goes into RB8, the8 data bitsgo into S0BUF, andis activated.At this time, whether the above conditions
are met or not, the unit goes back to looking for a 1-to-0
transition in RxD.
More About Modes 2 and 3
Eleven bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable9th data bit, anda stopbit (1). On transmit,
the9th databit (TB8) canbe assigned the valuesof0or1. receive, the9the databit goes into RB8in SCON. The
baud rate is programmable to either1 ⁄16 or1 ⁄32 the
oscillator frequency in Mode 2. Mode 3 may have a
variable baud rate generated from Timer 1.
Figure 25 show a functional diagram of the serial port in
Modes2 and3. The receive portionis exactly the sameas Mode1. The transmit portion differs from Mode1 onlyin
the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal also loads TB8 into the9thbit positionof the transmit
shift register and flags the TX Control unit that a
transmission is requested. Transmission commences at
S1P1of the machine cycle following the nextrolloverin the
divide-by-16 counter. (Thus, the bit times are
synchronizedto the divide-by-16 counter, notto the “write
to SUB” signal).
The transmission begins with activation of SEND, which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the outputbitof the transmit shift
register to TxD. The first shift pulse occurs one bit time
after that. The first shift clocksa1 (the stop bit) into the9th
bit positionof the shift register. Thereafter, only zeros are
clockedin. Thus,as databit shift outto the right, zeros are
clockedin from the left. When TB8isat the output position
of the shift register, then the stop bit is just to the left of
TB8, and all positions to the left of that contain zeros.
This condition flags theTX Control unittodo one last shift
and then deactivate SEND and set TI. This occurs at the
11th divide-by-16 rollover after “write to SUBF”.
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxDis sampledata rateof16 times
whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written to the input shift
register.
At the 7th, 8th , and 9th counter states of each bit time, the
bit detector samples the valueof R-D. The value accepted the value that was seeninat least2of the3 samples.If
the value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes backto looking
for another 1-to-0 transition. If the start bit proves valid, it
is shifted into the input shift register, and reception of the
rest of the frame will proceed. data bits comein from the right,1s shift outto the left.
When the start bit arrives at the left most position in the
shift register (whichin Modes2 and3isa 9-bit register),it
flags the RX Control blocktodo one last shift, load S0BUF
and RB8, and set RI.
The signal to load S0BUF and RB8, and to set RI, will be
generated if, and only if, the following conditions are met
at the time the final shift pulse is generated. RI = 0, and Either SM2 = 0, or the received 9th data bit = 1. eitherof these conditionsis not met, the received frame irretrievably lost, andRIis not set.If both conditions are
met, the received9th databit goes into RB8, and the first8
data bits go into S0BUF. One bit time later, whether the
above conditions were met or not, the unit goes back to
looking for a 1-to-0 transition at the RxD input.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
14.5 Enhanced UART
The UART operates in all of the usual modes that are
described in the Section of Standard Serial Interface,
80C51-Based 8-Bit Microcontrollers.In addition the UART
can perform framing error detect by looking for missing
stop bits, and automatic address recognition. The UART
also fully supports multiprocessor communicationas does
the standard 80C51 UART.
When used for framing error detect the UART looks for
missing stop bits in the communication. A missing bit will
set theFEbitin the S0CON register. TheFEbit shares the
S0CON.7 bit with SM0 and the function of S0CON.7 is
determined byPCON.6 (SMOD0)see Table 50.If SMOD0 set then S0CON.7 functionsas FE. S0CON.7 functions
as SM0 when SMOD0 is cleared. When as FE S0CON.7
can only be cleared by software. Refer to Figure 25.
14.5.1 AUTOMATIC ADDRESS RECOGNITION
Automatic Address Recognition is a feature which allows
the UART to recognize certain addresses in the serial bit
streamby using hardwareto make the comparisons. This
feature saves a great deal of software overhead by
eliminating the need for the software to examine every
serial address which passes bythe serial port. This feature
is enabled by setting the SM2 bit in S0CON. In the 9 bit
UART modes, mode2 and mode3, the Receive Interrupt
flag (RI) will be automatically set when the received byte
contains either the “Given” address or the “Broadcast”
address. The 9 bit mode requires that the 9th information
bit is a 1 to indicate that the received information is an
address and not data. Automatic address recognition is
shown in Figure 29.
The 8 bit mode is called Mode 1. In this mode the RI flag
willbe setif SM2is enabled and the information received
has a valid stop bit following the 8 address bits and the
information is either a Given or Broadcast address.
14.5.2 SERIAL PORT CONTROL REGISTER (S0CON)
Table 49 Serial Port Control Register (address 98H)
Table 50 Description of S0CON bits
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allowsa
master to selectively communicate with one or more
slavesby invoking the Given slave addressor addresses.
Allof the slaves maybe contactedby using the Broadcast
address. All of the slaves may be contacted by using the
Broadcast address. Two Special Function Registers are
used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which
bitsin the SADDR aretobe used and which bits are “don’t
care”. The SADEN mask canbe logically ANDed with the
SADDR to create the “Given” address which the master
willusefor addressingeach oftheslaves. Useof the Given
address allows multiple slaves to be recognized while
excluding others. The following examples will helpto show
the versatility of this scheme:
Slave 0 SADDR= 1100 0000
SADEN= 1111 1101
Given = 1100 00X0
Slave 1 SADDR= 1100 0000
SADEN= 1111 1110
Given = 1100 000X the above example SADDRis the same and the SADEN
datais usedto differentiate between the two salves. Slave requiresas0inbit0 andit ignoresbit1. Slave1 requires0inbit1 andbit0is ignored.A unique addressfor Slave wouldbe 1100 0010 since slave1 requiresa0inbit1.A
unique addressfor Slave1 wouldbe 1100 0001 sincea1bit0 will exclude slave0. Both slaves canbe selectedat
the same timebyan address which hasbit0=0 (for Slave
0) and bit 1 = 0 (for Slave 1). Thus, both could be
addressed with 1100 0000.
In a more complex system the following could be used to
select Slaves 1 and 2 while excluding Slave 0:
Slave 0 SADDR= 1100 0000
SADEN= 1111 1001
Given = 1100 0XX0
Slave 1 SADDR= 1110 0000
SADEN= 1111 1010
Given = 1110 0X0X
Slave 2 SADDR= 1110 0000
SADEN= 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3
Slavesisin the lower3 address bits. Slave0 requires that
bit 0 = 0 and it can be uniquely addressed by 1110 0110.
Slave 1 requires that bit 1 = 0 and it can be uniquely
addressedby 1110 and 0101. Slave2 requires thatbit2= andits unique addressis 1110 0011.To select Slaves0
and1 and exclude Slave2 use address 1110 0100, since
it is necessary to make bit 2 = 1 to exclude Slave2.
The Broadcast Addressfor each slaveis createdby taking
the logical ORof SADDR and SADEN. Zerosin this result
are trendedas don’t cares.In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF
hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN
(SFR address 0B9H) are leaded with 0s. This producesa
given address of all “don’t cares” as well as a Broadcast
address of all “don’t cares”. This effectively disables the
Automatic Addressing mode and allows the
microcontrollerto use standard 80C51 type UART drivers
which do not make use of this feature. SIO1, I2 C SERIAL IO
The I2 C bus uses two wires (SDA and SCL) to transfer
information between devices connected to the bus. The
main features of the bus are: Bidirectional data transfer between masters and slaves Multimaster bus (no central master) Arbitration between simultaneously transmitting
masters without corruption of serial data on the bus Serial clock synchronization allows devices with
different bit rates to communicate via one serial bus Serial clock synchronization can be used as a
handshake mechanism to suspend and resume serial
transfer The I2 C bus may be used for test and diagnostic
purposes
The I/O pins P1.6 and P1.7 must be set to Open Drain
(SCL and SDA).
The 8xC591 on-chip I2 C logic provides a serial interface
that meets the I2 C bus specification. The SIO1 logic
handles bytes transfer autonomously. It also keeps track
of serial transfers, and a status register (S1STA) reflects
the status of SIO1 and the I2 C bus.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
The CPU interfaces to the I2 C logic via the following four
special function registers: S1CON (SIO1 control register),
S1STA (SIO1 status register), S1DAT (SIO1 data
register), and S1ADR (SIO1 slave address register). The
SIO1 logic interfacesto the externalI2C busvia two port1
pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial
data line). typicalI2C bus configurationis shownin Figure 30, and
Figure 31 shows how a data transfer is accomplished on
the bus. Dependingon the stateof the directionbit (R/W),
two types of data transfers are possible on the I2 C bus: Data transfer from a master transmitter to a slave
receiver. The first byte transmittedby the masteris the
slave address. Next follows a number of data bytes.
The slave returns an acknowledge bit after each
received byte. Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an
acknowledge bit. Next follows the data bytes
transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte.At the endof the last received
byte, a not acknowledge is returned.
The master device generatesallof the serial clock pulses
and the START and STOP conditions.A transferis ended
with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the
beginningof the next serial transfer, theI2C bus will notbe
released.
15.1 Modes of Operation
The on-chip SIO1 logic may operate in the following four
modes: Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL
outputs the serial clock. The first byte transmitted
contains the slave address of the receiving device (7
bits) and the data direction bit. In this case the data
direction bit(R/W) will belogic 0,andwe say that a“W”
is transmitted. Thus the first byte transmitted is
SLA+W. Serial datais transmitted8 bits atatime. After
each byte is transmitted, an acknowledge bit is
received. START and STOP conditions are output to
indicate the beginning and the endofa serial transfer. Master Receiver Mode:
Thefirstbyte transmitted contains the slave addressof
the transmitting device (7 bits) and the data direction
bit.In this case the data directionbit (R/W) willbe logic and we say thatan “R”is transmitted. Thus the first
byte transmittedis SLA+R. Serial datais receivedvia
P1.7/SDA while P1.6/SCL outputs the serial clock.
Serial datais received8 bitsata time. After each byte received,an acknowledgebitis transmitted. START
and STOP conditions are output to indicate the
beginning and end of a serial transfer. Slave Receiver Mode:
Serial data and the serial clock are received through
P1.7/SDA and P1.6/SCL. After each byteis received, acknowledgebitis transmitted. START and STOP
conditions are recognizedas the beginning and endof
a serial transfer. Address recognition is performed by
hardware after reception of the slave address and
direction bit. Slave Transmitter Mode:
The first byte is received and handled as in the slave
receiver mode. However,in this mode, the directionbit
will indicate that the transfer direction is reversed.
Serial datais transmittedvia P1.7/SDA while the serial
clock is input through P1.6/SCL. START and STOP
conditions are recognizedas the beginning and endof
a serial transfer.a given application, SIO1 may operateasa master anda slave.In the slave mode, the SIO1 hardware looksfor
its own slave address and the general call address.If one
of these addresses is detected, an interrupt is requested.
When the microcontroller wishes to become the bus
master, the hardware waits until the busis free before the
master mode is entered so that a possible slave action is
not interrupted.If bus arbitrationis lostin the master mode,
SIO1 switches to the slave mode immediately and can
detect its own slave address in the same serial transfer.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
15.2 SIO1 Implementation and Operation
Figure 32 shows how the on-chip I2C bus interface is
implemented, and the following text describes the
individual blocks.
15.2.1 INPUT FILTERS AND OUTPUT STAGES
The input filters have I2C compatible input levels. If the
input voltage is less than 1.5 V, the input logic level is
interpreted as 0; if the input voltage is greater than 3.0V,
the input logic level is interpreted as 1. Input signals are
synchronized with the internal clock (fCLK/4), and spikes
shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that
can sink3 mAat VOUT< 0.4V. These open drain outputs
do have clamping diodes to VDD. Thus, precautions havebe considered,ifa powered-down 8xC591on oneboard
clamps the I2 C bus externally.
15.2.2 ADDRESS REGISTER, S1ADR
This 8-bit special function register maybe loaded with the
7-bit slave address(7 most significant bits)to which SIO1
will respond when programmed as a slave transmitter or
receiver. The LSB (GC) is used to enable general call
address (00H) recognition.
15.2.3 COMPARATOR
The comparator compares the received 7-bit slave
address withits own slave address(7 most significant bits
in S1ADR). It also compares the first received 8-bit byte
with the general call address (00H).Ifan equalityis found,
the appropriate status bits are set and an interrupt is
requested.
15.2.4 SHIFT REGISTER, S1DAT
This 8-bit special function register containsa byteof serial
data to be transmitted or a byte which has just been
received. Datain S1DATis always shifted from rightto left;
the firstbittobe transmittedis the MSB (bit7) and, aftera
byte has been received, the first bit of received data is
locatedat the MSBof S1DAT. While datais being shifted
out, data on the bus is simultaneously being shifted in;
S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from
master transmitter to slave receiver is made with the
correct data in S1DAT.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
15.2.5 ARBITRATION AND SYNCHRONIZATION LOGIC the master transmitter mode, the arbitration logicchecks
that every transmitted logic1 actually appearsasa logic1
on the I2 C bus. If another device on the bus overrules a
logic 1 and pulls the SDA line low, arbitration is lost, and
SIO1 immediately changes from master transmitter to
slave receiver. SIO1 will continue to output clock pulses
(on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode.
Lossof arbitrationin this mode can only occur while SIO1
is returning a not acknowledge: (logic 1) to the bus.
Arbitrationis lost when anotherdeviceon the buspulls this
signal LOW. Since this can occur onlyat the endofa serial
byte, SIO1 generates no further clock pulses. Figure33
shows the arbitration procedure.
The synchronization logic will synchronize the serial clock
generator with the clock pulses on the SCL line from
another device. If two or more master devices generate
clock pulses, the mark duration is determined by the
device that generates the shortest marks, and the space
duration is determined by the device that generates the
longest spaces. Figure 34 shows the synchronization
procedure.
A slave may stretch the space duration to slow down the
bus master. The space duration may alsobe stretchedfor
handshaking purposes. This canbe done after eachbitor
after a complete byte transfer. SIO1 will stretch the SCL
space duration after a byte has been transmitted or
received and the acknowledge bit has been transferred.
The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
15.2.6 SERIAL CLOCK GENERATOR
This programmable clock pulse generator provides the
SCL clock pulses when SIO1 is in the master transmitter master receiver mode.Itis switchedoff when SIO1isin
a slave mode. The programmable output clock
frequencies are: fCLK/120, fCLK/9600, and the Timer 1
overflow rate divided by eight. The output clock pulses
have a 50% duty cycle unless the clock generator is
synchronized with other SCL clock sources as described
above.
15.2.7 TIMING AND CONTROL
The timing and control logic generates the timing and
control signals for serial byte handling. This logic block
provides the shift pulses for S1DAT, enables the
comparator, generates and detects start and stop
conditions, receives and transmits acknowledge bits,
controls the master and slave modes, contains interrupt
request logic, and monitors the I2 C bus status.
15.2.8 CONTROL REGISTER, S1CON
This 7-bit special function register is used by the
microcontroller to control the following SIO1 functions:
start and restartofa serial transfer, terminationofa serial
transfer, bit rate, address recognition, and
acknowledgment.
15.2.9 STATUS DECODER AND STATUS REGISTER
The status decoder takesallof the internal status bits and
compresses them intoa 5-bit code. This codeis uniquefor
each I2C bus status. The 5-bit code may be used to
generate vector addresses for fast processing of the
various service routines. Each service routine processesa
particularbus status.There are26 possible bus states ifall
four modes of SIO1 are used. The 5-bit status code is
latched into the five most significant bits of the status
register when the serial interrupt flagis set (by hardware)
and remains stable until the interrupt flag is cleared by
software. The three least significant bits of the status
register are always zero. If the status code is used as a
vectorto service routines, then the routines are displaced eight address locations. Eight bytesof codeis sufficient
for mostof the service routines (see the software example
in this section).
15.2.10 THE FOUR SIO1 SPECIAL FUNCTION REGISTERS
The microcontroller interfaces to SIO1 via four special
function registers. These four SFRs (S1ADR, S1DAT,
S1CON, and S1STA) are described individually in the
following sections.
Philips Semiconductors Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller P8xC591
15.2.10.1 The Address Register, S1ADR
The CPU can read from and write to this 8-bit, directly
addressable SFR. S1ADR is not affected by the SIO1
hardware. The contentsof this register are irrelevant when
SIO1 is in a master mode. In the slave modes, the seven
most significant bits must be loaded with the
microcontrollers own slave address, and, if the least
significant bit is set, the general call address (00H) is
recognized; otherwise it is ignored.
The most significantbit corresponds tothefirstbit received
from theI2C bus aftera start condition.A logic1in S1ADR
corresponds to a high level on the I2 C bus, and a logic 0
corresponds to a low level on the bus.
Table 51 Address Register S1ADR (address DBH)
Table 52 Description of S1ADR (DBH) bits
15.2.11 THE DATA REGISTER, S1DAT
S1DAT contains a byte of serial data to be transmitted or
a byte which has just been received. The CPU can read
from and writeto this 8-bit, directly addressable SFR whileis notin the processof shiftinga byte. This occurs when
SIO1isina defined state and the serial interruptflagis set.
Datain S1DAT remains stableas longasSIis set. Datain
S1DATis always shifted from rightto left: the firstbittobe
transmitted is the MSB (bit 7), and, after a byte has been
received, the firstbitof received datais locatedat the MSB S1DAT. While datais being shifted out, dataon the bus simultaneously being shiftedin; S1DAT always contains
the last data byte presenton the bus. Thus,in the eventof
lost arbitration, the transition from master transmitter to
slave receiver is made with the correct data in S1DAT.
S1DAT and the ACK flag form a 9-bit shift register which
shifts in or shifts out an 8-bit byte, followed by an
acknowledge bit. The ACK flag is controlled by the SIO1
hardware and cannotbe accessedby the CPU. Serial data
is shifted through the ACK flag into S1DAT on the rising
edgesof serial clock pulseson the SCL line. Whena byte
has been shifted into S1DAT, the serial datais availablein
S1DAT, and the acknowledgebitis returnedby the control
logic during the ninth clock pulse. Serial datais shifted out
from S1DAT via a buffer (BSD7) on the falling edges of
clock pulses on the SCL line.
When the CPU writesto S1DAT, BSD7is loaded with the
contentof S1DAT.7, whichis the firstbittobe transmitted
to the SDA line (see Figure 36). After nine serial clock
pulses, the eight bitsin S1DAT will have been transmitted the SDA line, and the acknowledgebit willbe presentin
ACK. Note that the eight transmitted bits are shifted back
into S1DAT.
Table 53 Address Register S1DAT (address DAH)
Table 54 Description of S1DAT (DAH) bits
