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P87C557E8EFB
8-bit microcontroller
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
CONTENTS FEATURES GENERAL DESCRIPTION
2.1 Electromagnetic Compatibility (EMC)
2.2 Recommendation on ALE ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION
6.1 Pinning diagram
6.2 Pin description FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION
8.1 Program Memory
8.2 Internal Data Memory
8.3 Addressing I/O FACILITIES PULSE WIDTH MODULATED OUTPUTS
(PWM)
10.1 Prescaler Frequency Control Register (PWMP)
10.2 Pulse Width Register 0 (PWM0)
10.3 Pulse Width Register 1 (PWM1) ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1 ADC features
11.2 ADC functional description
11.3 ADC timing
11.4 ADC configuration and operation
11.5 ADC during Idle and Power-down mode
11.6 ADC resolution and characteristics
11.7 ADC after reset
11.8 ADC Special Function Registers TIMERS/COUNTERS
12.1 Timer 0 and Timer1
12.2 Timer T2
12.3 Watchdog Timer T3 SERIAL I/O PORTS
13.1 Serial I/O Port: SIO0 (UART)
13.2 Serial I/O Port: SIO1 (I2 C-bus interface) INTERRUPT SYSTEM
14.1 Interrupt Enable Registers
14.2 Interrupt Handling
14.3 Interrupt Priority Structure
14.4 Interrupt vectors
14.5 Interrupt Enable and Priority Registers POWER REDUCTION MODES
15.1 Idle mode
15.2 Power-down mode
15.3 Wake-up from Power-down mode
15.4 Status of external pins
15.5 Power Control Register (PCON) OSCILLATOR CIRCUITS
16.1 XTAL1; XTAL2 oscillator: standard 80C51
16.2 XTAL3; XTAL4 oscillator: 32 kHz PLL oscillator
(with Seconds timer) RESET CIRCUITRY
17.1 Power-on Reset INSTRUCTION SET
18.1 Addressing modes
18.2 80C51 family instruction set
18.3 Instruction set description LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS EPROM CHARACTERISTICS
22.1 Programming and verification
22.2 Security SPECIAL FUNCTION REGISTERS
OVERVIEW PACKAGE OUTLINES SOLDERING
25.1 Introduction
25.2 Reflow soldering
25.3 Wave soldering
25.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
FEATURES 80C51 Central Processing Unit (CPU) 64 kbytes ROM (only P83C557E8) 64 kbytes EPROM (only P87C557E8) ROM/EPROM Code protection 2048 bytes RAM, expandable externally to 64 kbytes Two standard 16-bit timers/counters An additional 16-bit timer/counter coupled to four
capture registers and three compare registers A 10-bit Analog-to-Digital Converter (ADC) with eight
multiplexed analog inputs and programmable autoscan Two 8-bit resolution, Pulse Width Modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with
analog inputsI2 C-bus serial I/O port with byte oriented master and
slave functions Full-duplex UART compatible with the standard 80C51 On-chip Watchdog Timer 15 interrupt sources with 2 priority levels (2to6 external
sources possible) Phase-Locked Loop (PLL) oscillator with 32 kHz
reference and software-selectable system clock
frequency Seconds timer Software enable/disable of ALE output pulse Electromagnetic compatibility improvements Wake-up from Power-down by external or seconds
interrupt Frequency range for 80C51-family standard oscillator:
3.5to16 MHz Extended temperature range: −40to +85C Supply voltage: 4.5to 5.5 V.
GENERAL DESCRIPTIONThe 8-bit microcontrollers P80C557E8, P83C557E8 and
P87C557E8 - hereafter referred to as P8xC557E8 - are
manufactured in an advanced CMOS process and are
derivatives of the 80C51 microcontroller family.
The P8xC557E8 contains a volatile 2048 bytes read/write
Data Memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the
80C51), an additional 16-bit timer coupled to capture and
compare latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC, a dual
Digital-to-Analog Convertor (DAC), Pulse Width
Modulated interface, two serial interfaces (UART and2 C-bus), a Watchdog Timer, an on-chip oscillator and
timing circuits.
The P8xC557E8 is available in 3 versions: P80C557E8: ROMless version P83C557E8: containing a non-volatile 64 kbytes mask
programmable ROM P87C557E8: containing 64 kbytes programmable
EPROM/OTP.
The P8xC557E8 is a control-oriented CPU with on-chip
Program and Data Memory; it cannot be extended with
external Program Memory. It can access up to 64 kbytes
of external Data Memory. For systems requiring extra
capability, the P8xC557E8 can be expanded using
standard TTL compatible memories and peripherals.
In addition, the P8xC557E8 has two software selectable
reduced power modes: Idle mode and Power-down mode.
The Idle mode freezes the CPU while allowing the RAM,
timers, serial ports, and interrupt system to continue
functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip
functions to be inoperative.The Power-down mode can be
terminated by an external reset, by the seconds interrupt
and by any one of the two external interrupts;
see Section 15.3.
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic as well
as bit-handling capabilities. The instruction set of the
P8xC557E8 is the same as the 80C51 and consists of over
100 instructions: 49 one-byte, 45 two-byte, and three-byte. With a 16 MHz system clock, 58% of the
instructions are executed in 0.75 μs and 40% in 1.5 μs.
Multiply and divide instructions require 3 μs.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
2.1 Electromagnetic Compatibility (EMC)Primary attention is paid to the reduction of
electromagnetic emission of the microcontroller
P8xC557E8. The following features reduce the
electromagnetic emission and additionally improve the
electromagnetic susceptibility: Four digital part supply voltage pins (VDD1to VDD4) and
four digital ground pins (VSS1to VSS4) are placed as
pairs of VDDn and VSSn at two adjacent pins, at each side
of the package. Separated VDD pins for the internal logic and the port
buffers. Internal decoupling capacitance improves the EMC
radiation behaviour and the EMC immunity. External capacitors should be connected across
associated VDDn and VSSn pins (i.e. VDD1 and VSS1).
Lead length should be as short as possible. Ceramic
chip capacitors are recommended (100 nF).
2.2 Recommendation on ALEFor applications that require no external memory or
temporarily no external memory: the ALE output signal
(pulses at a frequency of1⁄6× fOSC) can be disabled under
software control (bit RFI; SFR: PCON.5); if disabled, no
ALE pulse will occur. ALE pin will be pulled down
internally, switching an external address latch to a quiet
state. The MOVX instruction will still toggle ALE (external
Data Memory is accessed). ALE will retain its normal HIGH
value during Idle mode and a LOW value during
Power-down mode while in the ‘RFI reduction mode’.
Additionally during internal access (EA= 1) ALE will toggle
normally when the address exceeds the internal Program
Memory size. During external access (EA= 0) ALE will
always toggle normally, whether the flag ‘RFI’ is set or not.
ORDERING INFORMATION
Notes ROMless type. ROM coded type; ‘nnn’ denotes the ROM code number. EPROM/OTP type.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
BLOCK DIAGRAM
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
FUNCTIONAL DIAGRAM
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 PINNING INFORMATION
6.1 Pinning diagram
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
6.2 Pin description
Table 1 Pin description for QFP80 (SOT318-2)
To avoid a ‘latch-up’ effect at power-on: VSS− 0.5V < ‘voltage at any pin at any time’< VDD+ 0.5V.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 FUNCTIONAL DESCRIPTION
The P8xC557E8 is a stand-alone high-performance
microcontroller designed for use in real time applications
such as instrumentation, industrial control, medium to
high-end consumer applications and specific automotive
control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xC557E8 is a control-oriented CPU with on-chip
program and Data Memory, but it cannot be extended with
external Program Memory. It can access up to 64 kbytes
of external Data Memory. For systems requiring extra
capability, the P8xC557E8 can be expanded using
standard memories and peripherals.
The functional description of the device is described in:
Chapter 8 “Memory organization”
Chapter 9 “I/O facilities”
Chapter 10 “Pulse Width Modulated outputs”
Chapter 11 “Analog-to-Digital Converter (ADC)”
Chapter 12 “Timers/counters”
Chapter 13 “Serial I/O ports”
Chapter 14 “Interrupt system”
Chapter 15 “Reduced power modes”
Chapter 16 “Oscillator circuits”
Chapter 17 “Reset circuitry”.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbytes external
Data Memory, 2048 bytes internal Data Memory
(consisting of 256 bytes standard RAM and 1792 bytes
AUX-RAM) and the 64 kbytes internal or 64 kbytes
external Program Memory (see Fig.4).
8.1 Program Memory
The Program Memory of the P8xC557E8 consists of kbytes ROM or 64 kbytes EPROM. If, during reset, the
EA pin was held HIGH, the P8xC557E8 always executes
out of the internal Program Memory. If the EA pin was held
LOW during reset the P8xC557E8 fetches all instructions
from the external Program Memory. The EA input is
latched during reset and is don’t care after reset.
The internal Program Memory content is protected by
setting a mask programmable security bit (ROM) or by the
software programmable security bits (EPROM)
respectively, i.e. it cannot be read out at any time by any
test mode or by any instruction in the external Program
Memory space. The MOVC instructions are the only ones
which have access to program code in the internal or
external Program Memory. The EA input is latched during
reset and is don’t care after reset. This implementation
prevents from reading internal program code by switching
from external Program Memory to internal Program
Memory during MOVC instruction or an instruction that
handles immediate data. Table 2 lists the access to the
internal and external Program Memory with MOVC
instructions whether the security feature has been
activated or not.
Due to the maximum size of the internal Program Memory,
the MOVC instructions can always operate either in the
internal or in the external Program Memory.
Table 2 Memory access by the MOVC instruction
For code protection of the P87C557E8 see Section 23.2.
Note Not applicable due to 64 kbytes internal Program
Memory.
8.2 Internal Data Memory
The internal Data Memory is divided into three physically
separated parts: 256 bytes of RAM, 1792 bytes of
AUX-RAM, and a 128 bytes Special Function Registers
(SFRs) area. These parts can be addressed each in a
different way as described in Sections 8.2.1to 8.2.2 and
Table3.
Table 3 Internal Data Memory map
8.2.1 RAM RAM 0to 127 can be addressed directly and indirectly
as in the 80C51. Address pointers are R0 and R1 of the
selected register bank. RAM 128to 255 can only be addressed indirectly.
Address pointers are R0 and R1 of the selected register
bank.
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations. The stack can be located anywhere in the
internal 256 bytes RAM. The stack depth is only limited by
the available internal RAM space of 256 bytes (see Fig.6).
All registers except the Program Counter and the four
register banks reside in the Special Function Register
address space.
8.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers can only be addressed
directly in the address range from 128to 255 (see Fig.7).
8.2.3 AUX-RAM AUX-RAM 0to 1791 is indirectly addressable via page
register (XRAMP) and MOVX-Ri instructions, unless it is
disabled by setting ARD= 1 (see Fig.5). When
executing from internal Program Memory, an access to
AUX-RAM 0to 1791 will not affect the ports P0, P2,
P3.6 and P3.7. AUX-RAM 0to 1791 is also indirectly addressable as
external Data Memory locations 0to 1791 via MOVX-Ri
instructions, unless it is disabled by setting ARD=1.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
An access to external Data Memory locations higher than
1791 will be performed with the MOVX @DPTR
instructions in the same way as in the 80C51 structure, so
with P0 and P2 as data/address bus and P3.6 and P3.7 as
write and read timing signals.
Note that the external Data Memory cannot be accessed
with R0 and R1 as address pointer if the AUX-RAM is
enabled (ARD= 0, default).
8.2.4 AUX-RAM PAGE REGISTER (XRAMP)
The AUX-RAM Page Register is used to select one of
seven 256-bytes pages of the internal 1792 bytes
AUX-RAM for MOVX-accesses via R0 or R1. Its reset
value is ‘XXXX X000B’.
Table 4 AUX-RAM Page Register (address FAH)
Table 5 Description of XRAMP bits
Table 6 Memory locations for all possible MOVX-accesses= don’t care.
Note ARD: AUX-RAM disable, is a bit in SFR PCON (bit PCON.6); see Section 15.5.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
8.3 Addressing
The P8xC557E8 has five methods for addressing: Register Direct Register-Indirect Immediate Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
Access to memory addresses is as follows: Register in one of the four register banks through
Register, Direct or Register-Indirect addressing. Internal RAM (2048 bytes) through Direct or
Register-Indirect addressing. Internal RAM: bytes0to
directly/indirectly. Internal RAM: bytes 128
location with the SFRs and so may only be addressed
indirectly as data RAM. AUX-RAM: bytes0to 1791; can only be addressed
indirectly via MOVX. Special Function Registers through direct addressing at
address locations 128to 255 (see Fig.7). External Data Memory through Register-Indirect
addressing. Program Memory look-up tables through Base-Register
plus Index-Register-Indirect addressing.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 I/O FACILITIES
The P8xC557E8 has six 8-bit ports. Ports0to 3 are the
same as in the 80C51, with the exception of the additional
functions of Port 1. The parallel I/O function of Port 4 is
equal to that of Ports1,2 and 3. All ports are bidirectional
with the exception of Port 5 which is only a parallel input
port.
Ports0,1,2,3,4 and 5 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P8xC557E8 with
standard memories and peripherals.
Port 1 Is used for a number of special functions:4 capture inputs (or external interrupt request
inputs if capture information is not utilized) external counter input external counter reset input.
Port 2 Provides the high-order address bus when the
P8xC557E8 is expanded with external Data
Memory and / or the P8xC557E8 executes from
external Program Memory.
Port 3 Pins can be configured individually to provide: External interrupt request inputs Counter inputs Receiver input and transmitter output of serial
port SIO0 (UART) Control signals to read and write external Data
Memory.
Port 4 Can be configured to provide signals indicating a
match between timer/counter T2 and its compare
registers.
Port 5 May be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs.
As Port 5 lines may be used as inputs to the ADC,
these digital inputs have an inherent hysteresis to
prevent the input logic from drawing too much
current from the power lines when driven by analog
signals. Channel-to-channel crosstalk should be
taken into consideration when both digital and
analog signals are simultaneously input to Port5
(see Chapter 21).
A pin of which the alternative function is not used may be
used as normal bidirectional I/O. The generation or use of
a Port 1, Port 3 or Port 4 pin as an alternative function is
carried out automatically by the P8xC557E8 provided the
associated Special Function Register bit is set HIGH.
The SDA and SCL lines serve the serial port SI012 C-bus). Because the I2 C-bus may be active while the
device is disconnected from VDD, these pins are provided
with open-drain drivers.
Figure 8 shows the pull-up arrangements of Ports1to4;
Transistor ‘p1’ is turned on for 2 oscillator periods afterQ
makes a HIGH-to-LOW transition. During this time, ‘p1’
also turns on ‘p3’ through the inverter to form an additional
pull-up.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 PULSE WIDTH MODULATED OUTPUTS
The P8xC557E8 contains two Pulse Width Modulated
(PWM) output channels (see Fig.9). These channels
generate pulses of programmable length and interval.
The repetition frequency is defined by an 8-bit prescaler
PWMP, which supplies the clock for the counter.
The prescaler and counter are common to both PWM
channels. The 8-bit counter counts modulo 255, i.e., fromto 254 inclusive. The value of the 8-bit counter is
compared to the contents of two registers: PWM0 and
PWM1.
Provided the contents of either of these registers is greater
than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers
are equal to, or less than the counter value, the output will
be HIGH. The pulse-width-ratio is therefore defined by the
contents of the registers PWM0 and PWM1.
The pulse-width-ratio is in the range of0⁄255to 255 ⁄255 and
may be programmed in increments of 1⁄255.
Buffered PWM outputs may be used to drive DC motors.
The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be
configured as a dual DAC.
In this application, the PWM outputs must be integrated
using conventional operational amplifier circuitry. If the
resulting output voltages have to be accurate, external
buffers with their own analog supply should be used to
buffer the PWM outputs before they are integrated.
The repetition frequency fPWM, at the PWMn outputs is
given by:
This gives a repetition frequency range of 123 Hz to
31.4 kHz (at fclk=16 MHz). By loading the PWM registers
with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit
counter counts modulo 255, it can never actually reach the
value of the PWM registers when they are loaded with
FFH.
When a compare register (PWM0or PWM1) is loaded with
a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other
purpose. PWM CLK PWMP 1+()× 255× ---------------------------------------------------------------=
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
10.1 Prescaler Frequency Control Register (PWMP)
Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
Table 7 Prescaler Frequency Control Register (address FEH)
Table 8 Description of PWMP bits
10.2 Pulse Width Register 0 (PWM0)
Table 9 Pulse width register (address FCH)
Table 10 Description of PWM0 bits
10.3 Pulse Width Register 1 (PWM1)
Table 11 Pulse width register (address FDH)
Table 12 Description of PWM1 bits
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1 ADC features 10-bit resolution 8 multiplexed analog inputs Programmable autoscan of the analog inputs Bit oriented 8-bit scan-select register to select analog
inputs Continuous scan or one time scan configurable fromto 8 analog inputs Start of a conversion by software or with an external
signal Eight 10-bit buffer registers, one register for each analog
input channel Interrupt request after one channel scan loop Programmable prescaler (dividingby2,4,6, 8) to adapt
to different system clock frequencies Conversion time for one analog-to-digital conversion:to50μs Differential non-linearity (DLe): ±1 LSB Integral non-linearity (ILe): ±2 LSB Offset error (OSe): ±2 LSB Gain error (Ge): ±4% Absolute voltage error (Ae): 3 LSB Channel-to-channel matching (Mctc):±1 LSB Crosstalk between analog inputs (Ct): <60 dB at
100 kHz Monotonic and no missing codes Separated analog (VDDA,VSSA) and digital (VDD,VSS)
supply voltages Reference voltage at two special pins: Vref(n)(A) and
Vref(p)(A).
For information on the ADC characteristics, refer to
Chapter 21.
11.2 ADC functional description
The P8xC557E8 has a 10-bit successive approximation
ADC with 8 multiplexed analog input channels, comprising
a high input impedance comparator, DAC (built with
1024 series resistors and analog switches), registers and
control logic. Input voltage range is from Vref(n)(A)
(typical0 V) to Vref(p)(A) (typical+5 V).
Each of the set of 8 buffer registers (10-bit wide) store the
conversion results of the proper analog input channel.
Eleven Special Function Registers (SFRs) perform the
user software interface to the ADC; see Table 14 for an
overview of the ADC SFRs. In order to have a minimum of
ADC service overhead in the microcontroller program, the
ADC is able to operate autonomously within its user
configurable autoscan function.
Figure 10 shows the functional diagram of the ADC.
11.3 ADC timing
A programmable prescaler is controlled by the user
selectable bits ADPR1 and ADPR0 in SFR ADCON to
adapt the conversion time for different microcontroller
clock frequencies.
Table 13 shows conversion times (tADC) for one
analog-to-digital conversion at some convenient system
clock frequencies (fclk) and ADC programmable prescaler
divisors:m.
Conversion time tADC =(6×m+ 1) machine cycles.
A conversion time tADC consists of one sample time period
(which equals two bit conversion times), 10 bit conversion
time periods and one machine cycle to store the result.
After result storage an extra initializing time period follows
to select the next analog input channel (according to the
contents of SFR ADPSS), before the input signal is
sampled.Thus the time period between two adjacent
conversions within an autoscan loop is larger than the pure
time tADC. This autoscan cycle time is (7× m) machine
cycles.
At the start of an autoscan conversion the time between
writing to SFR ADCON and the first analog input signal
sampling depends on the current prescaler value (m) and
the relative time offset between this write operation and the
internal (divided) ADC clock. This gives a variation range
for the analog-to-digital conversion start time of (1⁄2×m)
machine cycles.
Table 13 Conversion time configuration examples
Note Prohibited tADC values; for tADC outside the limits ofμs≤ tADC≤50 μs, the specified ADC
characteristics are not guaranteed.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
11.4 ADC configuration and operation
Every analog-to-digital conversion is an autoscan
conversion. The two user selectable general operation
modes are continuous scan and one-time scan mode.
The desired analog input port channel(s) for conversion
is(are) selected by programming analog-to-digital input
port scan-select bits in SFR ADPSS. An analog input
channel is included in the autoscan loop if the
corresponding bit in SFR ADPSS is logic 1, a channel is
skipped if the corresponding bit in SFR ADPSS is logic0.
An autoscan is always started according to the lowest bit
position of SFR ADPSS that contains a logic1.
An autoscan conversion is started by setting the flag
ADSST in register ADCON either by software or by an
external start signal at input pin ADEXS, if enabled.
Either no edge (external start totally disabled), a rising
edge or/and a falling edge of ADEXS is selectable for
external conversion start by the bits ADSRE and ADSFE
in register ADCON.
After completion of an analog-to-digital conversion the
10-bit result is stored in the corresponding 10-bit buffer
register. Then the next analog input is selected according
to the next higher set bit position in ADPSS, converted and
stored, and so on.
When the result of the last conversion of this autoscan loop
is stored, the ADC interrupt flag ADINT (SFR ADCON), is
set. It is not cleared by interrupt hardware - it must be
cleared by software.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
In continuous scan mode (ADCSA= 1; ADCON.2) the
ADC start and status flag ADSST (ADCON.3) retains the
set state and the autoscan loop restarts from the
beginning. In one-time scan mode (ADCSA=0)
conversions stop after the last selected analog input was
converted, ADINT (ADCON.4) is set and ADSST is
cleared automatically.
ADSST cannot be set (neither externally nor by software)
as long as ADINT= 1, i.e. as long as ADINT is set, a new
conversion start - by setting flag ADSST - is inhibited;
actually it is only delayed until ADINT is cleared. If a logic1
is written to ADSST while ADINT= 1, this new value is
internally latched and preserved, not setting ADSST until
ADINT= 0. In this state, a read of SFR ADCON will display
ADSST= 0, because always the effective ADC status is
read.
Note that under software control the analog inputs can also
be converted in arbitrary order, when one-time scan mode
is selected and in SFR ADPSS only one bit is set at a time.
In this case ADINT is set and ADSST is cleared after every
conversion.
11.5 ADC during Idle and Power-down mode
The analog-to-digital converter is active only when the
microcontroller is in normal operating mode. If the Idle or
Power-down mode is activated, then the ADC is switched
off and put into a power saving idle state - a conversion in
progress is aborted, a previously set ADSST flag is cleared
and the internal clock is halted. The conversion result
registers are not affected.
The interrupt flag ADINT will not be set by activation of Idle
or Power-down mode. A previously set flag ADINT will not
be cleared by the hardware. (Note: ADINT cannot be
cleared by hardware at all, except for a reset - it must be
cleared by the user software.)
After a wake-up from Idle or Power-down mode a set flag
ADINT indicates that at least one autoscan loop was
finished completely before the microcontroller was put into
the respective power reduction mode and it indicates that
the stored result data may be fetched now - if desired.
For further information on Idle and Power-down modes,
refer to Chapter 15.
11.6 ADC resolution and characteristics
The ADC system has its own analog supply pins VDDA1
and VSSA1. It is referenced by two special reference
voltage input pins sourcing the resistance ladder of the
DAC: Vref(p)(A) and Vref(n)(A). The voltage between Vref(p)(A)
and Vref(n)(A) defines the full-scale range. Due to the 10-bit
resolution the full scale range is divided into 1024 unit
steps.
The unit step voltage is 1 LSB, which is typically 5 mV
(Vref(p)(A)= 5.12 V, Vref(n)(A) =0 V=VSSA1).
The DAC's resistance ladder has 1023 equally spaced
taps, separated by a unit resistance ‘R’.
The first tap is located 0.5× R above Vref(n)(A), the last tap
is located 1.5× R below Vref(p)(A). This results in a total
ladder resistance of 1024× R. This structure ensures that
the DAC is monotonic and results in a symmetrical
quantization error. For input voltages between: Vref(n)(A) and [Vref(n)(A)+1⁄2× LSB] the 10-bit conversion
result code will be 0000000000B (= 000Hor 0D) [Vref(p)(A)−3⁄2× LSB] and Vref(p)(A) the 10-bit conversion
result code will be 1111111111B (= 3FFHor 1023D).
The result code corresponding to an analog input voltage
(Vin(A)) can be calculated from the formula:
The analog input voltage should be stable when it is
sampled for conversion. At any times the input voltage
slew rate must be less than 10 V/ms (5 V conversion
range) in order to prevent an undefined result.
This maximum input voltage slew rate can be ensured by
an RC low pass filter with R= 2.2 kΩ and C= 100 nF.
The capacitor between analog input pin and analog
ground pin shall be placed close to the pins in order to
have maximum effect in minimizing input noise coupling.
11.7 ADC after reset
After a reset of the microcontroller the ADCON and
ADPSS registers are initialized to zero. Registers ADRSLn
and ADRSH are not initialized by a reset.
Result code 1024 V in(A) V ref(n)(A)– ref(p)(A) V ref(n)(A)– ------------------------------------------------×=
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
11.8 ADC Special Function Registers
Table 14 ADC Special Function Registers overview
The SFRs are not bit addressable. For more information on Special Function Registers refer to Section 8.2.
11.8.1 ADC RESULT REGISTERS
The binary result code of the analog-to-digital conversions is accessed by the ADC Result Registers: ADRSLn (ADRSL0 to ADRSL7); eight input channel related conversion result SFRs for the 8 result lower bytes. Each
of ADRSLn is associated with the indexed analog input channel ADCn (ADC0/P5.0to ADC7/P5.7). ADRSH for the ADC; one general SFR for the 2 result upper bits (bit 9 and 8).
During read (by software) of the ADRSLn register, simultaneously the two highest bits of the 10-bit conversion result are
copied into the two latches, ADRSH.0 and ADRSH.1 (SFR ADRSH) preserving them until the next read of any ADRSLn
register. Thus to ensure that the 10-bit result of the same single analog-to-digital conversion is captured, first read the
ADRSLn register and then the ADRSH register.
Table 15 ADC Result Register Low Byte; ADRSLn; n=0to 7 (address see 86Hto F6H)
Table 16 Description of ADRSLn bits
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Table 17 ADC Result Register High Bits; ADRSH (address F7H)
Table 18 Description of ADRSH bits
11.8.2 ADC INPUT PORT SCAN-SELECT REGISTER (ADPSS)
Table 19 ADC Input Port Scan-Select Register (address E7H)
Table 20 Description of ADPSS bits
11.8.3 ADC CONTROL REGISTER (ADCON)
Table 21 ADC Control Register (address D7H)
Table 22 Description of ADCON bits
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8-bit microcontroller P8xC557E8
Table 23 Prescaler selection
11.8.4 DIGITAL INPUT PORT REGISTER (P5)
Digital Input Port Register (P5) is shared with analog inputs. P5 is not affected by chip reset. SFR P5 always represents
the binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC7. Reading P5 does not affect analog-to-digital
conversions. But it is recommended to use the digital input port function of the hardware Port 5 only as an alternative to
analog input voltage conversions. Simultaneous mixed operation is discouraged to guarantee a reliable and accurate
ADC result. For more information on P5 refer to Chapter9.
Table 24 Digital Input Port Register (address C7H)
Table 25 Description of P5 bits
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 TIMERS/COUNTERS
The P8xC557E8 contains, Three 16-bit timer/event counters:
Timer 0, Timer 1 and TimerT2 One 8-bit timer, T3.
12.1 Timer 0 and Timer1
Timer 0 and Timer 1 may be programmed to carry out the
following functions: Measure time intervals and pulse durations Count events Generate interrupt requests.
Timers 0 and 1 each have a control bit in SFR TMOD that
selects the timer or counter function of the corresponding
timer.
In the timer function, the register is incremented every
machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of oscillator periods, the count rate is1⁄12× the oscillator
frequency.
In the counter function, the register is incremented in
response to a HIGH-to-LOW transition at the
corresponding external input pin, T0 or T1. In this function,
the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one
cycle and a LOW in the next cycle, the counter is
incremented. Thus, it takes two machine cycles
(24 oscillator periods) to recognize a HIGH-to-LOW
transition. There are no restrictions on the duty cycle of the
external input signal. To ensure that a given level is
sampled at least once before it changes, it should be held
for at least one full machine cycle.
Timer 0 and Timer 1 can be programmed independently to
operate in one of four modes:
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Mode 3 Timer 0: one 8-bit time-interval or event counter
and one 8-bit time-interval counter.
Timer1: stopped.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1or 2 but cannot set an interrupt
request flag or generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the serial port
baud rate generator. With a 16 MHz crystal, the counting
frequency of these timers/counters is as follows: In the timer function, the timer is incremented at a
frequency of 1.33 MHz (1⁄12× the system clock
frequency) When programmed for external inputs: 0to 660 kHz1⁄24× the system clock frequency).
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations. When configured as a counter, the
register is incremented on every falling edge on the
corresponding input pin T0 or T1. The earliest moment, the
incremented register value can be read is during the
second machine cycle following the machine cycle within
which the incrementing pulse occurred.
The counters are started and stopped under software
control. Each one sets its interrupt request flag when it
overflows from all HIGHs to all LOWs (or automatic reload
value), with the exception of Mode 3 as previously
described.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
12.1.1 TIMER/COUNTER MODE CONTROL REGISTER (TMOD)
Table 26 Timer/Counter Mode Control Register (address 89H)
Table 27 Description of TMOD bits for Timer 1 and Timer0
Timer 0: bit TMOD.0to TMOD.3; Timer 1: bit TMOD.4to TMOD.7; n= 0, 1.
Table 28 Timer 0, Timer 1 mode select
12.1.2 TIMER/COUNTER CONTROL REGISTER (TCON)
Table 29 Timer/Counter Control Register (address 88H)
Table 30 Description of TCON bits
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
12.2 Timer T2
Timer T2 is a 16-bit timer/counter which has capture and
compare facilities. The operational diagram is shown in
Figure 11.
The 16 bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with1⁄12 of the clock frequency, or
by an external source connected to the T2 input, or it is
switched off. The maximum repetition rate of the external
clock source is1⁄12× fclk, twice that of Timer 0 and Timer1.
The prescaler is incremented on a rising edge. It is cleared
if its division factor or its input source is changed, or if the
timer/counter is reset (see in Table 31). T2 is readable ‘on
the fly’, without any extra read latches; this means that
software precautions have to be taken against
misinterpretation at overflow from least to most significant
byte while T2 is being read. T2 is not loadable and is reset
by the RST signal or at the positive edge of the input signal
RT2, if enabled. In the Idle or Power-down mode the timer/
counter and prescaler are reset and halted.
T2 is connected to four 16-bit Capture Registers:
CT0, CT1, CT2 and CT3. A rising or falling edge on the
inputs CT0I, CT1I, CT2I or CT3I (alternative function of
Port 1) results in loading the contents of T2 into the
respective Capture Registers and an interrupt request.
Using the Capture Register CTCON (see Table 35), these
inputs may invoke capture and interrupt request on a
positive edge, a negative edge or on both edges. If neither
a positive nor a negative edge is selected for capture input,
no capture or interrupt request can be generated by this
input.
The contents of the Compare Registers CM0, CM1 and
CM2 are continuously compared with the counter value of
Timer T2. When a match occurs, an interrupt may be
invoked. A match of CM0 sets the bits 0to 5 of Port 4, a
CM1 match resets these bits and a CM2 match toggles bits
6 and 7 of Port 4, provided these functions are enabled by
the STE respectively RTE registers. A match of CM0 and
CM1 at the same time results in resetting bits 0-5 of Port4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
For more information concerning the TM2CON, CTCON,
TM2IR and the STE/RTE registers see “Data Handbook
IC20; Section 80C51 family hardware description”.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At a byte
overflow of the least significant byte, or at a 16-bit overflow
of the timer/counter, an interrupt sharing the same
interrupt vector is requested. Either one or both of these
overflows can be programmed to request an interrupt.
All interrupt flags must be reset by software.
12.2.1 T2 CONTROL REGISTER (TM2CON)
Table 31 T2 Control Register (address EAH)
Table 32 Description of TM2CON bits
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8-bit microcontroller P8xC557E8
Table 33 Timer 2 prescaler select
Table 34 Timer 2 mode select
12.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 35 Capture Control Register (address EBH)
Table 36 Description of CTCON bits
12.2.3 INTERRUPT FLAG REGISTER (TM2IR)
Table 37 Interrupt flag register (address C8H)
Table 38 Description of TM2IR bits
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8-bit microcontroller P8xC557E8
12.2.4 SET ENABLE REGISTER (STE)
Table 39 Set enable register (address EEH)
Table 40 Description of STE bits
12.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 41 Reset/Toggle enable register (address EFH)
Table 42 Description of RTE bits
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8-bit microcontroller P8xC557E8
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
12.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer (T3) consisting of an 11-bit prescaler and
an 8-bit timer is also incorporated (see Fig.12).
T3 is incremented every 1.5 ms, derived from the oscillator
frequency of 16 MHz by the following formula:
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at pin RSTOUT. Also
the PLL control register is reset.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control. timerclk 2048× --------------------------=
The Watchdog Timer can only be reloaded if the condition
flag WLE= PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded value.
For example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
In the Idle state the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer is controlled by the watchdog enable
pin (EW). A LOW level enables the watchdog timer and
disables the Power-down mode. A HIGH level disables the
watchdog timer and enables the Power-down mode.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 SERIAL I/O PORTS
The P8xC557E8 is equipped with 2 independent serial
ports: SIO0, which is the full duplex UART port, identical to the
PCB80C51 serial port SIO1,which is an I2 C-bus serial I/O interface with byte
oriented master and slave functions.
13.1 Serial I/O Port: SIO0 (UART)
SIO0 is a full duplex serial I/O port - it can transmit and
receive simultaneously. This serial port is also
receive-buffered. It can commence reception of a second
byte before the previously received byte has been read
from the receive register. If, however, the first byte has still
not been read by the time reception of the second byte is
complete, one of the bytes will be lost. The SIO0 receive
and transmit registers are both accessed via the S0BUF
special function register. Writing to S0BUF loads the
transmit register, and reading S0BUF accesses a
physically separate receive register. SIO0 can operate in
four modes:
Mode 0 Serial data is transmitted and received through
RXD. TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at1⁄12 × the oscillator frequency. A write into
S0CON should be avoided during a transmission
to avoid spikes on RXD/TXD.
Mode 1 10 bits are transmitted via TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit is put
into RB8 of the S0CON SFR. The baud rate is
variable.
Mode 2 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
On transmit, the 9th data bit (TB8 in S0CON) can
be assigned the value of 0or 1. With nominal
software, TB8 can be the parity bit (P in PSW).
During a receive, the 9th data bit is stored in RB8
(S0CON), and the stop bit is ignored. The baud
rate is programmable to either1 ⁄32 or1 ⁄64 of the
oscillator frequency.
Mode 3 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
Mode 3 is the same as Mode 2 except for the
baud rate which is variable in Mode3.
In all four modes, transmission is initiated by any
instruction that writes to the SFR S0BUF. Reception is
initiated in Mode 0 when RI= 0 and REN= 1. In the other
three modes, reception is initiated by the incoming start bit
provided that REN=1.
Modes2 and 3 are provided for multiprocessor
communications. In these modes, 9 data bits are received
with the 9th bit written to RB8 (S0CON). The 9th bit is
followed by the stop bit. The port can be programmed so
that with receiving the stop bit, the serial port interrupt will
be activated if, and only if RB8=1.
This feature is enabled by setting bit SM2 in S0CON.
It may be used in multiprocessor systems.
For more information about how to use the UART in
combination with the registers S0CON, PCON, IE, SBUF
and the Timer register, refer to “Data Handbook IC20”.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
13.1.1 SERIAL PORT CONTROL REGISTER (S0CON)
Table 43 Serial Port Control Register (address 98H)
Table 44 Description of S0CON bits
Table 45 Serial port mode select
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
13.2 Serial I/O Port: SIO1 (I2C-bus interface)
The SIO1 of the P8xC557E8 provides the fast mode,
which allows a fourth-fold increase of the bit rate up to
400 kHz. Nevertheless it is downward compatible, i.e. it
can be used in a 0to 100 kbit/s I2C-bus system.
Except from the bit rate selection (see Table 48) and the
timing of the SCL and SDA signals (see Chapter 11) the
SIO circuit is the same as described in detail in the
80C51-based “Data Handbook IC20” for the 8xC552
microcontroller.
The I2 C-bus is a simple bidirectional 2-wire bus for efficient
inter-IC data exchange. Features of the I2 C-bus are: Only two bus lines are required: a serial clock line (SCL)
and a serial data line (SDA) Each device connected to the bus is software
addressable by a unique address Masters can operate as master transmitter or as master
receiver It is a true multi-master bus including collision detection
and arbitration to prevent data corruption if two or more
masters simultaneously initiate data transfer Serial clock synchronization allows devices with
different bit rates to communicate via the same serial
bus ICs can be added to or removed from an I2C-bus system
without affecting any other circuit on the bus Fault diagnostics and debugging are simple;
malfunctions can be immediately traced.
For more information on the I2 C-bus specification
(including fast-mode) please refer to the Philips publication
“The I2 C-bus and how to use it” ordering number
9398 393 40011 and/or the 80C51-based
“Data Handbook IC20”.
The on-chip I2 C logic provides a serial interface that meets
the I2 C-bus specification, supporting 4 modes of operation: Master transmitter Master receiver Slave transmitter Slave receiver.
The SIO1 logic performs a byte oriented data transport;
clock generation, address recognition and bus control
arbitration are all controlled by hardware. Via two pins the
external I2 C-bus is interfaced to the SIO1 logic: SCL serial
clock I/O and SDA serial data I/O (SFR S1CON bit ENS1
for enabling the SIO1 logic).
The SIO1 logic handles byte transfer autonomously.
It keeps track of the serial transfers, and a status register
(S1STA) reflects the status of SIO1 and the I2 C-bus.
Via 4 SFRs the CPU interfaces to the I2 C-bus logic: S1CON; Serial Control Register. Bit-addressable by the
CPU S1STA; Status Register whose contents may be used
as a vector to service routines S1DAT; Data Shift Register. The data byte is stable as
long as SI= 1 (SFR S1CON) S1ADR; Slave Address Register. Its LSB
enables/disables general call address recognition.
13.2.1 SERIAL CONTROL REGISTER (S1CON)
The CPU can read from and write to this 8-bit, directly
addressable SFR. Two bits are affected by the SIO1
hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present
on the I2 C-bus. The STO bit is also cleared when
ENS1=0.
When SIO1 is in a master mode, serial clock frequency is
determined by the clock rate bits CR2, CR1 and CR0.
The various bit rates are shown in Table 48.
The data shown in Table 48 do not apply to SIO1 in a slave
mode. In the slave modes, SIO1 will automatically
synchronize with any clock frequency up to 400 kHz.
However, serial clock frequencies above 100 kHz require
an oscillator frequency fclk of at least 12 MHz.
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8-bit microcontroller P8xC557E8
Table 46 Serial Control Register (address D8H)
Table 47 Description of S1CON bits
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
Table 48 Selection of I2C-bus bit rate
Note These bit rates are for ‘fast-mode’ I2 C-bus applications and cannot be used for standard I2 C bit rates up to
100 kbits/s.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
13.2.2 SERIAL STATUS REGISTER (S1STA)
The contents of this register may be used as a vector to a service routine. This optimizes the response time of the
software and consequently that of the I2 C-bus. S1STA is a read-only register. The status codes for all possible modes
of the I2 C-bus interface are given in Tables51to 55.
Table 49 Serial status register (address D9H)
Table 50 Description of S1STA bits
Table 51 MST/TRX mode
Table 52 MST/REC mode
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8-bit microcontroller P8xC557E8
Table 53 SLV/REC mode
Table 54 SLV/TRX mode
Table 55 Miscellaneous
Table 56 Symbols used in Tables51to55
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
13.2.3 DATA SHIFT REGISTER (S1DAT)
This register contains the serial data to be transmitted or data which has been received. Bit 7 is transmitted or received
first; i.e. data is shifted from right to left.
Table 57 Data Shift Register (address DAH)
13.2.4 ADDRESS REGISTER (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.
Table 58 Address Register (address DBH)
Table 59 Description of S1ADR bits
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. Interrupt response
time in a single-interrupt system is in the range
2.25μsto 6.75 μs when using a 16 MHz crystal.
The latency time depends on the sequence of instructions
executed directly after an interrupt request.
The P8xC557E8 acknowledges interrupt requests from sources as follows (see Fig.14): INT0 and INT1 external interrupts Timer 0 and Timer 1 internal timer/counter interrupts Timer 2 internal timer/counter byte and/or 16-bit
overflow, 3 compare and 4 capture interrupts (or additional external interrupts).
Note that if a capture register is unused and its contents
are of no interest, then the corresponding input pin
CTnI/P1.n (n=0to 3) may be used as a (configurable)
positive and/or negative edge triggered additional
external interrupt input (INT2, INT3, INT4 and INT5). UART serial I/O port receive/transmit interrupt I2C-bus interface serial I/O interrupt ADC autoscan completion interrupt ‘Seconds’ timer interrupt SEC (ORed with INT1); for
details please refer to Chapter 16.2.4.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in register TCON. The flags that actually
generate these interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the hardware
when the service routine is vectored to, only if the interrupt
was transition-activated. If the interrupt was level-activated
then the interrupt request flag remains set until the external
interrupt pin INTn goes HIGH. Consequently, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is
completed, or else another interrupt will be generated.
As these external interrupts are active LOW a ‘wire-ORing’
of several interrupt sources to one input pin allows
expansion.
The Timer 0 and Timer 1 interrupts are generated by TF0
and TF1, which are set by a roll-over in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
The eight Timer/Counter T2 Interrupt sources are: capture Interrupts (1), 3 compare interrupts and an
overflow interrupt. The appropriate interrupt request flags
must be cleared by software.
The UART Serial Port Interrupt is generated by the logical
OR of RI and TI (register S0CON). Neither of these flags
is cleared by hardware. The service routine will normally
have to determine whether it was RI or TI that generated
the interrupt, and the bit will have to be cleared by
software.
The I2 C Interrupt is generated by bit SI in register S1CON.
This flag has to be cleared by software.
The ADC Interrupt is generated by bit ADINT, which is set
when the conversion of all selected analog inputs to be
scanned is finished. ADINT must be cleared by software.
It cannot be set by software.
The ‘seconds’ timer Interrupt is generated by bit SECINT
in register PLLCON. This flag has to be cleared by
software. Note that the ‘seconds’ timer can only be used
with the 32 kHz PLL oscillator.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware (except the ADC interrupt
request flag ADINT, which cannot be set by software).
That is, interrupts can be generated or pending interrupts
can be cancelled in software.
The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are able to
terminate the Idle mode.
14.1 Interrupt Enable Registers
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the interrupt enable
Special Function Registers IEN0 and IEN1. All interrupt
sources can also be globally disabled by clearing bit EA in
IEN0. The interrupt enable registers are described in
Tables62 and 64.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
14.2 Interrupt Handling
The interrupt sources are sampled at S5P2 of every
machine cycle. The samples are polled during the
following machine cycle. If one of the flags was in a set
condition at S5P2 of the previous machine cycle, the
polling cycle will detect it and the interrupt system will
generate an LCALL to the appropriate service routine,
provided this hardware generated LCALL is not blocked by
any of the following conditions: An interrupt of higher or equal priority level is already
in progress. The current machine cycle is not the final cycle in the
execution of the instruction in progress. (No interrupt
request will be serviced until the instruction in progress
is completed.). The instruction in progress is RETI or any access to
the interrupt priority or interrupt enable registers.
(No interrupt will be serviced after RETI or after a read
or write to IP0, IP1, IE0, or IE1 until at least one other
instruction has been subsequently executed.).
The polling cycle is repeated every machine cycle, and the
values polled are the values present at S5P2 of the
previous machine cycle. Note that if an interrupt flag is
active but is not being responded to because of one of the
above conditions, and if the flag is inactive when the
blocking condition is removed, then the blocked interrupt
will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
The processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
service routine. In some cases it also clears the flag which
generated the interrupt, and in others it does not. It clears
the Timer 0, Timer 1, and external interrupt flags.
An external interrupt flag (IE0or IE1) is cleared only if it
was transition-activated. All other interrupt flags are not
cleared by hardware and must be cleared by the software.
The LCALL pushes the contents of the program counter on
to the stack (but it does not save the PSW) and reloads the
PC with an address that depends on the source of the
interrupt being vectored to as shown in Table 60.
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the
‘priority level active’ flip-flop that was set when this
interrupt was acknowledged. It then pops the top two bytes
from the stack and reloads the program counter. Execution
of the interrupted program continues from where it was
interrupted.
14.3 Interrupt Priority Structure
Each interrupt source can be assigned one of two priority
levels: high and low. Interrupt priority levels are defined by
the interrupt priority SFRs IP0 and IP1, which are
described in Tables66 and 68.
Interrupt priority levels are as follows:
logic0= low priority
logic1= high priority.
A low priority interrupt may be interrupted by a high priority
interrupt. A high priority interrupt cannot be interrupted by
any other interrupt source. If two requests of different
priority occur simultaneously, the high priority level request
is serviced. If requests of the same priority are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level,
there is a second priority structure determined by the
polling sequence. This second priority structure is shown
in Table 60.
14.4 Interrupt vectors
The vector indicates the Program Memory location where
the appropriate interrupt service routine starts; Table 60.
Table 60 Interrupt vectors and priority structure
Note X0 has the highest priority; T2 the lowest.
Philips Semiconductors Product specification
8-bit microcontroller P8xC557E8
