P87C552SBAA ,80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, low voltage 2.7V.5.5V, low powerINTEGRATED CIRCUITSP87C55280C51 8-bit microcontroller28K/256 OTP, 8 channel 10 bit A/D, I C, PWM,ca ..
P87C552SFAA ,80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high IO, low voltage (2.7 V to 5.5 V), low powerINTEGRATED CIRCUITSP87C55280C51 8-bit microcontroller28K/256 OTP, 8 channel 10 bit A/D, I C, PWM,ca ..
P87C552SFAA ,80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high IO, low voltage (2.7 V to 5.5 V), low powerINTEGRATED CIRCUITSP87C55280C51 8-bit microcontroller28K/256 OTP, 8 channel 10 bit A/D, I C, PWM,ca ..
P87C554SBAA ,80C51 8-bit microcontrollerELECTRICAL CHARACTERISTICS . . . . 65EXPLANATION OF THE AC SYMBOLS . . . . 67EPRO ..
P87C554SFAA ,P87C554; 80C51 8-bit microcontrollerBLOCK DIAGRAM . . . . . . . 2PINNING INFORMATION . 3Plastic Leaded Chip Carri ..
P87C557E8EFB ,8-bit microcontrollerFEATURES The P8xC557E8 contains a volatile 2048 bytes read/writeData Memory, five 8-bit I/O ports, ..
PCA9541BS/01 ,PCA9541; 2-to-1 I²C master selector with interrupt logic and reset
PCA9541D/03 ,PCA9541; 2-to-1 I²C master selector with interrupt logic and reset
PCA9541PW ,2-to-1 I2C-bus master selector with interrupt logic and resetapplications where system operation is required, even when one master fails orthe controller card i ..
PCA9542APW ,2-channel I2C-bus multiplexer and interrupt logicGeneral description2The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via ..
PCA9542PW ,2-channel I2C multiplexer and interrupt controller
PCA9543AD ,2-channel I虏C-bus switch with interrupt logic and reset PCA9543A/43B22-channel I C-bus switch with interrupt logic and resetRev. 8 — 3 April 2014 Product ..
P87C552SBAA
80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, low voltage 2.7V.5.5V, low power
Preliminary specification
Supersedes data of 1999 Feb 04
IC20 Data Handbook
1999 Mar 30
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP , 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
DESCRIPTIONThe 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51.
The 87C552 contains a 8k × 8 non-volatile EPROM, a 256 × 8
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2C-bus), a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that require extra
capability, the 8xC552 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC552 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75μs and 40% in 1.5μs.
Multiply and divide instructions require 3μs.
FEATURES• 80C51 central processing unit 8k × 8 EPROM expandable externally to 64k bytes An additional 16-bit timer/counter coupled to four capture registers
and three compare registers Two standard 16-bit timer/counters 256 × 8 RAM, expandable externally to 64k bytes Capable of producing eight synchronized, timed outputs A 10-bit ADC with eight multiplexed analog inputs Fast 8-bit ADC option Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputsI2 C-bus serial I/O port with byte oriented master and slave
functions On-chip watchdog timer Extended temperature ranges Full static operation – 0 to 16 MHz Operating voltage range: 2.7V to 5.5V (0 to 16MHz) Security bits: OTP/EPROM – 3 bits Encryption array – 64 bytes 4 level priority interrupt 15 interrupt sources Full-duplex enhanced UART Framing error detection Automatic address recognition Power control modes Clock can be stopped and resumed Idle mode Power down mode Second DPTR register ALE inhibit for EMI reduction Programmable I/O pins Wake-up from power-down by external interrupts Software reset Power-on detect reset ADC charge pump disable ONCE mode ADC active in Idle mode
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
ORDERING INFORMATION
PART NUMBER DERIVATION
BLOCK DIAGRAM
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
PIN CONFIGURATIONS
Plastic Leaded Chip Carrier pin functions
LOGIC SYMBOL
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
PIN DESCRIPTION
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
PIN DESCRIPTION (Continued)
NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS – 0.5V,
respectively.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Table 1. 87C552 Special Function Registers
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
OSCILLATOR CHARACTERISTICSXTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESETA reset is accomplished by either (1) externally holding the RST pin
high for at least two machine cycles (24 oscillator periods) or (2)
internally by an on-chip power-on detect (POD) circuit which detects
VCC ramping up from 0V.
To insure a good external power-on reset, the RST pin must be high
long enough for the oscillator to start up (normally a few
milliseconds) plus two machine cycles. The voltage on VDD and the
RST pin must come up at the same time for a proper startup.
For a successful internal power-on reset, the VCC voltage must
ramp up from 0V smoothly at a ramp rate greater than 5V/100 ms.
The RST line can also be pulled HIGH internally by a pull-up
transistor activated by the watchdog timer T3. The length of the
output pulse from T3 is 3 machine cycles. A pulse of such short
duration is necessary in order to recover from a processor or system
fault as fast as possible.
Note that the short reset pulse from Timer T3 cannot discharge the
power-on reset capacitor (see Figure 2). Consequently, when the
watchdog timer is also used to set external devices, this capacitor
arrangement should not be connected to the RST pin, and a
different circuit should be used to perform the power-on reset
operation. A timer T3 overflow, if enabled, will force a reset condition
to the 8XC554 by an internal connection, independent of the level of
the RST pin.
A reset may be performed in software by setting the software reset
bit, SRST (AUXR1.5).
Figure 2. Power-On Reset
LOW POWER MODES
Stop Clock ModeThe static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle ModeIn the idle mode (see Table 2), the CPU puts itself to sleep while
some of the on-chip peripherals stay active. The instruction to
invoke the idle mode is the last instruction executed in the normal
operating mode before the idle mode is activated. The CPU
contents, the on-chip RAM, and all of the special function registers
remain intact during this mode. The idle mode can be terminated
either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and continued), or by a hardware
reset which starts the processor in the same manner as a power-on
reset.
Power-Down ModeTo save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. The Wake-up from Power-down bit, WUPD (AUXR1.3)
must be set in order for an external interrupt to cause a wake-up
from power-down. Reset redefines all the SFRs but does not
change the on-chip RAM. An external interrupt allows both the SFRs
and the on-chip RAM to retain their values.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Table 2. External Pin Status During Idle and Power-Down ModesWith an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
POWER OFF FLAGThe Power Off Flag (POF) is set by on-chip circuitry when the VCC
level on the 8XC552 rises from 0 to 5V. The POF bit can be set or
cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after powerdown. The VCC level
must remain above 3V for the POF to remain unaffected by the VCC
level.
Design Consideration• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
ONCE ModeThe ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by: Pull ALE low while the device is in reset and PSEN is high; Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Reduced EMI ModeThe ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output.
It will automatically become active when required for external
memory accesses and resume to the OFF state after completing the
external memory access.
Figure 3. Power Control Register (PCON)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 4. AUXR: Auxiliary Register
Dual DPTRThe dual DPTR structure (see Figure 5) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
Figure 5. Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an
INC AUXR1 instruction without affecting the other bits.
DPTR InstructionsThe instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 6. AUXR1: DPTR Control Register
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Enhanced UARTThe UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
S0CON register. The FE bit shares the S0CON.7 bit with SM0 and
the function of S0CON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then S0CON.7 functions as FE.
S0CON.7 functions as SM0 when SMOD0 is cleared. When used as
FE S0CON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address RecognitionAutomatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in S0CON. In the 9 bit
UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI)
will be automatically set when the received byte contains either the
“Given” address or the “Broadcast” address. The 9 bit mode
requires that the 9th information bit is a 1 to indicate that the
received information is an address and not data. Automatic address
recognition is shown in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Figure 7. S0CON: Serial Port Control Register
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 8. UART Framing Error Detection
Figure 9. UART Multiprocessor Communication, Automatic Address RecognitionMode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1101
Slave 1 SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1 SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
Slave 2 SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Timer T2Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH
byte) and TML2 (LOW byte). The 16-bit timer/counter can be
switched off or clocked via a prescaler from one of two sources:
fOSC/12 or an external signal. When Timer T2 is configured as a
counter, the prescaler is clocked by an external signal on T2 (P1.4).
A rising edge on T2 increments the prescaler, and the maximum
repetition rate is one count per machine cycle (1MHz with a 12MHz
oscillator).
The maximum repetition rate for Timer T2 is twice the maximum
repetition rate for Timer 0 and Timer 1. T2 (P1.4) is sampled at
S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising
edge is detected when T2 is LOW during one sample and HIGH
during the next sample. To ensure that a rising edge is detected, the
input signal must be LOW for at least 1/2 cycle and then HIGH for at
least 1/2 cycle. If a rising edge is detected before the end of S2P1,
the timer will be incremented during the following cycle; otherwise it
will be incremented one cycle later. The prescaler has a
programmable division factor of 1, 2, 4, or 8 and is cleared if its
division factor or input source is changed, or if the timer/counter is
reset.
Timer T2 may be read “on the fly” but possesses no extra read
latches, and software precautions may have to be taken to avoid
misinterpretation in the event of an overflow from least to most
significant byte while Timer T2 is being read. Timer T2 is not
loadable and is reset by the RST signal or by a rising edge on the
input signal RT2, if enabled. RT2 is enabled by setting bit T2ER
(TM2CON.5).
Either or both of these overflows can be programmed to request an
interrupt. In both cases, the interrupt vector will be the same. When
the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and
flag T20V (TM2IR) is set when TMH2 overflows. These flags are set
one cycle after an overflow occurs. Note that when T20V is set,
T2B0 will also be set. To enable the byte overflow interrupt, bits ET2
(IEN1.7, enable overflow interrupt, see Figure 10) and T2IS0
(TM2CON.6, byte overflow interrupt select) must be set. Bit TWB0
(TM2CON.4) is the Timer T2 byte overflow flag.
To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable
overflow interrupt) and T2IS1 (TM2CON.7, 16-bit overflow interrupt
select) must be set. Bit T2OV (TM2IR.7) is the Timer T2 16-bit
overflow flag. All interrupt flags must be reset by software. To enable
both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two
interrupt service routines are required. A test on the overflow flags
indicates which routine must be executed. For each routine, only the
corresponding overflow flag must be cleared.
Timer T2 may be reset by a rising edge on RT2 (P1.5) if the Timer
T2 external reset enable bit (T2ER) in T2CON is set. This reset also
clears the prescaler. In the idle mode, the timer/counter and
prescaler are reset and halted. Timer T2 is controlled by the
TM2CON special function register (see Figure 11).
Timer T2 Extension: When a 12MHz oscillator is used, a 16-bitoverflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms,
depending on the prescaler division ratio; i.e., the maximum cycle
time is approximately 0.5 seconds. In applications where cycle times
are greater than 0.5 seconds, it is necessary to extend Timer T2.
This is achieved by selecting fosc/12 as the clock source (set
T2MS0, reset T2MS1), setting the prescaler division ration to 1/8
(set T2P0, set T2P1), disabling the byte overflow interrupt (reset
T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The
following software routine is written for a three-byte extension which
gives a maximum cycle time of approximately 2400 hours.
OVINT: PUSH ACC ;save accumulator
PUSH PSW ;save status
INC TIMEX1 ;increment first byte (low order)
;of extended timer
MOV A,TIMEX1
JNZ INTEX ;jump to INTEX if ;there is no overflow
INC TIMEX2 ;increment second byte
MOV A,TIMEX2
JNZ INTEX ;jump to INTEX if there is no overflow
INC TIMEX3 ;increment third byte (high order)
INTEX: CLR T2OV ;reset interrupt flag
POP PSW ;restore status
POP ACC ;restore accumulator
RETI ;return from interrupt
Timer T2, Capture and Compare Logic: Timer T2 is connected tofour 16-bit capture registers and three 16-bit compare registers. A
capture register may be used to capture the contents of Timer T2
when a transition occurs on its corresponding input pin. A compare
register may be used to set, reset, or toggle port 4 output pins at
certain pre-programmable time intervals.
The combination of Timer T2 and the capture and compare logic is
very powerful in applications involving rotating machinery,
automotive injection systems, etc. Timer T2 and the capture and
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 10. Timer T2 Interrupt Enable Register (IEN1)
Figure 11. T2 Control Register (TM2CON)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 12. Block Diagram of Timer 2
Capture Logic: The four 16-bit capture registers that Timer T2 isconnected to are: CT0, CT1, CT2, and CT3. These registers are
loaded with the contents of Timer T2, and an interrupt is requested
upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These
input signals are shared with port 1. The four interrupt flags are in
the Timer T2 interrupt register (TM2IR special function register). If
the capture facility is not required, these inputs can be regarded as
additional external interrupt inputs.
Using the capture control register CTCON (see Figure 13), these
inputs may capture on a rising edge, a falling edge, or on either a
rising or falling edge. The inputs are sampled during S1P1 of each
cycle. When a selected edge is detected, the contents of Timer T2
are captured at the end of the cycle.
Measuring Time Intervals Using Capture Registers: When arecurring external event is represented in the form of rising or falling
edges on one of the four capture pins, the time between two events
can be measured using Timer T2 and a capture register. When an
event occurs, the contents of Timer T2 are copied into the relevant
capture register and an interrupt request is generated. The interrupt
service routine may then compute the interval time if it knows the
previous contents of Timer T2 when the last event occurred. With a
12MHz oscillator, Timer T2 can be programmed to overflow every
524ms. When event interval times are shorter than this, computing
the interval time is simple, and the interrupt service routine is short.
For longer interval times, the Timer T2 extension routine may be
used.
Compare Logic: Each time Timer T2 is incremented, the contentsof the three 16-bit compare registers CM0, CM1, and CM2 are
compared with the new counter value of Timer T2. When a match is
found, the corresponding interrupt flag in TM2IR is set at the end of
the following cycle. When a match with CM0 occurs, the controller
sets bits 0-5 of port 4 if the corresponding bits of the set enable
register STE are at logic 1.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 13. Capture Control Register (CTCON)When a match with CM1 occurs, the controller resets bits 0-5 of port
4 if the corresponding bits of the reset/toggle enable register RTE
are at logic 1 (see Figure 14 for RTE register function). If RTE is “0”,
then P4.n is not affected by a match between CM1 or CM2 and
Timer 2. When a match with CM2 occurs, the controller “toggles”
bits 6 and 7 of port 4 if the corresponding bits of the RTE are at
logic 1. The port latches of bits 6 and 7 are not toggled.
Two additional flip-flops store the last operation, and it is these
flip-flops that are toggled.
Thus, if the current operation is “set,” the next operation will be
“reset” even if the port latch is reset by software before the “reset”
operation occurs. The first “toggle” after a chip RESET will set the
port latch. The contents of these two flip-flops can be read at STE.6
and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits
STE.6 and STE.7 are read only (see Figure 15 for STE register
function). A logic 1 indicates that the next toggle will set the port
latch; a logic 0 indicates that the next toggle will reset the port latch.
CM0, CM1, and CM2 are reset by the RST signal.
The modified port latch information appears at the port pin during
S5P1 of the cycle following the cycle in which a match occurred. If
the port is modified by software, the outputs change during S1P1 of
the following cycle. Each port 4 bit can be set or reset by software at
any time. A hardware modification resulting from a comparator
match takes precedence over a software modification in the same
cycle. When the comparator results require a “set” and a “reset” at
the same time, the port latch will be reset.
Timer T2 Interrupt Flag Register TM2IR: Eight of the nine TimerT2 interrupt flags are located in special function register TM2IR (see
Figure 16). The ninth flag is TM2CON.4.
The CT0I and CT1I flags are set during S4 of the cycle in which the
contents of Timer T2 are captured. CT0I is scanned by the interrupt
logic during S2, and CT1I is scanned during S3. CT2I and CT3I are
set during S6 and are scanned during S4 and S5. The associated
interrupt requests are recognized during the following cycle. If these
flags are polled, a transition at CT0I or CT1I will be recognized one
cycle before a transition on CT2I or CT3I since registers are read
during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the
cycle following a match. CMI0 is scanned by the interrupt logic
during S2; CMI1 and CMI2 are scanned during S3 and S4. A match
will be recognized by the interrupt logic (or by polling the flags) two
cycles after the match takes place.
The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO)
are set during S6 of the cycle in which the overflow occurs. These
flags are recognized by the interrupt logic during the next cycle.
Special function register IP1 (Figure 16) is used to determine the
Timer T2 interrupt priority. Setting a bit high gives that function a
high priority, and setting a bit low gives the function a low priority.
The functions controlled by the various bits of the IP1 register are
shown in Figure 16.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 15. Set Enable Register (STE)
Figure 16. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Timer T3, The Watchdog TimerIn addition to Timer T2 and the standard timers, a watchdog timer is
also incorporated on the 8xC552. The purpose of a watchdog timer
is to reset the microcontroller if it enters erroneous processor states
(possibly caused by electrical noise or RFI) within a reasonable
period of time. An analogy is the “dead man’s handle” in railway
locomotives. When enabled, the watchdog circuitry will generate a
system reset if the user program fails to reload the watchdog timer
within a specified length of time known as the “watchdog interval.”
Watchdog Circuit Description: The watchdog timer (Timer T3)consists of an 8-bit timer with an 11-bit prescaler as shown in
Figure 17. The prescaler is fed with a signal whose frequency is
1/12 the oscillator frequency (1MHz with a 12MHz oscillator). The
8-bit timer is incremented every “t” seconds, where:
t = 12 × 2048 × 1/fOSC
(= 1.5ms at fOSC = 16MHz)
If the 8-bit timer overflows, a short internal reset pulse is generated
which will reset the 8xC552. A short output reset pulse is also
generated at the RST pin. This short output pulse (3 machine
cycles) may be destroyed if the RST pin is connected to a capacitor.
This would not, however, affect the internal reset operation.
Watchdog operation is activated when external pin EW is tied low.
When EW is tied low, it is impossible to disable the watchdog
operation by software.
How to Operate the Watchdog Timer: The watchdog timer has tobe reloaded within periods that are shorter than the programmed
watchdog interval; otherwise the watchdog timer will overflow and a
system reset will be generated. The user program must therefore
continually execute sections of code which reload the watchdog
timer. The period of time elapsed between execution of these
sections of code must never exceed the watchdog interval. When
using a 16MHz oscillator, the watchdog interval is programmable
between 1.5ms and 392ms.
In order to prepare software for watchdog operation, a programmer
should first determine how long his system can sustain an
erroneous processor state. The result will be the maximum
watchdog interval. As the maximum watchdog interval becomes
shorter, it becomes more difficult for the programmer to ensure that
the user program always reloads the watchdog timer within the
watchdog interval, and thus it becomes more difficult to implement
watchdog operation.
The programmer must now partition the software in such a way that
reloading of the watchdog is carried out in accordance with the above
requirements. The programmer must determine the execution times
of all software modules. The effect of possible conditional branches,
subroutines, external and internal interrupts must all be taken into
account. Since it may be very difficult to evaluate the execution
times of some sections of code, the programmer should use worst
case estimations. In any event, the programmer must make sure
that the watchdog is not activated during normal operation.
The watchdog timer is reloaded in two stages in order to prevent
erroneous software from reloading the watchdog. First PCON.4
(WLE) must be set. The T3 may be loaded. When T3 is loaded,
PCON.4 (WLE) is automatically reset. T3 cannot be loaded if
PCON.4 (WLE) is reset. Reload code may be put in a subroutine as
it is called frequently. Since Timer T3 is an up-counter, a reload
value of 00H gives the maximum watchdog interval (510ms with a
12MHz oscillator), and a reload value of 0FFH gives the minimum
watchdog interval (2ms with a 12MHz oscillator).
In the idle mode, the watchdog circuitry remains active. When
watchdog operation is implemented, the power-down mode cannot
be used since both states are contradictory. Thus, when watchdog
operation is enabled by tying external pin EW low, it is impossible to
enter the power-down mode, and an attempt to set the power-down
bit (PCON.1) will have no effect. PCON.1 will remain at logic 0.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
During the early stages of software development/debugging, the
watchdog may be disabled by tying the EW pin high. At a later
stage, EW may be tied low to complete the debugging process.
Watchdog Software Example: The following example shows howwatchdog operation might be handled in a user program.
;at the program start: EQU 0FFH ;address of watchdog timer T3
PCON EQU 087H ;address of PCON SFR
WATCH-INTV EQU 156 ;watchdog interval (e.g., 2x100ms)
;to be inserted at each watchdog reload location within
;the user program:
LCALL WATCHDOG
;watchdog service routine:
WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4)
MOV T3,WATCH-INV ;load T3 with watchdog interval
RET
If it is possible for this subroutine to be called in an erroneous state,
then the condition flag WLE should be set at different parts of the
main program.
Serial I/OThe 8xC552 is equipped with two independent serial ports: SIO0
and SIO1. SIO0 is a full duplex UART port and is similar to the
Enhanced UART serial port. SIO1 accommodates the I2 C bus.
SIO0: SIO0 is a full duplex serial I/O port identical to that of theEnhanced UART except Time 2 cannot be used as a baud rate
generator. Its operation is the same, including the use of timer 1 as a
baud rate generator.
Port 5 OperationPort 5 may be used to input up to 8 analog signals to the ADC.
Unused ADC inputs may be used to input digital inputs. These
inputs have an inherent hysteresis to prevent the input logic from
drawing excessive current from the power lines when driven by
analog signals. Channel to channel crosstalk (Ct) should be taken
into consideration when both analog and digital signals are
simultaneously input to Port 5 (see, D.C. characteristics in data
sheet).
Port 5 is not bidirectional and may not be configured as an output
port. All six ports are multifunctional, and their alternate functions
are listed in the Pin Descriptions section of this datasheet.
Pulse Width Modulated OutputsThe 8xC552 contains two pulse width modulated output channels
(see Figure 18). These channels generate pulses of programmable
length and interval. The repetition frequency is defined by an 8-bit
prescaler PWMP, which supplies the clock for the counter. The
prescaler and counter are common to both PWM channels. The 8-bit
counter counts modulo 255, i.e., from 0 to 254 inclusive. The value
of the 8-bit counter is compared to the contents of two registers:
PWM0 and PWM1. Provided the contents of either of these registers
is greater than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers are
equal to, or less than the counter value, the output will be HIGH. The
pulse-width-ratio is therefore defined by the contents of the registers
PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1
Buffered PWM outputs may be used to drive DC motors. The
rotation speed of the motor would be proportional to the contents of
PWMn. The PWM outputs may also be configured as a dual DAC. In
this application, the PWM outputs must be integrated using
conventional operational amplifier circuitry. If the resulting output
voltages have to be accurate, external buffers with their own analog
supply should be used to buffer the PWM outputs before they are
integrated. The repetition frequency fPWM, at the PWMn outputs is
give by:
fPWM fOSC(1 PWMP) 255
This gives a repetition frequency range of 123Hz to 31.4kHz (fOSC =
16MHz). By loading the PWM registers with either 00H or FFH, the
PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never
actually reach the value of the PWM registers when they are loaded
with FFH.
When a compare register (PWM0 or PWM1) is loaded with a new
value, the associated output is updated immediately. It does not
have to wait until the end of the current counter period. Both PWMn
output pins are driven by push-pull drivers. These pins are not used
for any other purpose.
Prescaler frequency control register PWMP Reset Value = 00H
PWMP (FEH)
MSB LSB
PWMP.0-7 Prescaler division factor = PWMP + 1.
Reading PWMP gives the current reload value. The actual count of
the prescaler cannot be read.
Reset Value = 00H
PWM0 (FCH)
PWM1 (FDH)
MSB LSB
PWM0/1.0-7} Low/high ratio of PWMn (PWMn)
255 (PWMn)
Analog-to-Digital ConverterThe analog input circuitry consists of an 8-input analog multiplexer
and a 10-bit, straight binary, successive approximation ADC. The
A/D can also be operated in 8-bit mode with faster conversion times
by setting bit ADC8 (AUXR1.7). The 8-bit results will be contained in
the ADCH register. The analog reference voltage and analog power
supplies are connected via separate input pins. For 10-bit accuracy,
the conversion takes 50 machine cycles, i.e., 37.5μs at an oscillator
frequency of 16MHz. For the 8-bit mode, the conversion takes 24
machine cycles. Input voltage swing is from 0V to +5V. Because the
internal DAC employs a ratiometric potentiometer, there are no
discontinuities in the converter characteristic. Figure 19 shows a
functional diagram of the analog input circuitry.
The ADC has the option of either being powered off in idle mode for
reduced power consumption or being active in idle mode for
reducing internal noise during the conversion. This option is selected
by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set,
the ADC is active in the idle mode, and with the AIDL bit cleared, the
ADC is powered off in idle mode.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 18. Functional Diagram of Pulse Width Modulated Outputs
Figure 19. Functional Diagram of Analog Input Circuitry
10-Bit Analog-to-Digital Conversion: Figure 20 shows theelements of a successive approximation (SA) ADC. The ADC
contains a DAC which converts the contents of a successive
approximation register to a voltage (VDAC) which is compared to
the analog input voltage (Vin). The output of the comparator is fed to
the successive approximation control logic which controls the
The software only start mode is selected when control bit ADCON.5
(ADEX) = 0. A conversion is then started by setting control bit
ADCON.3 (ADCS). The hardware or software start mode is selected
when ADCON.5 = 1, and a conversion may be started by setting
ADCON.3 as above or by applying a rising edge to external pin
STADC. When a conversion is started by applying a rising edge, a
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 20. Successive Approximation ADCThe low-to-high transition of STADC is recognized at the end of a
machine cycle, and the conversion commences at the beginning of
the next cycle. When a conversion is initiated by software, the
conversion starts at the beginning of the machine cycle which
follows the instruction that sets ADCS. ADCS is actually
implemented with two flip-flops: a command flip-flop which is
affected by set operations, and a status flag which is accessed
during read operations.
The next two machine cycles are used to initiate the converter. At
the end of the first cycle, the ADCS status flag is set and a value of
“1” will be returned if the ADCS flag is read while the conversion is in
progress. Sampling of the analog input commences at the end of the
second cycle.
During the next eight machine cycles, the voltage at the previously
selected pin of port 5 is sampled, and this input voltage should be
stable in order to obtain a useful sample. In any event, the input
voltage slew rate must be less than 10V/ms in order to prevent an
undefined result.
The successive approximation control logic first sets the most
significant bit and clears all other bits in the successive
approximation register (10 0000 0000B). The output of the DAC
(50% full scale) is compared to the input voltage Vin. If the input
voltage is greater than VDAC, then the bit remains set; otherwise it
is cleared.
The successive approximation control logic now sets the next most
significant bit (11 0000 0000B or 01 0000 0000B, depending on the
previous result), and VDAC is compared to Vin again. If the input
voltage is greater than VDAC, then the bit being tested remains set;
otherwise the bit being tested is cleared. This process is repeated
until all ten bits have been tested, at which stage the result of the
conversion is held in the successive approximation register.
Figure 21 shows a conversion flow chart. The bit pointer identifies
the bit under test. The conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit ADCON.4
(ADCI). The upper 8 bits of the result are held in special function
register ADCH, and the two remaining bits are held in ADCON.7
(ADC.1) and ADCON.6 (ADC.0). The user may ignore the two least
significant bits in ADCON and use the ADC as an 8-bit converter (8
upper bits in ADCH). In any event, the total actual conversion time is
50 machine cycles for the 8XC552. ADCI will be set and the ADCS
status flag will be reset 50 (or 24) cycles after the command flip-flop
(ADCS) is set.
Control bits ADCON.0, ADCON.1, and ADCON.2 are used to control
an analog multiplexer which selects one of eight analog channels
(see Figure 22). An ADC conversion in progress is unaffected by an
external or software ADC start. The result of a completed
conversion remains unaffected provided ADCI = logic 1; a new ADC
conversion already in progress is aborted when the idle or
power-down mode is entered. The result of a completed conversion
(ADCI = logic 1) remains unaffected when entering the idle mode.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 21. A/D Conversion Flowchart
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 22. ADC Control Register (ADCON)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
10-Bit ADC Resolution and Analog Supply: Figure 23 shows howthe ADC is realized. The ADC has its own supply pins (AVDD and
AVSS) and two pins (Vref+ and Vref–) connected to each end of the
DAC’s resistance-ladder. The ladder has 1023 equally spaced taps,
separated by a resistance of “R”. The first tap is located 0.5 x R
above Vref–, and the last tap is located 1.5 x R below Vref+. This
gives a total ladder resistance of 1024 x R. This structure ensures
that the DAC is monotonic and results in a symmetrical quantization
error as shown in Figure 25.
For input voltages between Vref– and (Vref–) + 1/2 LSB, the 10-bit
result of an A/D conversion will be 00 0000 0000B = 000H. For input
voltages between (Vref+) – 3/2 LSB and Vref+, the result of a
conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref– may
be between AVDD + 0.2V and AVSS – 0.2V. AVref+ should be
positive with respect to AVref–, and the input voltage (Vin) should be
between AVref+ and AVref–. If the analog input voltage range is from
2V to 4V, then 10-bit resolution can be obtained over this range if
AVref+ = 4V and AVref– = 2V.
The result can always be calculated from the following formula:
Result 1024VINAVrefref AVref
Power Reduction ModesThe 8XC552 has two reduced power modes of operation: the idle
mode and the power-down mode. These modes are entered by
setting bits in the PCON special function register. When the 8XC552
enters the idle mode, the following functions are disabled:
CPU (halted)
Timer T2 (halted and reset)
PWM0, PWM1 (reset; outputs are high)
ADC (may be enabled for operation in Idle mode
by setting bit AIDC (AUXR1.6) ).
In idle mode, the following functions remain active:
Timer 0
Timer 1
Timer T3
SIO0 SIO1
External interrupts
When the 8XC552 enters the power-down mode, the oscillator is
stopped. The power-down mode is entered by setting the PD bit in
the PCON register. The PD bit can only be set if the EW input is tied
HIGH.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 24. A/D Input: Equivalent Circuit
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
InterruptsThe 8XC552 has fifteen interrupt sources, each of which can be
assigned one of four priority levels. The five interrupt sources
common to the 80C51 are the external interrupts (INT0 and INT1),
the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O
interrupt (RI or TI). In the 8XC552, the standard serial interrupt is
called SIO0.
The eight Timer T2 interrupts are generated by flags CTI0-CT13,
CMI0-CMI2, and by the logical OR of flags T2OV and T2BO. Flags
CTI0 to CT13 are set by input signals CT0I to CT3i. Flags CMI0 to
CMI2 are set when a match occurs between Timer T2 and the
compare registers CM0, CM1, and CM2. When an 8-bit or 16-bit
overflow occurs, flags T2BO and T2OV are set, respectively. These
nine flags are not cleared by hardware and must be reset by
software to avoid recurring interrupts.
The ADC interrupt is generated by the ADCI flag in the ADC control
register (ADCON). This flag is set when an ADC conversion result is
ready to be read. ADCI is not cleared by hardware and must be
reset by software to avoid recurring interrupts.
The SIO1 (I2C) interrupt is generated by the SI flag in the SIO1
control register (S1CON). This flag is set when S1STA is loaded
with a valid status code.
The ADCI flag may be reset by software. It cannot be set by
software. All other flags that generate interrupts may be set or
cleared by software, and the effect is the same as setting or
resetting the flags by hardware. Thus, interrupts may be generated
by software and pending interrupts can be canceled by software.
Interrupt Enable Registers: Each interrupt source can beindividually enabled or disabled by setting or clearing a bit in the
interrupt enable special function registers IEN0 and IEN1. All
interrupt sources can also be globally enabled or disabled by setting
or clearing bit EA in IEN0. The interrupt enable registers are
described in Figures 26 and 27.
There are 3 SFRs associated with each of the four-level interrupts.
They are the IENx, IPx, and IPxH. (See Figures 28, 29, and 30.) The
IPxH (Interrupt Priority High) register makes the four-level interrupt
structure possible.
The function of the IPxH SFR is simple and when combined with the
IPx SFR determines the priority of each interrupt. The priority of
each interrupt is determined as shown in the following table:
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Figure 26. Interrupt Enable Register (IEN0)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.
Figure 27. Interrupt Enable Register (IEN1)
Figure 28. Interrupt Priority Register (IP0)
Figure 29. Interrupt Priority Register High (IP0H)
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 30. Interrupt Priority Register (IP1)
Figure 31. Interrupt Priority Register High (IP1H)
Table 3. Interrupt Priority Structure
Table 4. Interrupt Vector Addresses
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
SIO1, I2C Serial I/O: The I2 C bus uses two wires (SDA and SCL) to
transfer information between devices connected to the bus. The
main features of the bus are: Bidirectional data transfer between masters and slaves Multimaster bus (no central master) Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates
to communicate via one serial bus Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer The I2C bus may be used for test and diagnostic purposes
The output latches of P1.6 and P1.7 must be set to logic 1 in order
to enable SIO1.
The 8XC552 on-chip I2 C logic provides a serial interface that meets
the I2 C bus specification and supports all transfer modes (other than
the low-speed mode) from and to the I2 C bus. The SIO1 logic
handles bytes transfer autonomously. It also keeps track of serial
transfers, and a status register (S1STA) reflects the status of SIO1
and the I2 C bus.
The CPU interfaces to the I2 C logic via the following four special
function registers: S1CON (SIO1 control register), S1STA (SIO1
status register), S1DAT (SIO1 data register), and S1ADR (SIO1
slave address register). The SIO1 logic interfaces to the external I2C
bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA
(serial data line).
A typical I2 C bus configuration is shown in Figure 32, and Figure 33
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I2 C bus: Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
Modes of Operation: The on-chip SIO1 logic may operate in thefollowing four modes: Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first byte transmitted contains the slave address
of the receiving device (7 bits) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer. Master Receiver Mode:
The first byte transmitted contains the slave address of the
transmitting device (7 bits) and the data direction bit. In this case
the data direction bit (R/W) will be logic 1, and we say that an “R”
is transmitted. Thus the first byte transmitted is SLA+R. Serial
data is received via P1.7/SDA while P1.6/SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is
received, an acknowledge bit is transmitted. START and STOP
conditions are output to indicate the beginning and end of a
serial transfer. Slave Receiver Mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit. Slave Transmitter Mode:
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 32. Typical I2 C Bus Configuration
Figure 33. Data Transfer on the I2C Bus
SIO1 Implementation and Operation: Figure 34 shows how theon-chip I2 C bus interface is implemented, and the following text
describes the individual blocks.
INPUT FILTERS AND OUTPUT STAGES
The input filters have I2 C compatible input levels. If the input voltage
is less than 1.5V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (fOSC/4), and
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3mA at VOUT < 0.4V. These open drain outputs do not have
clamping diodes to VDD. Thus, if the device is connected to the I2C
bus and VDD is switched off, the I2C bus is not affected.
ADDRESS REGISTER, S1ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
COMPARATOR
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
SHIFT REGISTER, S1DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 34. I2C Bus Serial Interface Block Diagram
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
ARBITRATION AND SYNCHRONIZATION LOGIC
In the master transmitter mode, the arbitration logic checks that
every transmitted logic 1 actually appears as a logic 1 on the I2C
bus. If another device on the bus overrules a logic 1 and pulls the
SDA line low, arbitration is lost, and SIO1 immediately changes from
master transmitter to slave receiver. SIO1 will continue to output
clock pulses (on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while SIO1 is returning a “not
acknowledge: (logic 1) to the bus. Arbitration is lost when another
device on the bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIO1 generates no further clock pulses.
Figure 35 shows the arbitration procedure.
The synchronization logic will synchronize the serial clock generator
with the clock pulses on the SCL line from another device. If two or
more master devices generate clock pulses, the “mark” duration is
determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the
longest “spaces.” Figure 36 shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus
master. The space duration may also be stretched for handshaking
purposes. This can be done after each bit or after a complete byte
transfer. SIO1 will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been
transferred. The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
Figure 35. Arbitration Procedure
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
SERIAL CLOCK GENERATOR
This programmable clock pulse generator provides the SCL clock
pulses when SIO1 is in the master transmitter or master receiver
mode. It is switched off when SIO1 is in a slave mode. The
programmable output clock frequencies are: fOSC/120, fOSC/9600,
and the Timer 1 overflow rate divided by eight. The output clock
pulses have a 50% duty cycle unless the clock generator is
synchronized with other SCL clock sources as described above.
TIMING AND CONTROL
The timing and control logic generates the timing and control signals
for serial byte handling. This logic block provides the shift pulses for
S1DAT, enables the comparator, generates and detects start and
stop conditions, receives and transmits acknowledge bits, controls
the master and slave modes, contains interrupt request logic, and
monitors the I2C bus status.
CONTROL REGISTER, S1CON
This 7-bit special function register is used by the microcontroller to
control the following SIO1 functions: start and restart of a serial
transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
STATUS DECODER AND STATUS REGISTER
The status decoder takes all of the internal status bits and
compresses them into a 5-bit code. This code is unique for each I2C
bus status. The 5-bit code may be used to generate vector
addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26
possible bus states if all four modes of SIO1 are used. The 5-bit
status code is latched into the five most significant bits of the status
register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The
three least significant bits of the status register are always zero. If
the status code is used as a vector to service routines, then the
routines are displaced by eight address locations. Eight bytes of
code is sufficient for most of the service routines (see the software
example in this section).
The Four SIO1 Special Function Registers: The microcontrollerinterfaces to SIO1 via four special function registers. These four
SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described
individually in the following sections.
The Address Register, S1ADR: The CPU can read from and writeto this 8-bit, directly addressable SFR. S1ADR is not affected by the
SIO1 hardware. The contents of this register are irrelevant when
SIO1 is in a master mode. In the slave modes, the seven most
significant bits must be loaded with the microcontroller’s own slave
address, and, if the least significant bit is set, the general call
address (00H) is recognized; otherwise it is ignored.
S1ADR (DBH) 65 4 3 2 1 0The most significant bit corresponds to the first bit received from the
I2C bus after a start condition. A logic 1 in S1ADR corresponds to a
high level on the I2C bus, and a logic 0 corresponds to a low level
on the bus.
The Data Register, S1DAT: S1DAT contains a byte of serial data tobe transmitted or a byte which has just been received. The CPU can
read from and write to this 8-bit, directly addressable SFR while it is
not in the process of shifting a byte. This occurs when SIO1 is in a
defined state and the serial interrupt flag is set. Data in S1DAT
remains stable as long as SI is set. Data in S1DAT is always shifted
from right to left: the first bit to be transmitted is the MSB (bit 7), and,
after a byte has been received, the first bit of received data is
located at the MSB of S1DAT. While data is being shifted out, data
on the bus is simultaneously being shifted in; S1DAT always
contains the last data byte present on the bus. Thus, in the event of
lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in S1DAT.
S1DAT (DAH) 65 4 3 2 1 0
shift directionSD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in S1DAT
corresponds to a high level on the I2C bus, and a logic 0
corresponds to a low level on the bus. Serial data shifts through
S1DAT from right to left. Figure 37 shows how data in S1DAT is
serially transferred to and from the SDA line.
S1DAT and the ACK flag form a 9-bit shift register which shifts in or
shifts out an 8-bit byte, followed by an acknowledge bit. The ACK
flag is controlled by the SIO1 hardware and cannot be accessed by
the CPU. Serial data is shifted through the ACK flag into S1DAT on
the rising edges of serial clock pulses on the SCL line. When a byte
has been shifted into S1DAT, the serial data is available in S1DAT,
and the acknowledge bit is returned by the control logic during the
ninth clock pulse. Serial data is shifted out from S1DAT via a buffer
(BSD7) on the falling edges of clock pulses on the SCL line.
When the CPU writes to S1DAT, BSD7 is loaded with the content of
S1DAT.7, which is the first bit to be transmitted to the SDA line (see
Figure 38). After nine serial clock pulses, the eight bits in S1DAT will
have been transmitted to the SDA line, and the acknowledge bit will
be present in ACK. Note that the eight transmitted bits are shifted
back into S1DAT.
The Control Register, S1CON: The CPU can read from and writeto this 8-bit, directly addressable SFR. Two bits are affected by the
SIO1 hardware: the SI bit is set when a serial interrupt is requested,
and the STO bit is cleared when a STOP condition is present on the
I2C bus. The STO bit is also cleared when ENS1 = “0”.
S1CON (D8H) 65 4 3 2 1 0ENS1, THE SIO1 ENABLE BIT
ENS1 = “0”: When ENS1 is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO1
is in the “not addressed” slave state, and the STO bit in S1CON is
forced to “0”. No other bits are affected. P1.6 and P1.7 may be used
as open drain I/O ports.
ENS1 = “1”: When ENS1 is “1”, SIO1 is enabled. The P1.6 and P1.7
port latches must be set to logic 1.
ENS1 should not be used to temporarily release SIO1 from the I2C
bus since, when ENS1 is reset, the I2C bus status is lost. The AA
flag should be used instead (see description of the AA flag in the
following text).
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
Figure 37. Serial Input/Output Configuration
Figure 38. Shift-in and Shift-out TimingIn the following text, it is assumed that ENS1 = “1”.
STA, THE START FLAG
STA = “1”: When the STA bit is set to enter a master mode, the SIO1
hardware checks the status of the I2C bus and generates a START
condition if the bus is free. If the bus is not free, then SIO1 waits for
a STOP condition (which will free the bus) and generates a START
condition after a delay of a half clock period of the internal serial
clock generator.
STA = “0”: When the STA bit is reset, no START condition or
repeated START condition will be generated.
STO, THE STOP FLAG
STO = “1”: When the STO bit is set while SIO1 is in a master mode,
a STOP condition is transmitted to the I2C bus. When the STOP
condition is detected on the bus, the SIO1 hardware clears the STO
flag. In a slave mode, the STO flag may be set to recover from an
error condition. In this case, no STOP condition is transmitted to the
I2C bus. However, the SIO1 hardware behaves as if a STOP
Philips Semiconductors Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2 C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I2 C bus if SIO1 is in a master mode (in a slave
mode, SIO1 generates an internal STOP condition which is not
transmitted). SIO1 then transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated.
SI, THE SERIAL INTERRUPT FLAG
SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible SIO1 states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA, THE ASSERT ACKNOWLEDGE FLAG
AA = “1”: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line
when: The “own slave address” has been received The general call address has been received while the general call
bit (GC) in S1ADR is set A data byte has been received while SIO1 is in the master
receiver mode A data byte has been received while SIO1 is in the addressed
slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on SCL
when: A data has been received while SIO1 is in the master receiver
mode A data byte has been received while SIO1 is in the addressed
slave receiver mode
When SIO1 is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 42).
When SI is cleared, SIO1 leaves state C8H, enters the not
addressed slave receiver mode, and the SDA line remains at a high
level. In state C8H, the AA flag can be set again for future address
recognition.
When SIO1 is in the not addressed slave mode, its own slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, SIO1 can be temporarily released from the I2C bus while the
bus status is monitored. While SIO1 is released from the bus,
START and STOP conditions are detected, and serial data is shifted
in. Address recognition can be resumed at any time by setting the
AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will
be recognized at the end of the byte transmission.
CR0, CR1, AND CR2, THE CLOCK RATE BITS
These three bits determine the serial clock frequency when SIO1 is
in a master mode. The various serial rates are shown in Table 5.
A 12.5kHz bit rate may be used by devices that interface to the I2C
bus via standard I/O port lines which are software driven and slow.
100kHz is usually the maximum bit rate and can be derived from a
16MHz, 12MHz, or a 6MHz oscillator. A variable bit rate (0.5kHz to
62.5kHz) may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
The frequencies shown in Table 5 are unimportant when SIO1 is in a
slave mode. In the slave modes, SIO1 will automatically synchronize
with any clock frequency up to 100kHz.
The Status Register, S1STA: S1STA is an 8-bit read-only specialfunction register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
Table 5. Serial Clock Rates
NOTES: These frequencies exceed the upper limit of 100kHz of the I2 C-bus specification and cannot be used in an I2 C-bus application.
