P87C51MB2BA ,80C51 8-bit microcontroller family with extended memory
P87C51MB2BA ,80C51 8-bit microcontroller family with extended memoryfeatures 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbyt ..
P87C51MB2BA ,80C51 8-bit microcontroller family with extended memoryGENERAL DESCRIPTIONThe P87C51Mx2 represents the first microcontroller based on Philips Semiconducto ..
P87C51MC2BA ,80C51 8-bit microcontroller family with extended memoryINTEGRATED CIRCUITSSEE THE LAST 2 PAGES OF THIS DATA SHEET FOR A LIST OF ERRATA RELATED TO THIS PAR ..
P87C51RA+4A ,80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHzapplications that require pulse width modulation, high-speed I/O andup/down counting capabilities s ..
P87C51RA+4B ,80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHzfeatures make it an even more powerful microcontroller for
PCA9502BS ,8-bit I/O expander with I2C-bus/SPI interfaceApplicationsn Factory automation and process controln Portable and battery operated devicesn Cellul ..
PCA9504A ,Glue chip 4
PCA9504A ,Glue chip 4
PCA9505DGG ,40-bit I2C-bus I/O port with RESET, OE and INTapplications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sour ..
PCA9506BS ,40-bit I2C-bus I/O port with RESET, OE and INTFeatures and benefits2 Standard mode (100 kHz) and Fast mode (400 kHz) compatible I C-bus serial i ..
PCA9506DGG ,40-bit I2C-bus I/O port with RESET, OE and INTApplications Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gami ..
P87C51MB2BA-P87C51MC2BA
80C51 8-bit microcontroller family with extended memory
Preliminary specification 2001 Apr 06
GENERAL DESCRIPTIONThe P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2
features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2
Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI.
Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of
program memory and 8Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use
80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits
(ASICs).
The P87C51Mx2 provides greater functionality, increased performance and overall lower system cost. By offering an embedded
memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for
software work-arounds. The increased program memory enables design engineers to develop more complex programs in a high-level language like C, for example, without struggling to contain the program within the traditional 64 Kbytes of program memory.
These enhancements also greatly improve C Language efficiency for code size below 64 Kbytes.
The 51MX core is described in more details in the 51MX Architecture Reference.
KEY FEATURES Extended features of the 51MX Core: 23-bit program memory space and 23-bit data memory space - linear program and data address range expanded to sup-
port up to 8 Mbytes each- Program counter expanded to 23 bits Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces. 100% binary compatibility with the classic 80C51 so that existing code is completely reusable Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 Kbytes or 64 Kbytes of on-chip OTP 3 Kbytes or 2 Kbytes of on-chip RAM Programmable Counter Array (PCA) Two full-duplex enhanced UARTs Industry-standard Serial Peripheral Interface (SPI)
KEY BENEFITS Increases program/data address range to 8 Mbytes each Enhances performance and efficiency for C programs Fully 80C51-compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs Supported by 80C51 development and programming tools (Keil, Nohau, BP Micro, etc.) The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market
COMPLETE FEATURES Fully static Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 Kbytes or 64 Kbytes of on-chip OTP 3 Kbytes or 2 Kbytes of on-chip RAM 23-bit program memory space and 23-bit data memory space Four-level interrupt priority 34 I/O lines (5 ports) Three Timers: Timer0, Timer1 and Timer2 Two full-duplex enhanced UARTs with baud rate generator Framing error detection Automatic address recognition Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to 6 Mbits/sec Power control modes Clock can be stopped and resumed Idle mode Power down mode Second DPTR register Asynchronous port reset Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules Low EMI (inhibit ALE) Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)
ORDERING INFORMATION
LOGIC SYMBOL
PIN CONFIGURATION Pins 1, 12, 23, 34 were not internally connected in some derivatives. Please refer to section on Pin Descriptions for details.
BLOCK DIAGRAM
PIN DESCRIPTIONS
SPECIAL FUNCTION REGISTERS
Note: Special Function Register (SFR) accesses are restricted in the following ways: User must NOT attempt to access any SFR locations not defined.2. SFR bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows: ’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may
be used in future derivatives.- ’0’ MUST be written with ’0’, and will return a ’0’ when read. ’1’ MUST be written with ’1’, and will return a ’1’ when read.
Special Function Registers
Special Function Registers (Continued)
Special Function Registers (Continued)
Notes: SFRs are bit addressable.# SFRs are modified from or added to the 80C51 SFRs. Extended SFRs accessed by preceeding the instruction with 51MX escape (opcode A5h). Reserved bits, must be written with 0’s.& Power on reset is 10H. Other reset is 00H. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ’0’. If any of them is written if BRGEN = 1, result is
unpredictable.% The unimplemented bits (labeled ’-’) in the SFRs are ’X’s (unknown) at all times. ’1’s should NOT be written to these bits, as
they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are
unknown when read.
Special Function Registers (Continued)
FUNCTIONAL DESCRIPTIONThe following paragraphs briefly describe the features of the P87C51Mx2. For more detailed information, please refer to the
P87C51Mx2 User Manual or the 51MX Architecture Reference.
INTERRUPTSTable 1 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, and whether each
interrupt may wake up the CPU from Power Down mode.
DATA RAMThe P87C51MB2 and P87C51MC2 have 2 Kbytes and 3 K bytes of on-chip RAM respectively. Usages of the different data
PORT 4The P87C51Mx2 has a fifth I/O port (Port 4) that is shared with the second UART pins (RXD1 and TXD1) and two of the SPI pins
(MISO and SS). This port is also bit addressable and can be accessed in the same manner as any other ports, except that the
associated SFR is in the extended SFR space. Accesses to this SFR space is the same as those to the conventional SFR space except that the instructions must be preceeded by an escape code (A5h), as described in the 51MX Architecture Reference.
LOW POWER MODESThe P87C51Mx2 supports the standard 51MX low power modes - Stop Clock Mode, Idle Mode and Power-Down Mode.
The PCON register is the same as the standard 51MX PCON register. Note that bits PCON.7 and PCON.6 are for UART configurations (see section "UARTs").
ONCE™ MODEThe ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed
from the circuit. It is supported in the P87C51Mx2.
PERIPHERALSThe P87C51Mx2 peripherals are described in more detail in the User Manual. The on-chip peripherals include: Timers: Timers 0 and 1. Timer 2.
Note: When Timer 1 or Timer 2 can only be used as a baud rate generator for UART 0, but not for UART 1. Two enhanced UARTs with an independent Baud Rate Generator - The section "UARTs" provides information regarding the two UARTs.
Note: UART 1 shares the RXD1 and TXD1 with the SPI pins. The SPEN (SPCTL.6) bit must be cleared ’0’ (reset value) to enable UART 1 operation. Serial Peripheral Interface (SPI). Note: The SPI shares pins with the UART 1 shares the RXD1 and TXD1 with the SPI pins. The SPEN (SPCTL.6) bit must be set to ’1’ to enable SPI operation. Watchdog Timer. Programmable Counter Array (PCA).
UARTSP87C51Mx2 includes two enhanced UART ports with one independent Baud Rate Generator: UART 0 is the standard 51MX enhanced UART as described in the User Manual. It can be selected to use Timer1 overflow,
Timer2 overflow or the independent Baud Rate Generator. UART 1 only uses the independent Baud Rate Generator to generate its baud rate. It has the same baud rate for both
transmission and reception. The Baud Rate Generator is described in the User Manual.
PCON.7 and PCON.6 SFR BitsThe PCON.7 and PCON.6 SFR bits configure the UARTs as follows: PCON.7 (SMOD1) - Baud Rate Control bit for serial port 0. When 0, the baud rate for UART 0 will be the input rate (T1 timer or baud rate generator, as determined by the BRGCON extended SFR) divided by two. When 1, the baud rate for UART 0 will
be the input rate (T1 timer or baud rate generator). UART 1 is not affected by this bit PCON.6 (SMOD0) - Framing Error Location: When 0, bit 7 of S0CON and S1CON will function as SM0 for UARTs 0 and 1 respectively. When 1, bit 7 of S0CON and S1CON will be used for framing error status for UART 0 and 1 respectively. PCON.6 also determines when the UART receive interrupts RI_0 and RI_1 occur in UART modes 2 or 3. (Refer to User
Manual for details.)
Table 3: UARTs 0 and 1 SFRs.
Baud Rate SelectionUART 0 and UART 1 selects the baud rate differently as shown in Tables 4 and 5:
Transmit Baud Rate Selection
Table 5: Baud Rate Generation for UART 1.
SECURITY BITSThe P87C51Mx2 has security bits to protect users’ firmware codes. With none of the security bits programmed, the code in the
program memory can be verified. With only security bit 1 (see Table 6) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further
programming of EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is
disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.
