P82B96TD ,Dual bidirectional bus bufferApplications2n Interface between I C-buses operating at different logic levels (for example, 5 V an ..
P82C215 , NEW ENHANCED AT DATA BOOK
P82C55A , CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
P8397BH , COMMERCIAL/EXPRESS HMOS MICROCONTROLLER
P8398 , COMMERCIAL/EXPRESS HMOS MICROCONTROLLER
P83C51FB-4B ,80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHzFEATURESThree different Single-Chip 8-Bit Microcontroller families are• 80C51 Central Processing Un ..
PCA2002T ,32 kHz watch circuit with programmable output period and pulse width
PCA2125 , SPI Real time clock / calendar
PCA24S08ADP ,1024 x 8-bit CMOS EEPROM with access protectionGeneral descriptionThe PCA24S08A provides 8192 bits of serial Electrically Erasable and Programmabl ..
PCA24S08D ,PCA24S08; 1024 x 8-bit CMOS EEPROM with access protection
PCA24S08DP ,1024 ?8-bit CMOS EEPROM with access protection
PCA24S08DP ,1024 ?8-bit CMOS EEPROM with access protection
P82B96TD
Dual bidirectional bus buffer
General descriptionThe P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface
between the normal I2 C-bus and a range of other bus configurations. It can interface2 C-bus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350 μA SMBus, to 3.3 V logic devices, and to 15V
levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I2 C-bus protocols or clock
speed. The IC adds minimal loading to the I2 C-bus node, and loadings of the new bus or
remote I2 C-bus nodes are not transmitted or transformed to the local node. Restrictions
on the number of I2 C-bus devices in a system, or the physical separation between them,
are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission
lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals may be directly
connected, without causing latching,to providean alternative bidirectional signal line with2 C-bus properties.
Features Bidirectional data transfer of I2 C-bus signals Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side Tx/T y outputs have 60 mA sink capability for driving low-impedance or high capacitive
buses 400 kHz operation over at least 20 meters of wire (see AN10148) Supply voltage range of 2 V to 15 V with I2 C-bus logic levels on Sx/Sy side
independent of supply voltage Splits I2 C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths. Low power supply current ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400V
SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up free (bipolar process with no latching structures) Packages offered: DIP8, SO8 and TSSOP8
P82B96
Dual bidirectional bus buffer
Rev. 08 — 10 November 2009 Product data sheet
NXP Semiconductors P82B96
Dual bidirectional bus buffer Applications Interface between I2 C-buses operating at different logic levels (for example, 5 V and V or 15V) Interface between I2 C-bus and SMBus (350 μA) standard Simple conversion of I2 C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250 Interfaces with opto-couplers to provide opto-isolation between I2 C-bus nodes up to
400 kHz
Ordering information
4.1 Ordering options
Table 1. Ordering informationP82B96DP TSSOP8 plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
P82B96PN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
P82B96TD SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
P82B96TD/S900 SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
Table 2. Ordering optionsP82B96DP 82B96 −40 °C to +85°C
P82B96PN P82B96PN −40 °C to +85°C
P82B96TD P82B96T −40 °C to +85°C
P82B96TD/S900 P82B96T −40 °C to +125°C
NXP Semiconductors P82B96
Dual bidirectional bus buffer Block diagram Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description 1 I2 C-bus (SDA or SCL) 2 receive signal 3 transmit signal
GND 4 negative supply 5 transmit signal 6 receive signal 7 I2 C-bus (SDA or SCL)
VCC 8 positive supply voltage
NXP Semiconductors P82B96
Dual bidirectional bus buffer Functional descriptionRefer to Figure 1 “Block diagram of P82B96”.
The P82B96 has two identical buffers allowing buffering of both of the I2 C-bus (SDA and
SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the2 C-bus interface pin which drives the buffered bus, and a reverse signal path from the
buffered bus input to drive the I2 C-bus interface. Thus these paths are:
sense the voltage stateof theI2 C-bus pin Sx (or Sy) and transmit this stateto the pin
Tx (Ty respectively), and
sense the state of the pin Rx (Ry) and pull the I2 C-bus pin LOW whenever Rx (Ry) is
LOW.
The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is
identical.
The I2 C-bus pin (Sx) is designed to interface with a normal I2 C-bus.
The logic threshold voltage levels on the I2 C-bus are independent of the IC supply VCC.
The maximum I2 C-bus supply voltage is 15 V and the guaranteed static sink current is mA.
The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic
LOWis below42%of VCC, and logic HIGHis above58%of VCC (witha typical switching
threshold of half VCC).isan open-collector output without ESD protection diodesto VCC.It maybe connected
viaa pull-up resistortoa supply voltagein excessof VCC,as longas the15V ratingis not
exceeded. It has a larger current sinking capability than a normal I2 C-bus device, being
ableto sinka static currentof greater than30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is only transmitted to Tx when the voltage at the I2 C-bus pin (Sx) is below
0.6 V. A logic LOW at Rx will cause the I2 C-bus (Sx) to be pulled to a logic LOW level in
accordance with I2 C-bus requirements (maximum 1.5 V in 5 V applications) but not low
enough to be looped back to the Tx output and cause the buffer to latch LOW.
The minimum LOW level this chip can achieve on the I2 C-bus by a LOW at Rx is typically
0.8V. the supply voltage VCC fails, then neither theI2 C-bus nor theTx output willbe held LOW.
Their open-collector configuration allows them to be pulled up to the rated maximum of V even without VCC present. The input configuration on Sx and Rx also present no
loading of external signals even when VCC is not present.
The effective input capacitanceof any signal pin, measuredbyits effecton bus rise times,
is less than 7 pF for all bus voltages and supply voltages including VCC =0V.
Remark:T wo or more Sx or Sy I/Os must not be interconnected. The P82B96 design
does not support this configuration. Bidirectional I2 C-bus signals do not allow any
direction control pin so, instead, slightly different logic low voltage levels are usedat Sx/Sy
to avoid latching of this buffer. A ‘regular I2 C-bus LOW’ applied at the Rx/Ry of a P82B96
will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this
NXP Semiconductors P82B96
Dual bidirectional bus bufferspecial ‘buffered LOW’is appliedto the Sx/Syof another P82B96 that second P82B96 will
not recognize it as a ‘regular I2 C-bus LOW’ and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The
Sx/Sy side is only intended for, and compatible with, the normal I2 C-bus logic voltage
levels of I2 C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if
required. The Tx/Rx and Ty/Ry I/O pins use the standardI2 C-bus logic voltage levelsofall2 C-bus parts. There are
no restrictionson the interconnectionof the Tx/Rx and Ty/Ry I/O
pinsto other P82B96s,for exampleina staror multipoint configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave
devices. For more details see Application Note AN255.
Limiting values[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
VCC supply voltage VCC to GND −0.3 +18 V
VSx voltage on pin Sx I2 C-bus SDA or SCL −0.3 +18 V
VTx voltage on pin Tx buffered output [1] −0.3 +18 V
VRx voltage on pin Rx receive input [1] −0.3 +18 V current on any pin - 250 mA
Ptot total power dissipation - 300 mW junction temperature operating range
P82B96TD/S900
−40 +125 °C
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors P82B96
Dual bidirectional bus buffer Characteristics
Table 5. CharacteristicsTamb= +25 °C; voltages are specified with respect to GND with VCC=5 V, unless otherwise specified.
Power supplyVCC supply voltage operating 2.0 - 15 2.0 15 V
ICC supply current buses HIGH - 0.9 1.8 - 3 mA
VCC =15V;
buses HIGH 1.1 2.5 - 4 mA
ΔICC additional quiescent
supply current
per Tx or Ty LOW - 1.7 3.5 - 3.5 mA
Bus pull-up (load) voltages and currentsVSx, VSy maximum input/output
voltage
open-collector;2 C-bus andVRx,VRy=
HIGH 15 - 15 V
ISx, ISy static output loading on2 C-bus
VSx, VSy= 1.0V;
VRx,VRy =LOW
[2] 0.2 - 3 0.2 3 mA
ISx, ISy dynamic output sink
capability on I2 C-bus
VSx, VSy =2V;
VRx,VRy =LOW
718 - 7 - mA
ISx, ISy leakage current on2 C-bus
VSx, VSy =5V;
VRx,VRy= HIGH 1 - 10 μA
VSx, VSy =15V;
VRx,VRy= HIGH
-1- - 10 μA
VTx, VTy maximum outputvoltage
level
open-collector - - 15 - 15 V
ITx, ITy static output loading on
buffered bus
VTx, VTy= 0.4V;
VSx,VSy= LOW on2 C-bus= 0.4V - 30 - 30 mA
ITx, ITy dynamic output sink
capability, buffered bus
VTx, VTy >1V;
VSx,VSy= LOW on2 C-bus= 0.4V 100 - 60 - mA
ITx, ITy leakage current on
buffered bus
VTx, VTy =VCC =15V;
VSx, VSy= HIGH
-1- - 10 μA
Input currentsISx, ISy input current from2 C-bus
bus LOW;
VRx,VRy= HIGH −1- - −10 μA
IRx, IRy input current from
buffered bus
bus LOW;
VRx,VRy= 0.4V −1- - −10 μA
IRx, IRy leakage current on
buffered bus input
VRx, VRy =VCC -1- - 10 μA
Output logic LOW levelVSx, VSy output logic level LOW
on normal I2 C-bus
ISx, ISy =3mA [3] 0.8 0.88 1.0 (see Figure 6)V
ISx, ISy= 0.2 mA [3] 670 730 790 (see Figure 5)mV
dVSx/dT,
dVSy/dT
temperature coefficient
of output LOW levels
ISx, ISy= 0.2 mA [3] - −1.8 - - - mV/K
NXP Semiconductors P82B96
Dual bidirectional bus buffer
Input logic switching threshold voltagesVSx, VSy input logic voltage LOW on normal I2 C-bus [4] - 640 600 (see Figure 7)mV
VSx, VSy input logic level HIGH
threshold
on normal I2 C-bus [4] 700 650 - (see Figure 8)mV
dVSx/dT,
dVSy/dT
temperature coefficient
of input thresholds −2 - - - mV/K
VRx, VRy input logic HIGH level fraction of applied VCC 0.58VCC - - 0.58VCC -V
VRx, VRy input threshold fraction of applied VCC - 0.5VCC -- - V
VRx, VRy input logic LOW level fraction of applied VCC - - 0.42VCC - 0.42VCCV
Logic level threshold differenceVSx, VSy input/output logic level
difference
VSx output LOW at
0.2 mA− VSx input
HIGH maximum
[2] 50 85 - 50 - mV
Thermal resistanceRth(j-pcb) thermal resistance from
junctionto printed-circuit
board
SOT96-1 (SO8);
average lead
temperature at board
interface 127 - - - K/W
Bus release on VCC failureVSx, VSy,
VTx, VTy
VCC voltage at which all
buses are guaranteedto
be released - 1 (see Figure 9)V
dV/dT temperature coefficient
of guaranteed release
voltage −4 - - - mV/K
Buffer response time[5]Tfall delay
VSxtoVTx,
VSy to VTy
buffer time delay on
falling input betweenVSx= input switching
threshold, and VTx
output falling 50%
RTx pull-up= 160Ω; capacitive load;
VCC =5V
-70- - - ns
Trise delay
VSxtoVTx,
VSy to VTy
buffer time delay on
rising input betweenVSx= input switching
threshold, and VTx
output reaching 50%
VCC
RTx pull-up= 160Ω; capacitive load;
VCC =5V
-90- - - ns
Table 5. Characteristics …continuedTamb= +25 °C; voltages are specified with respect to GND with VCC=5 V, unless otherwise specified.
NXP Semiconductors P82B96
Dual bidirectional bus buffer[1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.
[2] The minimum value requirementfor pull-up current, 200μA, guarantees thatthe minimum valuefor VSx output LOWwill always exceed
the minimumVSx input HIGH levelto eliminate any possibilityof latching. The specified differenceis guaranteedby designwithin anyIC.
While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because
the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes.
[3] The output logic LOW depends on the sink current. For scaling, see Application Note AN255.
[4] The input logic threshold is independent of the supply voltage.
[5] The fall time of VTx from 5 V to 2.5 V in the test is approximately 15ns.
The fall time of VSx from 5 V to 2.5 V in the test is approximately 50ns.
The rise time of VTx from 0 V to 2.5 V in the test is approximately 20ns.
The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70ns.
Tfall delay
VRx to
VSx, VRy
to VSy
buffer time delay on
falling input betweenVRx= input switching
threshold, and VSx
output falling 50%
RSx pull-up= 1500Ω; capacitive load;
VCC =5V 250 - - - ns
Trise delay
VRx to
VSx, VRy
to VSy
buffer time delay on
rising input betweenVRx= input switching
threshold, and VSx
output reaching 50%
VCC
RSx pull-up= 1500Ω; capacitive load;
VCC =5V 270 - - - ns
Input capacitance input capacitance effective input
capacitance of any
signal pin measured
by incremental bus
rise times 7 - 7 pF
Table 5. Characteristics …continuedTamb= +25 °C; voltages are specified with respect to GND with VCC=5 V, unless otherwise specified.
NXP Semiconductors P82B96
Dual bidirectional bus buffer
NXP Semiconductors P82B96
Dual bidirectional bus buffer
10. Application informationRefer to AN460 and AN255 for more application detail.
NXP Semiconductors P82B96
Dual bidirectional bus bufferFigure 13 shows how a master I2 C-bus can be protected against short circuits or failures applications that involve plug and socket connections and long cables that may become
damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds
the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its
supply is removed, so one option is to connect its VCC to the output of a logic gate from,
say, the 74LVC family. The SDA and SCL lines could be timed and VCC disabled via the
gate if one or other lines exceeds a design value of ‘LOW’ period as in Figure 28 of
AN255. If the supply voltage of logic gates restricts the choice of VCC supply then the
low-cost discrete circuitin Figure13 canbe used.If the SDA lineis held LOW, the 100nF
capacitor will charge and the Ry input willbe pulled towards VCC. Whenit exceeds 0.5VCC
the Ry input will set the Sy input HIGH, which in practice means simply releasing it. this example the SCL lineis made unidirectionalby tying theRx pinto VCC. The stateof
the buffered SCL line cannot affect the master clock line which is allowed when
clock-stretching is not required. It is simple to add an additional transistor or diode to
control the Rx input in the same way as Ry when necessary. The +V cable drive can be
any voltageupto15V and the bus maybe runata lower impedanceby selecting pull-up
resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the
connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable
lengthis not restrictedto20mby theI2 C-bus signalling, butit maybe limitedby the video
signalling.
NXP Semiconductors P82B96
Dual bidirectional bus bufferFigure 14 shows that P82B96 can achieve high clock rates over long cables. While
calculating with lumped wiring capacitance yields reasonable approximations to actual
timing, even25 metersof cableis better treated using transmission line theory. Flat ribbon
cables connected as shown, with the bus signals on the outer edge, will have a
characteristic impedance in the range 100 Ω to 200 Ω. For simplicity they cannot be
terminated in their characteristic impedance but a practical compromise is to use the
minimum pull-up allowed for P82B96 and place half this termination at each end of the
cable. When each pull-up is below 330 Ω, the rising edge waveforms have their first
voltage ‘step’ level above the logic threshold at Rx and cable timing calculations can be
based on the fast rise/fall times of resistive loading plus simple one-way propagation
delays. When the pull-up is larger, but below 750 Ω, the threshold at Rx will be crossed
after one signal reflection. So at the sending end it is crossed after 2 times the one-way
propagation delay and at the receiving end after 3 times that propagation delay. For flat
cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays will be about 5ns per meter. The 10 % to 90 % rise and fall times on
the cable will be between 20 ns and 50 ns, so their delay contributions are small. There
will be ringing on falling edges that can be damped, if required, by using Schottky diodes
as shown.
When the Master SCL HIGH and LOW periods can be programmed separately, for
example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow
for bus delays. The LOW period should be programmed to achieve the minimum 1300ns
plus the net delay in the slave's response data signal caused by bus and buffer delays.
The longest data delay is the sum of the delay of the falling edge of SCL from master to
slave and the delay of the rising edge of SDA from slave data to master. Because the
buffer will ‘stretch’ the programmed SCL LOW period, the actual SCL frequency will be
lower than calculated from the programmed clock periods. In the example for 25 meters
the clockis stretched 400 ns, the falling edgeof SCLis delayed 490ns and the SDA rising
edge is delayed 570 ns. The required additional LOW period is
(490ns+ 570 ns)= 1060 ns and the I2 C-bus specifications already include an allowance
for a worst case bus rise time 0%to70 % of 425 ns. (The bus rise time can be 300ns%to70%, which meansit canbe 425ns0%to70%. The25 meter cable delay times quoted already includeall rise andfall times.) Therefore, the microcontroller only needs
to be programmed with an additional (1060ns− 400ns− 425 ns)= 235 ns, making a
total programmed LOW period 1535 ns. The programmed LOW will the be stretched by
400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH
period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
Note that in both the 100 meter and 250 meter examples, the capacitive loading on the2 C-buses at each end is within the maximum allowed Standard mode loading of 400 pF,
but exceeds the Fast mode limit. Thisisan exampleofa ‘hybrid’ mode becauseit relieson
the response delaysof Fast mode parts but uses (allowable) Standard mode bus loadings
with rise times that contribute significantly to the system delays. The cables cause large
propagation delays, so these systems need to operate well below the 400 kHz limit, but
illustrate how they can still exceed the 100 kHz limit provided all parts are capable of
Fast mode operation. The fastest example illustrates how the 400 kHz limit can be
exceeded, provided masters and slaves have the required timings, namely smaller than
the maximum allowed for Fast mode. Many NXP slaves have delays shorter than 600ns
and all Fm+ devices must be < 450 ns.
NXP Semiconductors P82B96
Dual bidirectional bus buffer
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors P82B96
Dual bidirectional bus buffer
le 6.
Examples of b
us capabilityer to
Figure
n/a(dela
based)
kHz
Nor
mal spec.
kHz par
n/a(dela
based)
kHz
Nor
mal spec.
kHz par
kHz
Nor
mal spec.
kHz par
kHz
600
NXP Semiconductors P82B96
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequency for a Fast mode
system
NXP Semiconductors P82B96
Dual bidirectional bus bufferFigure 15, Figure 16, and Figure17 show the P82B96 usedto drive extended bus wiring,
with relatively large capacitance, linking two Fast mode I2 C-bus nodes. It includes
simplified expressions for making the relevant timing calculations for 3.3 V or 5V
operation. Because the buffers and the wiring introduce timing delays, it may be
necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the
actual bus frequency will be lower than the nominal Master timing due to bit-wise
stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A — The propagation delay of the master signal through the buffers and wiring to the
slave. The important delay is that of the falling edge of SCL because this edge ‘requests’
the data or acknowledge from a slave. See Figure 15.
B — The effective stretching of the nominal LOW period of SCL at the master caused by
the buffer and bus rise times. See Figure 16.
C — The propagation delay of the slave's response signal through the buffers and wiring
back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limitedby the passive pull-up while falling edges are actively driven).
See Figure 17.
The timing requirement in any I2 C-bus system is that a slave's data response (which is
provided in response to a falling edge of SCL) must be received at the master before the
endof the corresponding LOW periodof SCLas appearson the bus wiringat the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of a
400 kHz part, they must provide their response within the minimum allowed clock LOW
period of 1300 ns. Therefore in systems that introduce additional delays it is only
necessaryto extend that minimum clock LOW periodby any ‘effective’ delayof the slave's
response. The effective delayof the slaves response equals the total delaysin SCL falling
