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P82B715TD
I2C-bus extender
General descriptionThe P82B715 is a bipolar IC intended for application in I2 C-bus and derivative bus
systems. While retaining all the operating modes and features of the I2 C-bus it permits
extension of the practical separation distance between components on the I2 C-bus by
buffering both the data (SDA) and the clock (SCL) lines.
The I2 C-bus capacitance limit of 400 pF restricts practical communication distances to a
few meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly)
reduces that cable’s loading on the linked I2 C-buses by a factor of 10 and allows the total
system capacitance load (all devices, cable, connectors, and tracesor wires connectedto
the I2 C-bus) to be around 3000 pF while the loading on each I2 C-bus on the Sx/Sy sides
remains below 400 pF. Longer cablesor low-cost, general-purpose wiring maybe usedto
link I2 C-bus based modules without degrading noise margins. Multiple P82B715s can be
connected together, linking their Lx/Ly ports,ina staror multi-point architectureas longas
the total capacitance of the system is less than about 3000 pF and each bus at an Sx/Sy
connection is well below 400 pF . This configuration, with the master and/or slave devices
attached to the Sx/Sy port of each P82B715, has full multi-master communication
capability. The P82B715 alone does not support voltage level translation, but it can be
simply implemented using low cost transistors when required. There is no restriction on
interconnecting the Sx/Sy I/Os, and, because the device output levels are always held
within 100 mV of input drive levels, P82B715 is compatible with bus buffers that use
voltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96.
The lower VOL level and ability to operate with any master, slave or bus buffer is the
primary advantageof the using the P82B715for long distance busesat the disadvantage
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate
bus capacitance does not allow these devices to operate with other bus buffers with
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise
margin. A proven quick design-in point-to-point/multi-point circuit (Figure 9) is included in
Section 8.2 to allow rapid use of the P82B715 along with comparison waveforms so that
the designer can clearly see the trade-offs between the P82B715 and the
P82B96/PCA9600 and choose the type of device that is best for their application.
Features Dual, bidirectional, unity voltage gain buffer with no external directional control
required Compatible with I2 C-bus and its derivatives SMBus, PMBus, DDC, etc. Logic signal levels may include (but not exceed) both supply and ground Logic signal input voltage levels are output without change and are independentof VCC ×10 impedance transformation, but does not change logic voltage levels
P82B7152 C-bus extender
Rev. 08 — 9 November 2009 Product data sheet
NXP Semiconductors P82B7152 C-bus extender Supply voltage range 3 V to 12V Clock speeds to at least 100 kHz and 400 kHz when other system delays permit ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 and 400 V MM per
JESD22-A115 (I/Os have diodes to VCC and GND) Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Applications Increase the total connected capacitance of an I2 C-bus system to around 3000 pF Drive I2 C-bus signals over long cables to approximately 50 meters or 3000pF Drives ×10 lower impedance bus wiring for improved noise immunity Multi-drop distribution of I2 C-bus signals using low cost twisted-pair cables AdvancedTCA radial IPMB architecture Driving 30 mA Fm+ devices from standard 3 mA parts
Ordering information[1] For applications requiring lower voltage operation, or additional buffer performance, see application notes
AN255, “I2 C/SMBus repeaters, hubs and expanders” and AN10710, “Features and applications of the
P82B715 I2 C-bus extender”.
4.1 Ordering options
Table 1. Ordering information[1]P82B715PN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
P82B715TD SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Table 2. Ordering optionsP82B715PN P82B715PN −40 °C to +85°C
P82B715TD P82B715 −40 °C to +85°C
NXP Semiconductors P82B7152 C-bus extender Block diagram Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin descriptionn.c. 1 not connected 2 buffered bus, LDA or LCL 3 I2 C-bus, SDA or SCL
GND 4 negative supply
n.c. 5 not connected 6 I2 C-bus, SCL or SDA 7 buffered bus, LCL or LDA
VCC 8 positive supply
NXP Semiconductors P82B7152 C-bus extender Functional descriptionThe P82B715 is a dual bidirectional logic signal device having unity voltage gain in both
directions, but ×10 current amplification in one direction that allows increasing the
allowableI2 C-bus system capacitance.It contains identical circuitsfor eachI2 C-bus signal
and requires no external directional control. It uses unidirectional analog current
amplification to increase the current sink capability of I2 C-bus chips by a factor of 10 and
to change the I2 C-bus specification limit of 400 pF to a 4 nF system limit. This allows2 C-bus, or similar bus systems, to be extended over long distances using conventional
cables and without degradation of system performance.
P82B715 provides current amplification from its I2 C-bus to its low-impedance or buffered
bus. Whenever current is flowing out of Sx, into an I2 C-bus chip driving the I2 C-bus LOW,
P82B715 will sink ten times that current into Lx to drive the buffered bus LOW (see
Figure4). minimize interference and ensure stability, the current rise and fall timesof theLx drive
amplifier are internally controlled.
The P82B715 does not amplify signal currents flowing in the other direction, i.e., into Sx
from theI2 C-bus. TheSx pinis driven LOWby current flowing outofLxto the driverof that
buffered side.
The buffered bus logic LOW voltage at Lx simply drives the I2 C-bus at Sx LOW via the
internal 30 Ω resistor. The buffer’s offset voltage (the difference between Sx and Lx)
depends on the current flowing in the sense resistor so it will be very small when the bus
currents are small, but it is guaranteed not to exceed 100 mV in either direction with full
static I2 C-bus loading.
The unity voltage gain, with signal current amplification dependenton direction, preserves
the multi-master, bidirectional, open-collector/open-drain, characteristic of any connected2 C-bus lines and provides these characteristicsto the new low-impedance bus. Bus logic
signal voltage levels will be clamped at (VCC+ 0.7 V), but otherwise are independent of
the supply voltage VCC.
7.1 Sx, Sy: I2 C-bus SDA or SCLOn the normal side, because the two buffer circuits in the P82B715 are identical, either
the Sx or Sy input pins can be used as the I2 C-bus SDA data line, or the SCL clock line.
NXP Semiconductors P82B7152 C-bus extender
7.2 Lx, Ly: buffered bus LDA or LCL the special low-impedanceor buffered line side, the corresponding outputat theLxor
Ly pins becomes the LDA data line or LCL clock line.
7.3 VCC, GND: positive and negative supply pinsThe power supply voltagesat each P82B715 usedina system are normally nominally the
same. If they differ by a significant amount, noise margin may be sacrificed as the bus
HIGH level should not exceed the lowest of those supplies.
Application design-in informationBy using two (or more) P82B715 ICs, a sub-system can be built that retains the interface
characteristics of a normal I2 C-bus device so that the sub-system may be included in, or
added onto, any I2 C-bus or related system.
The sub-system shown in Figure 5 features a low-impedance or buffered bus, capable of
driving large wiring capacitance.
The P82B715 will operate with a supply voltage from 3 V to 12.5 V but the logic signal
levels at Sx/Lx are independent of the chip’s supply. They remain at the levels presented the chipby the attached ICs. The maximum staticI2 C-bus sink current,3 mA, flowingin
either directionin the internal current sense resistor, causesa difference,or offset voltage,
less than 100 mV between the bus logic LOW levels at Sx and Lx. This makes P82B715
fully compatible with all logic signal drivers, including TTL. The P82B715 cannot modify
the bus logic signal voltage levels butit contains internal diodes connected between Lx/Sx
and VCC that will conduct and limit the logic signal swing if the applied logic levels would
have exceeded the supply voltage by more than 0.7 V. In normal applications external
pull-up resistors will pull the connected buses up to the desired voltage HIGH level.
Usually this will be the chip supply, VCC, but for very low logic voltages it is necessary to
use a VCC of at least 3.3 V and preferably even higher. Note that full performance over
temperatureis only guaranteed from 4.5V. Specification de-ratings apply whenits supply
voltage is reduced below 4.5 V. The absolute minimum VCC is 3V.
NXP Semiconductors P82B7152 C-bus extender
8.1I2 C-bus systemsAs in standard I2 C-bus systems, pull-up resistors are required to provide the logic HIGH
levels on the buffered bus. (The standard open-collector configuration is retained.) The
value and number of pull-up resistors used is flexible and depends on the system
requirements and designer preferences. P82B715 ICs aretobe permanently connected intoa systemit couldbe configured with
only one pull-up resistor on the buffered bus and none on the I2 C-buses, but the system
design will be simplified, and performance improved, by fitting separate pull-ups on each
sectionof the bus. Whena sub-system using P82B715 maybe optionally connectedtoan
existing I2 C-bus system that already has a pull-up, then the effects of the sub-system
pull-ups acting in parallel with the existing I2 C-bus pull-up must be considered.
8.1.1 Pull-up resistance calculationWhen calculating the pull-up resistance values, the gain of the buffer introduces scaling
factors which mustbe appliedto the system components.In practical systems the pull-up
resistance value is usually calculated to achieve the rise time requirement of the system.
As an approximation, this requirement will be satisfied for a standard 100 kHz system if
the time constantof the total system (productof the net resistance and net capacitance)is
set to 1 microsecond or less.
In systems using P82B715s, the most convenient way to achieve the total system
rise time requirement is by considering each bus node separately. Each of the I2 C-bus
nodes, and the buffered bus node, is designed by selecting its pull-up resistor to provide
the required rise time by setting its time constant (product of the pull-up resistance and
load capacitance) equalto theI2 C-bus rise time requirement.If each node complies, then
the system requirement will also be met with a small safety margin.
This arrangement, using multiple pull-ups as in Figure 6, provides the best system
performance and allows stand-alone operation of individual I2 C-buses if parts of the
extended system are disconnected or re-connected. For each bus section the pull-up
resistor for a Standard-mode system is calculated as shown in Equation1:
(1)
Where:C device= sumof any connected device capacitances, andC wiring= total wiring
and stray capacitance on the bus section.
Remark: The 1 μs is an approximation, with a safety factor, to the theoretical
time-constant necessary to meet the Standard-mode 1 μs bus rise time specification in a
system with variable logic thresholds where the CMOS limits of 30 % and 70 % of VCC
apply. The actual RC requirement can be shown to be 1.18 μs. For a Fast-mode system,
and the same safety margin, replace the 1 μs with its 300 ns requirement.
If these capacitances cannot be measured or calculated then an approximation can be
made by assuming that each device presents 10 pF of load capacitance and 10 pF of
trace capacitance and that cables range from 50 pF to 100 pF per meter.
If only a single pull-up must be used then it must be placed on the buffered bus (as R2 in
Figure 6) and the associated total system capacitance calculated by combining the
individual bus capacitances into an equivalent capacitive loading on the buffered bus. 1μs device C wiring+ -----------------------------------------------------=
NXP Semiconductors P82B7152 C-bus extenderThis equivalent capacitance is the sum of the capacitance on the buffered bus plus times the sumof the capacitancesonall the connectedI2 C-bus nodes. The calculated
value should not exceed4 nF. The single buffered bus pull-up resistoris then calculatedto
achieve the rise time requirement andit then provides the pull-upfor the buffered bus and
for all other connected I2 C-bus nodes included in the calculation.
8.1.2 Calculating static bus drive currentsFigure 6 shows three P82B715s connected to a common buffered bus. The associated
bus capacitances are omitted for clarity and we assume the pull-up resistors have been
selected to give RC products equal to the bus rise time requirement. An I2 C-bus chip
connectedatI2 C-bus1 and holding the SDA bus LOW must sink the current flowinginits
local pull-up R1 plus, with assistance from the P82B715, the currents in R2, R3 and R4.
When I2 C-bus 1 is LOW, the resistors R3 and R4 act to pull the bus nodes I2 C-bus 2 and2 C-bus3, and their corresponding Sx pins,toa voltage higher than the voltageat theirLx
pins (which are LOW)so their buffer amplifiers willbe inactive. The SDAatSxofI2 C-bus2
and I2 C-bus 3 is pulled LOW by the LOW at Lx via the internal 30 Ω resistor that links Lx Sx.So the effective current that mustbe sunkby the P82B715 bufferonI2 C-bus1,atits
Lx pin, is the sum of the currents in R2, R3 and R4. The Sx current that must be sunk byI2 C-bus chipatI2 C-bus1, dueto the buffer gain action,is1⁄10of theLx current. So the
effective pull-up, determining the currenttobe sunkbyanI2 C-bus chipatI2 C-bus1,is R1
in parallel with resistors 10 times the values of R2, R3 and R4. If R1= R3= R4=10 kΩ,
and R2=1kΩ, the effective pull-up load at I2 C-bus 1 is kΩ||10 kΩ|| 100 kΩ|| 100 kΩ= 4.55 kΩ. (‘||’ means ‘in parallel with’.)
The same calculation applies for I2 C-bus 2 or I2 C-bus3. calculate the current sunkby theLx pinof the bufferatI2 C-bus1, note that the current
in R1 is sunk directly by the IC at I2 C-bus 1. The buffer therefore sinks only the currents
flowing in R2, R3, and R4 so the effective pull-up is R2 in parallel with R3 and R4.
In this example that is 1 kΩ||10 kΩ||10 kΩ= 833 Ω. For a 5.5 V supply and 0.4 V LOW,
that means the buffer is sinking 16.3 mA.
NXP Semiconductors P82B7152 C-bus extenderThe P82B715 has a static sink rating of 30 mA at Lx. The requirement is that the pull-up the buffered bus,in parallel withall other pull-ups thatitis indirectly pulling LOWonSx
pins of other P82B715 ICs, will not cause this 30 mA limit to be exceeded.
The minimum pull-up resistance in a 5V±10 % system is 170Ω.
The general requirement is given in Equation2:
(2)
Where: RPU= parallel combination of all pull-up resistors driven by the Lx pin of the
P82B715.
Figure 7 shows calculations for an expanded Standard-mode I2 C-bus with 3 nF of cable
capacitance.CC max() 0.4V–PU
------------------------------------------ 30 mA<
NXP Semiconductors P82B7152 C-bus extenderFigure 8 shows P82B715 in an analog radial IPMB shelf application.
In this example the total system capacitance is 2800 pF, but it is distributed over 18
different bus sections and no section has a capacitance greater than 200 pF. every individual bus sectionis designedto riseat leastas fastas the IPMB requirement,
then when any driver releases the bus,all bus sections will rise together andno amplifiers
in the P82B715s will be activated or, if one is activated, it can only slow the system bus
rise to its own rate and that has been designed to meet the requirement.
It is then only necessary to calculate the equivalent static bus pull-up loading and to
ensure that it exceeds the specification requirement. The calculated loadings meet the
requirements.
Note thatin this example only oneof the four IPMB linesis shown and the usual switching
arrangementsfor isolatingor cross-connecting bus lines are not shown. The typical offset
(increase in the bus LOW level) measured between any two Sx points in this system is
below 100 mV.
NXP Semiconductors P82B7152 C-bus extender
8.2 Quick design-in point-to-point/multi-point circuit information for 5V
busWith many variables (cable length/capacitance, local capacitive loading on each I2 C-bus,
bus voltages, and bus speed), optimizing a design can be complex and requires
significant study of the application note information. The following circuit and simplified
approach has been checked to provide adequate performance in the typical 100 kHz
application and can be easily implemented by just using the values and circuit shown for
either point-to-point application, up to 30 meters long, or in multiple point applications if
additional nodes need to be added along the way.
Specific information on this circuit implementation:
The pull-up on each I2 C-bus is (VCC− 0.4 V)/1mA=4.6 kΩ, using 4.7 kΩ as the
nearest usual value.
The net pull-up on the cable bus can be (VCC− 0.5V)/ (21−n) mA where= total number of P82B715 modules on the cable. When there are only two
modules, one each end of the cable, the pull-up= (4.5/ 19)= 237 Ω. Make the
pull-ups at each end of the cable equal. Signalling is bidirectional so there is no
advantage optimizing for any one direction. The pull-up at each end will be 474Ω,
using 470 Ω as the nearest usual value.
The 100 kHz rise time requirement is 1 μs. Meeting this requires the product of the
bus capacitance and pull-up resistoron each bus sectiontobe less than 1.18 μs. That
provides one capacitance limit. With 4.7 kΩ pull-ups the I2 C-bus limit is 250 pF each,
while the 235 Ω sets a cable bus limit at 5000 pF.
NXP Semiconductors P82B7152 C-bus extender The 300 ns bus fall time, and the Standard-mode I2 C-bus limit specification limit of
400 pF, must alsobe observed.If the 400pF limitis observed the fall time limit willbe
met. Allocate about1 ⁄3 of this 400 pF limit, or 133 pF, to each I2 C-bus leaving2 ⁄3, or
266 pF , for the cable bus loading as it will appear at the Sx/Sy pins. The ×10 gain of
P82B715 allows the loading at Lx/Ly to be 10 times the load at Sx/Sy, so 2660pF
maximum. The loading at Lx/Ly due to the other standard buses is 133 pF each. For
just one remote module the cable capacitance may then be up to
(2660− 133)= 2530 pF. For typical twisted pairor flat cables,as usedfor telephonyor
Ethernet (Cat5e) wiring, that capacitance is around 50pFto70pF/ meter so the
cable could, in theory, be up to 50 m long. From practical experience, 30 m has
proven a safe cable length to be driven in this simple way, up to 100 kHz, with the
values shown. Longer distances and higher speeds are possible but require more
careful design.
If there are severe EMI/ESD teststobe passed then large clamp diodes canbe fitted the cable busat each moduleto VCC andto ground. They maybe diodes ratedfor
this ESD application, or simply large rectifiers (1N4000). The low-impedance bus
easily accommodates their relatively large capacitance. The P82B715 does not
provide any isolation between Lx and Sx, so this clamping method provides the best
protection for the lower voltage I2 C-bus parts. The VCC supply should be bypassed
using low-impedance capacitors. Zeners maybe fittedto prevent the supply rising due
to rectification during very large interference.
8.3 Comparison of P82B715 versus P82B96 in the quick design-in
point-to-point/multi-point circuitThe lower VOL level and ability to operate with any master, slave or bus buffer is the
primary advantageof the using the P82B715for long distance busesat the disadvantage
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate
bus capacitance does not allow these devices to operate with other bus buffers with
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise
margin. Waveforms using the circuit shown in Figure 9 are shown in Figure 10 using the
P82B715 and Figure 11 using the P82B96 so that the designer can clearly see these
trade-offs and choose the type of device that is best for their application.
NXP Semiconductors P82B7152 C-bus extenderFigure 10 shows the I2 C-bus waveforms from the long distance line as seen by the slave
on the P82B715 Sx/Sy I/O. Notice that the offset is small and the static levels remain
under 0.4 V. Coupling of SDA to SCL is negligible when SCL is LOW but slight
cross-coupling of SCL to SDA is visible when SDA is HIGH and therefore higher
impedance. The waveforms are very clean and will easily support all available I2 C-bus
masters and slaves.
Figure11 shows the waveformson the Sx/Sy I/Oas seenby the slave whena P82B96is
substituted. P82B96 uses a static level offset on the slave side to isolate noise and
loadingson either sideof this device. The nominal offsetis 0.8V and that VOL may create
worst-case design tolerance problems with slave devices that do not use I2 C-bus
switching levels,for example TTL levels.It also precludes operation with other bus buffers
using special non-compliant I2 C-bus levels.
The P82B96 does not actually interfere with the
operation of compliant I2 C-bus devices
down to at least 2.7 V supply or even with TTL devices (that switch around 1.4 V). It only
causes a theoretical worst case design tolerance problem because TTL devices have a
worst case 0.8 V requirement. A TTL designer must center the actual switch point
between the
two specified limits, 0.8V and 2.1V,soin realityit cannot ever approach the
problem 0.8 V theoretical limit.
The PCA9600 is an improved version of the P82B96 offering 1 MHz operation and lower,
more closely controlled VOL on the Sx and Sy pins.
