P80C652EFA ,CMOS single-chip 8-bit microcontrollerPIN CONFIGURATIONSThe P80C652/83C652 Single-Chip 8-BitMicrocontroller is manufactured in anP1.0adva ..
P80C652EHA ,CMOS single-chip 8-bit microcontrollerPIN CONFIGURATIONSThe P80C652/83C652 Single-Chip 8-BitMicrocontroller is manufactured in anP1.0adva ..
P80C652FFA ,CMOS single-chip 8-bit microcontrollers
P80C652FFA ,CMOS single-chip 8-bit microcontrollers
P80C652FFP ,CMOS single-chip 8-bit microcontroller
P80C652FFP ,CMOS single-chip 8-bit microcontroller
PC87351-IBW/VLA ,PC98 and ACPI Compliant SuperI/O with System Wake-up ControlBlock DiagramParallel Port/Floppy DriveInterfaceSerial Infrared Floppy DriveSerial ISAPPMInterface ..
PC87351-IBW/VLA ,PC98 and ACPI Compliant SuperI/O with System Wake-up ControlGeneral Description Outstanding
PC87360-ICK/VLA ,PC87360 128-Pin LPC SuperI/O with Protection and Extensive GPIO SupportPC87360 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support ..
PC87363IBW/VLA ,128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and ProtectionFeatures• PC99 and ACPI Compliant— PnP Configuration Register structure• Musical Instrument Digital ..
PC87363-IBW/VLA ,128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and ProtectionFeatures●The PC87363, a member of National Semiconductor’s 128-MIDI Port compatible with MPU-401 UA ..
PC87363-IBW/VLA ,128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protectionfeatures, including chassis intrusion detection,chip solution to the most commonly used PC I/O peri ..
P80C652EBA-P80C652EBB-P80C652EFA-P80C652EHA
CMOS single-chip 8-bit microcontroller
Product specification
Supersedes data of 1996 Aug 15
IC20 Data Handbook
1997 Dec 05
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
DESCRIPTIONThe P80C652/83C652 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
80C652/83C652 has the same instruction set
as the 80C51. Three versions of the
derivative exist:
83C652 — 8k bytes mask programmable
ROM
80C652 — ROMless version
87C652 — EPROM version (described in a
separate chapter)
This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 8XC652 contains a non-volatile
8k × 8 read-only program memory, a volatile
256 × 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
interrupt structure, an I2C interface, UART
and on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC652 can be expanded using standard
TTL compatible memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)μs
and 40% in 1.5(1)μs. Multiply and divide
instructions require 3(2)μs.
LOGIC SYMBOL
FEATURES 80C51 central processing unit 8k × 8 ROM expandable externally to
64k bytes 256 × 8 RAM, expandable externally to
64k bytes Two standard 16-bit timer/counters Four 8-bit I/O ports I2C-bus serial I/O port with byte oriented
master and slave functions Full-duplex UART facilities Power control modes
Idle mode
Power-down mode ROM code protection Extended frequency range: 3.5 to 24 MHz Three operating ambient temperature
ranges:
0 to +70°C
–40 to +85°C
–40 to +125°C
PIN CONFIGURATIONS
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
NOTES TO QFP ONLY: Due to EMC improvements, all VSS pins
(6, 16, 28, 39) must be connected to VSS
on the 80C652/83C652.
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
ORDER INFORMATION
NOTES: 80C652 and 83C652 frequency range is 3.5MHz–16MHz or 3.5MHz–24MHz. For specification of the EPROM version, see the 87C652 data sheet. xxx denotes the ROM code number.
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
BLOCK DIAGRAM
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
PIN DESCRIPTIONS
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
Table 1. 8XC652/654 Special Function Registers SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs.
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
ROM CODE PROTECTION
(83C652)The 8XC652 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code is
protected and cannot be read out at any time
by any test mode or by any instruction in the
external program memory space.
The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.
OSCILLATOR
CHARACTERISTICSXTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 2.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
ResetA reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on VDD and RST must
come up at the same time for a proper
start-up.
Idle ModeIn the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
Power-Down ModeIn the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.
2 C Serial Communication—SIO1The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.
Note that in both the 8XC652/4 and the
8XC552 the I2C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.
Table 2. External Pin Status During Idle and Power-Down Mode
Serial Control Register (S1CON) – See Table 3S1CON (D8H)
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3. Serial Clock Rates
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
ABSOLUTE MAXIMUM RATINGS1, 2, 3
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied. This product includes circuitry specifically designed for the protection of its internal devices
from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima. Parameters are valid over operating temperature range unless otherwise specified. All
voltages are with respect to VSS unless otherwise noted.
DEVICE SPECIFICATIONS
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
DC ELECTRICAL CHARACTERISTICSVSS = 0V; VDD = 5V ± 10%
NOTES ON NEXT PAGE.
Phlips Semiconductors Product specification
80C652/83C652CMOS single-chip 8-bit microcontrollers
NOTES FOR DC ELECTRICAL CHARACTERISTICS: See Figures 9 through 11 for IDD test conditions. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V;
VIH = VDD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD;
EA = RST = VSS. See Figure 11. 2V ≤ VPD ≤ VDDmax. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2 C specification, so an input voltage below 0.3VDD will be recognized as a
logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum
IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the
test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
10. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
11. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA.
