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P80C562EBA-P80C562EFA
8-bit microcontroller
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION
6.1 Pinning
6.2 Pin description FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION
8.1 Program Memory
8.2 Addressing I/O FACILITIES PULSE WIDTH MODULATED OUTPUTS
10.1 Prescaler Frequency Control Register (PWMP)
10.2 Pulse Width Register 0 (PWM0)
10.3 Pulse Width Register 1 (PWM1) ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1 Analog input pins
11.2 ADC Control Register (ADCON) TIMER/ COUNTERS
12.1 Timer 0 and Timer 1
12.2 Timer T2 Capture and Compare Logic
12.2.1 T2 Control Register (TM2CON)
12.2.2 Capture Control Register (CTCON)
12.2.3 Interrupt Flag Register (TM2IR)
12.2.4 Set Enable Register (STE)
12.2.5 Reset/Toggle Enable register (RTE)
12.3 Watchdog Timer (T3) SERIAL I/O INTERRUPT SYSTEM
14.1 Interrupt Vectors
14.2 Interrupt priority
14.3 Interrupt Enable and Priority Registers
14.3.1 Interrupt Enable Register 0 (IEN0)
14.3.2 Interrupt Enable register 1 (IEN1)
14.3.3 Interrupt priority register 0 (IP0)
14.3.4 Interrupt Priority Register 1 (IP1) REDUCED POWER MODES
15.1 Idle and Power-down operation
15.1.1 Idle mode
15.1.2 Power-down mode
15.2 Power Control Register (PCON) OSCILLATOR CIRCUITRY RESET CIRCUITRY
17.1 Power-on-reset INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING
23.1 Introduction
23.2 Reflow soldering
23.3 Wave soldering
23.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
FEATURES 80C51 Central Processing Unit8 kbytes ROM, expandable externally to 64 kbytes 256 bytes RAM, expandable externally to 64 kbytes Two standard 16-bit timer/counters An additional 16-bit timer/counter coupled to four
capture registers and three compare registers An 8-bit ADC with 8 multiplexed analog inputs Two 8-bit resolution, Pulse Width Modulated outputs Five 8-bit I/O ports plus one 8-bit input port shared with
analog inputs Full-duplex UART compatible with the standard 80C51 On-chip Watchdog Timer Oscillator frequency: 3.5to16 MHz.
GENERAL DESCRIPTIONThe P80C562/P83C562 (hereafter generally referred to as
P8xC562) single-chip 8-bit microcontroller is
manufactured in an advanced CMOS process and is a
derivative of the 80C51 microcontroller family.
The P8xC562 has the same instruction set as the 80C51.
Two versions of the derivative exist: With 8 kbytes mask-programmable ROM ROMless version of the P8xC562.
This I/O intensive device provides architectural
enhancements to function as a controller in the field of
automotive electronics, specifically engine management
and gear box control.
The P8xC562 contains a non-volatile 8 kbyte read only
program memory, a volatile 256 byte read/write data
memory, six 8-bit I/O ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare latches, a
fourteen-source, two-priority-level, nested interrupt
structure, an 8-input ADC, a dual DAC with pulse width
modulated outputs, a serial interface (UART), a
Watchdog Timer and on-chip oscillator and timing circuits.
For systems that require extra capability, the P8xC562 can
be expanded using standard TTL compatible memories
and logic.
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities. The instruction set consists of
over 100 instructions: 49 one-byte,45 two-byte and three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 0.75 μs and 40% in 1.5 μs.
Multiply and divide instructions require 3 μs.
ORDERING INFORMATION
Notes ROMless type. ROM coded type; nnn denotes the ROM code number.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
BLOCK DIAGRAM
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
FUNCTIONAL DIAGRAM
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 PINNING INFORMATION
6.1 Pinning
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
6.2 Pin description
Table 1 PLCC68 (SOT188-2)
To avoid latch-up at Power-on, the voltage at any pin at any time must lie within the range VDD +0.5VtoVSS− 0.5V.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 FUNCTIONAL DESCRIPTION
The P8xC562 is a stand-alone high-performance
microcontroller designed for use in real-time applications
such as instrumentation, industrial control and specific
automotive control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xC562 is a control-oriented CPU with on-chip
program and data memory. It can be extended with
external program memory up to 64 kbytes. It can also
access up to 64 kbytes of external data memory.
For systems requiring extra capability, the P8xC562 can
be expanded using standard memories and peripherals.
The P8xC562 has two software selectable modes of
reduced activity for further power reduction − Idle and
Power-down. The Idle mode freezes the CPU while
allowing the RAM, timers, serial ports and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to be inoperative. MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbyte external
data memory, 256 byte internal data memory and the kbyte internal and external program memory.
The internal data memory is divided into 3 sections: the
lower 128 bytes of RAM, the upper 128 bytes of RAM and
the 128 byte Special Function Register memory
(see Fig.4). Figure 5 shows the Special Function
Registers memory map. Internal RAM locations 0to 127
are directly and indirectly addressable. Internal RAM
locations 128to 155 are only indirectly addressable.
The Special Function Register locations 128to 255 are
only directly addressable.
The internal data RAM contains four register banks (each
with eight registers), 128 addressable bits, a scratch pad
area and the stack. The stack depth is limited by the
available internal data RAM and its location is determined
by the 8-bit Stack Pointer. All registers except the Program
Counter and the four 8-register banks reside in the
Special Function Register address space. These memory
mapped registers include arithmetic registers, pointers,
I/O ports, interrupt system registers, ADC and PWM
registers, timers and serial port registers. There are
120 addressable bit locations in the SFR address space.
The P8xC562 contains 256 bytes of internal data RAM
and 52 Special Function Registers. It provides a
non-paged program memory address space to
accommodate relocatable code. Conditional branches are
performed relative to the Program Counter.
The register-indirect jump permits branching relative to a
16-bit base register with an offset provided by an 8-bit
index register. 16-bit jumps and calls permit branching to
any location in the contiguous 64 kbyte program memory
address space.
8.1 Program Memory
The program memory address space of the P83C562
consists of internal and external memory. The P83C562
has 8 kbytes of program memory on-chip. The program
memory can be externally expanded up to 64 kbytes. If the
EA pin is held HIGH, the P83C562 executes out of the
internal program memory unless the address exceeds
1FFFH then locations 2000H through to 0FFFFH are
fetched from the external program memory. If the EA pin is
held LOW, the P83C562 fetches all instructions from the
external memory. Figure 4 illustrates the program
memory address space.
By setting a mask programmable security bit (i.e. user
dependent) the ROM content is protected i.e. it cannot be
read at any time by any test mode or by any instruction in
the external program memory space. The MOVC
instructions are the only ones which have access to
program code in the internal or external program memory.
The EA input is latched during reset and is ‘don’t care’ after
reset. This implementation prevents from reading internal
program code by switching from the external program
memory to internal program memory during MOVC
instruction or an instruction that handles immediate data.
Table 2 lists the access to internal and external program
memory by the MOVC instructions when the security bit
has been set to a logic 1. If the security bit has been set to
a logic 0 there are no restrictions for the MOVC
instructions.
Table 2 Memory access by the MOVC instruction
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
8.2 Addressing
The P8xC562 has five methods for addressing source
operands: Register Direct Register-Indirect Immediate Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
'destination/source' field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
Access to memory addressing is as follows: Registers in one of the four 8-register banks through
Register, Direct or Register-Indirect 256 bytes of internal data RAM through Direct or
Register-Indirect. Bytes 0to 127 may be addressed
directly/indirectly. Bytes 128to 155 share their address
locations with the SFR registers and so may only be
addressed indirectly as data RAM Special Function Registers through Direct at address
locations 128to 255 External data memory through Register-Indirect Program memory look-up tables through Base-Register
plus Index-Register-Indirect.
The P8xC562 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers,
Arithmetic Logic Unit and external data bus are all 8-bits
wide. It performs operations on bit, nibble, byte and
double-byte data types.
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 I/O FACILITIES
The P8xC562 has six 8-bit ports. Ports0to 3 are the same
as in the 80C51, with the exception of the additional
functions of Port 1. The parallel I/O function of Port 4 is
equal to that of Ports1, 2 and3. Port 5 has a parallel input
port function, but has no function as an output port.
Ports0to 5 perform the following alternative functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P8xC562 with
standard memories and peripherals.
Port 1 is used for a number of special functions:4 capture inputs (or external interrupt request inputs if
capture information is not utilized) External counter input External counter reset input.
Port 2 Provides the high-order address bus when
expanding the P8xC562 with external program
memory and/or external data memory.
Port 3 Pins can be configured individually to provide: External interrupt request inputs Counter inputs Serial port receiver input and transmitter output Control signals to READ and WRITE external data
memory.
Port 4 Can be configured to provide signals indicating a
match between timer counter T2 and its compare
registers.
Port 5 May be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs.
As Port 5 lines may be used as inputs to the ADC,
these digital inputs have an inherent hysteresis to
prevent the input logic from drawing too much
current from the power lines when driven by analog
signals. Channel-to-channel crosstalk should be
taken into consideration when both digital and
analog signals are simultaneously input to Port5
(see Chapter 20).
All ports are bidirectional with the exception of Port 5 which
is an input port. Alternative function bits which are not used
may be used as normal bidirectional I/O pins.
The generation or use of a Port 1, Port 3 or Port 4 pin as
an alternative function is carried out automatically by the
P8xC562 provided the associated Special Function
Register bit is set HIGH.
In addition to the standard 8-bit ports, the I/O facilities of
the P8xC562 also include a number of special I/O lines.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 PULSE WIDTH MODULATED OUTPUTS
Two pulse width modulated output channels are provided
with the P8xC562. These channels output pulses of
programmable length and interval. The repetition
frequency is defined by an 8-bit prescaler PWMP which
generates the clock for the counter. Both the prescaler and
counter are common to both PWM channels. The 8-bit
counter counts modulo 255 i.e. from 0to 254 inclusive.
The value of the 8-bit counter is compared to the contents
of two registers: PWM0 and PWM1.
Provided the contents of either of these registers is greater
than the counter value, the output of PWM0 or PWM1 is
set LOW. If the contents of these registers are equal to, or
less than the counter value, the output will be HIGH.
The pulse width ratio is therefore defined by the contents
of the registers PWM0 and PWM1.
The pulse width ratio is in the range of 0to 255/255 and
may be programmed in increments of 1/255.
The repetition frequency fPWM, at the PWMn outputs is
given by:
When using an oscillator frequency of 16 MHz for
example, the above formula would give a repetition
frequency range of 123 Hz to 31.4 kHz.
By loading the PWM registers with either 00Hor FFH, the
PWM outputs can be retained at a constant HIGH or LOW
level respectively. When loading FFH to the PWM
registers, the 8-bit counter will never actually reach this
value. Both PWMn output pins are driven by push-pull
drivers, and are not shared with any other function. PWM OSC 1 PWMP+ ()× 255× -------------------------------------------------------------=
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
10.1 Prescaler Frequency Control Register (PWMP)
Table 3 Prescaler Frequency Control Register (SFR address FEH)
Table 4 Description of PWMP bits
10.2 Pulse Width Register 0 (PWM0)
Table 5 Pulse Width Register 0 (SFR address FCH)
Table 6 Description of PWM0 bits
10.3 Pulse Width Register 1 (PWM1)
Table 7 Pulse Width Register 1 (SFR address FDH)
Table 8 Description of PWM1 bits
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 ANALOG-TO-DIGITAL CONVERTER (ADC)
The completion of the 8-bit ADC conversion is flagged by
ADCI in the ADCON register and the result is stored in
Special Function Register ADCH.
An ADC conversion in progress is unaffected by an
external or software ADC start. The result of a completed
conversion remains unaffected provided ADCI= 1. While
ADCS= 1 or ADCI= 1, a new ADC start will be blocked
and consequently lost.
An ADC conversion already in progress is aborted when
the Idle or Power-down mode is entered. The result of a
completed conversion (ADCI= 1) remains unaffected
when entering the Idle mode.
If ADCI is cleared by software and ADCS is set at the same
time, a new analog-to-digital conversion with the same
channel number, may be started. However, it is
recommended to reset ADCI before ADCS is set.
11.1 Analog input pins
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 8-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes machine cycles i.e. 18 μs at an oscillator frequency of MHz.
The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer, using bits AADR.0 to AADR.2 in ADCON.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
11.2 ADC Control Register (ADCON)
Table 9 ADC Control Register (SFR address C5H)
Table 10 Description of ADCON bits
Table 11 Function of ADCI and ADCS bits
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 TIMER/ COUNTERS
The P8xC562 contains: Three 16-bit timer/event counters: Timer0, Timer 1 and
Timer2 One 8-bit Watchdog Timer.
12.1 Timer 0 and Timer 1
Timer 0 and Timer 1 may be programmed to carry out the
following operations: Measure time intervals and pulse durations Count events Generate interrupt requests.
Timer 0 and Timer 1 can also be programmed
independently to operate in three modes:
Mode 0 8-bit timer or 8-bit counter each with
divide-by-32 prescaler
Mode 1 16-bit time-interval or event counter
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Timer 0 can be programmed to operate in an additional
mode as follows:
Mode 3 one 8-bit time-interval or event counter and one
8-bit time-interval counter.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes0, 1 or 2 but cannot set an interrupt
request flag or generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the serial port
transmission-rate generator.
The frequency handling range of these counters with a MHz crystal is as follows: In the timer function, the timer is incremented at a
frequency of 1.33 MHz; a division by 12 of the oscillator
frequency0 Hz to an upper limit of 0.66 MHz when programmed
for external inputs.
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations.
The counters are started and stopped under software
control. Each one sets its interrupt request flag when it
overflows from all logic 1s to all logic 0s (or automatic
reload value), with the exception of Mode 3 as previously
described.
12.2 Timer T2 Capture and Compare Logic
Timer T2 is a 16-bit timer/counter which has, coupled to it,
capture and compare facilities. The operational diagram is
shown in Fig.10.
The 16-bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4or 8. The input of
the prescaler is clocked with1 ⁄12 of the oscillator
frequency, or with positive edges on the T2 input, or it is
switched to the off position. The prescaler is cleared if its
division factor or its input source is changed, or if the
timer/counter is reset. T2 is readable on-the-fly, but
possesses no extra read latches; this means that software
precautions have to be taken against misinterpretation on
overflow from least to most significant byte during a read.
T2 is not loadable and is reset by the RST signal or at the
positive edge of the input signal RT2, if enabled. In the Idle
mode the timer/counter and prescaler are reset and
halted.
T2 is connected to four 16-bit Capture Registers: CT0,
CT1, CT2 and CT3. These registers are loaded with the
contents of T2 and an interrupt is requested upon receipt
of the input signals CT0I, CT1I, CT2I or CT3I. These input
signals are shared with Port 1. Using the Capture Register
(CTCON), these inputs may invoke capture and interrupt
request on a positive or negative edge or on both edges.
If neither a positive nor a negative edge is selected for a
capture input, no capture or interrupt request can be
generated by this input.
The contents of the Compare Registers CM0, CM1 and
CM2 are continually compared with the counter value of
Timer 2. When a match is found an interrupt may be
invoked. Using the match signal of CM0, the controller sets
bits 0to 5 of Port 4, if the corresponding bits of the Set
Enable Register are logic 1s.
Considering a match with CM1, if the corresponding bits of
the Reset/toggle Enable Register (RTE) are logic 1, then
the controller will use the match signal to reset bits 0to5
of Port 4. Bits 6 and 7 of Port 4 may be toggled by the
signal that indicates a match of Timer T2 and CM2 if the
corresponding bits of RTE are logic 1. CM0, CM1 and CM2
are reset by the RST signal.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At byte overflow
of the least significant byte, or at a 16-bit overflow of the
timer/counter, an interrupt sharing the same interrupt
vector is requested. Either one or both of these overflows
can be programmed to request an interrupt.
All interrupt flags must be reset by software.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
12.2.1 T2 CONTROL REGISTER (TM2CON)
Table 12 T2 Control Register (SFR address EAH)
Table 13 Description of TM2CON bits
Table 14 Timer 2 prescaler select
Table 15 Timer 2 mode select
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
12.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 16 Capture Control Register (SFR address EBH)
Table 17 Description of CTCON bits
12.2.3 INTERRUPT FLAG REGISTER (TM2IR)
Table 18 Interrupt Flag Register (SFR address C8H)
Table 19 Description of TM2IR bits (see notes1 and2)
Notes Interrupt Enable Register 1 (IEN1) is used to enable/disable Timer 2 interrupts. Interrupt Priority Register 1 (IP1) is used to determine the Timer 2 interrupt priority.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
12.2.4 SET ENABLE REGISTER (STE)
Table 20 Set Enable Register (SFR address EEH)
Table 21 Description of STE bits (see notes1 and2)
Notes If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n=0to5). STE.6 and STE.7 are read only.
12.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 22 Reset/toggle enable register (SFR address EFH)
Table 23 Description of RTE bits (note1)
Note If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2. For more information, refer to
the 8051-based “8-bit Microcontrollers Data Handbook IC20”.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
12.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer is also available, consisting of an 11-bit
prescaler and a 8-bit timer. The functional diagram of the
Watchdog Timer is shown in Fig.11. The timer is
incremented every t seconds,
where:
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/ software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control. 12 2048× OSC
--------------------------=
The Watchdog Timer can only be reloaded if the condition
flag WLE in the Power Control Register has been
previously set by software. At the moment the counter is
loaded the condition flag is automatically cleared.
The timer interval between the timer's reloading and
occurrence of a reset, is dependent upon the reloaded
value. For example, this may range from 2 ms to 0.5s
when using an oscillator frequency of 12 MHz. In the Idle
state the Watchdog Timer and reset circuitry remain
active.
The Watchdog Timer is controlled by the Enable
Watchdog pin (EW). A logic 0 enables the Watchdog
Timer and disables the Power-down mode. A logic1
disables the Watchdog Timer and enables the
Power-down mode.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562 SERIAL I/O
The P8xC562 is equipped with a full duplex UART port and
is identical to the serial port of the 80C51 (see‘Single-chip
8-bit Microcontrollers User Manual’ . INTERRUPT SYSTEM
External events and the real-time driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt system
is shown in Fig.12. Interrupt response latency is from
2.25 μs to 6 μs when using a 16 MHz crystal.
The P8xC562 acknowledges interrupt requests from sources as follows: INT0 and INT1: externally via pins P3.2/INT0 and
P3.3/INT1 respectively Timer 0 and Timer 1: from the two internal counters Timer T2 (8 separate interrupts): 4 capture interrupts, compare interrupts and an overflow interrupt. If the
Capture Register remains unused and its contents are
'don't care', then the corresponding input pin CTnI may
be used as a positive and/or negative edge triggered
external interrupt. ADC conversion completed interrupt UART serial I/O port interrupt.
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by a corresponding bit in
the IEN0 or IEN1 registers, in addition each interrupt may
be programmed to a high or low priority level using the
corresponding bit in the IP0 or IP1 registers. All enabled
sources can be globally disabled or enabled. Both external
interrupts can be programmed to be level-activated or
transition-activated; an active LOW level allows
'wire-ORing' of several interrupt sources to the input pin.
14.1 Interrupt Vectors
Table 24 gives the vector address in Program Memory
where the appropriate interrupt service routine is located.
Table 24 Interrupt vectors
14.2 Interrupt priority
Each interrupt source can be either high priority or low
priority. If both priorities are requested simultaneously, the
processor will branch to the high priority vector. If there are
simultaneous requests from sources of the same priority,
then interrupts will be serviced in the following order:
X0, ADC, T0, CT0, CM0, X1, CT1, CM1, T1, CT2, CM2,
S0, CT3, T2.
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine can
not be interrupted.
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
Philips Semiconductors Product specification
8-bit microcontroller P83C562; P80C562
14.3 Interrupt Enable and Priority Registers
14.3.1 INTERRUPT ENABLE REGISTER0 (IEN0)
Table 25 Interrupt Enable Register 0 (SFR address A8H)
Table 26 Description of IEN0 bits (note1)
Note Logic0= interrupt disabled; Logic1= interrupt enabled.
14.3.2 INTERRUPT ENABLE REGISTER1 (IEN1)
Table 27 Interrupt Enable Register1 (SFR address E8H)
Table 28 Description of IEN1 bits (note1)
Note Logic0= interrupt disabled; Logic1= interrupt enabled.
