P83C557E4EFB ,Single-chip 8-bit microcontrollerFEATURES• 80C51 central processing unit• 32 K × 8 ROM respectively FEEPROM (Flash-EEPROM),expandabl ..
P83C575EBBB ,80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
P83C592 ,8-bit microcontroller with on-chip CAN
P83C592 ,8-bit microcontroller with on-chip CAN
P83C592FFA ,8-bit microcontroller with on-chip CAN
P83C592FHA ,8-bit microcontroller with on-chip CAN
PCA8550 ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550 ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550 ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550 ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550 ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550D ,4-bit multiplexed/1-bit latched 5-bit I2C EEPROM DIP switchPin configurationORDERING INFORMATIONPACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUM ..
P80C557E4EFB-P83C557E4EFB
Single-chip 8-bit microcontroller
Product specification 1999 Mar 02
Supersedes data of 1999 Feb 15
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller FEATURES 80C51 central processing unit 32 K × 8 ROM respectively FEEPROM (Flash-EEPROM),
expandable externally to 64 Kbytes ROM/FEEPROM Code protection 1024 × 8 RAM, expandable externally to 64 Kbytes Two standard 16-bit timer/counters An additional 16-bit timer/counter coupled to four capture
registers and three compare registers A 10-bit ADC with eight multiplexed analog inputs and
programmable autoscan Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs I2C-bus serial I/O port with byte oriented master and slave
functions Full-duplex UART compatible with the standard 80C51 On-chip watchdog timer 15 interrupt sources with 2 priority levels (2 to 6 external sources
possible) Extended temperature range (–40 to +85°C) 4.5 to 5.5 V supply voltage range Frequency range for 80C51-family standard oscillator:
3.5 MHz to 16 MHz PLL oscillator with 32 kHz reference and software-selectable
system clock frequency Seconds Timer Software enable/disable of ALE output pulse Electromagnetic compatibility improvements Wake-up from Power-down by external or seconds interrupt
GENERAL DESCRIPTIONThe P80C557E4/P83C557E4/P89C557E4 (hereafter generically
referred to as P8xC557E4) single-chip 8-bit microcontroller is
manufactured in an advanced CMOS process and is a derivative of
the 80C51 microcontroller family. The P8xC557E4 has the same
instruction set as the 80C51. Three versions of the derivative exist: P83C557E4 — 32 Kbytes mask programmable ROM P80C557E4 — ROMless version of the P83C557E4 P89C557E4 — 32 Kbytes FEEPROM (Flash-EEPROM)
The P8xC557E4 contains a non-volatile 32 Kbytes mask
programmable ROM (P83C557E4) or electrically erasable
FEEPROM respectively (P89C557E4), a volatile 1024 × 8 read/write
data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2 C-bus), a “watchdog” timer, an on-chip
oscillator and timing circuits. For systems that require extra
capability the P8xC557E4 can be expanded using standard TTL
compatible memories and logic.
In addition, the P8xC557E4 has two software selectable modes of
power reduction — Idle Mode and power-down mode. The Idle
Mode freezes the CPU while allowing the RAM, timers, serial ports,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic as well as bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system
clock, 58% of the instructions are executed in 0.75 μs and 40% in
1.5 μs. Multiply and divide instructions require 3 μs.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
ORDERING INFORMATION
NOTE: YYY denotes the ROM code number
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
PINNING
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
4.1 PIN DESCRIPTION
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
PIN DESCRIPTION (Continued)
NOTE: To avoid a ‘latch-up’ effect at Power-on, the voltage at any pin at any time must not be higher or lower than VDD+ 0.5 V or VSS– 0.5 V
respectively.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller ELECTROMAGNETIC COMPATIBILITY (EMC)
IMPROVEMENTS
Primary attention was paid on the reduction of electromagnetic
emission of the microcontroller P8xC557E4.
The following features effect in reducing the electromagnetic
emission and additionally improve the electromagnetic susceptibility:• Four supply voltage pins (VDD) and four ground pins (VSS) with
pairs of VDD and VSS at two adjacent pins at each side of the
package. Separated VDD pins for the internal logic and the port buffers Internal decoupling capacitance improves the EMC radiation
behavior and the EMC immunity External capacitors are to be located as close as possible
between pins VDD1 and VSS1, VDD2 and VSS2, VDD3 and VSS3 as
well as VDD4 and VSS4 ; ceramic chip capacitors are
recommended (100nF).
Useful in applications that require no external memory or temporarily
no external memory: The ALE output signal (pulses at a frequency of fCLK/6) can be
disabled under software control (bit 5 in the SFR PCON: “RFI”); if
disabled, no ALE pulse will occur. ALE pin will be pulled down
internally, switching an external address latch to a quiet state.
The MOVX instruction will still toggle ALE (external data memory
is accessed). ALE will retain its normal HIGH value during Idle
Mode and a LOW value during Power-down mode while in the
“RFI” reduction mode. Additionally during internal access
(EA = 1) ALE will toggle normally when the address exceeds the
internal program memory size. During external access (EA = 0)
ALE will always toggle normally, whether the flag “RFI” is set or
not. FUNCTIONAL DESCRIPTION
6.1 General
The P8xC557E4 is a stand-alone high-performance microcontroller
designed for use in real time applications such as instrumentation,
industrial control, medium to high-end consumer applications and
specific automotive control applications.
In addition to the 80C51 standard functions, the device provides a
number of dedicated hardware functions for these applications.
The P8xC557E4 is a control-oriented CPU with on-chip program
and data memory. It can be extended with external program memory
up to 64 Kbytes. It can also access up to 64 Kbytes of external data
memory. For systems requiring extra capability, the P8xC557E4 can
be expanded using standard memories and peripherals.
The P8xC557E4 has two software selectable modes of reduced
activity for further power reduction – Idle and Power-down. The Idle
Mode freezes the CPU while allowing the RAM, timers, serial ports
and interrupt system to continue functioning. The Power-down Mode
saves the RAM contents but freezes the oscillator causing all other
chip functions to be inoperative. The Power-down Mode can be
terminated by an external Reset, by the seconds interrupt and by
any one of the two external interrupts. (See description Wake-up
from Power-down Mode.)
6.2 Memory organization
The central processing unit (CPU) manipulates operands in three
memory spaces; these are the 64 Kbytes external data memory,
1024 bytes internal data memory (consisting of 256 bytes standard
RAM and 768 bytes AUX-RAM) and the 32 Kbytes internal and/or
64 Kbytes external program memory (see Figure 4).
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.2.1 Program Memory
The program memory of the P8xC557E4 consists of 32 Kbytes
ROM respectively FEEPROM (”Flash Memory”) on-chip, externally
expandable up to 64 Kbytes. If, during RESET, the EA pin was held
HIGH, the P8xC557E4 executes out of the internal program memory
unless the address exceeds 7FFFH. Locations 8000H through
0FFFFH are then fetched from the external program memory. If the
EA pin was held LOW during RESET the P8xC557E4 fetches all
instructions from the external program memory. The EA input is
latched during RESET and is don’t care after RESET.
The internal program memory content is protected, by setting a
mask programmable security bit (ROM) or by the software
programmable security byte (FEEPROM) respectively, i.e. it cannot
be read out at any time by any test mode or by any instruction in the
external program memory space. The MOVC instructions are the
only ones which have access to program code in the internal or
external program memory. The EA input is latched during RESET
and is ’don’t care’ after RESET. This implementation prevents from
reading internal program code by switching from external program
memory to internal program memory during MOVC instruction or an
instruction that handles immediate data. Table 1 lists the access to
the internal and external program memory with MOVC instructions
when the security feature has been activated.
6.2.2 Internal Data Memory
The internal data memory is divided into three physically separated
parts:
256 bytes of RAM, 768 bytes of AUX-RAM, and a 128 bytes special
function area. These can be addressed each in a different way (see
also Table 2). RAM 0 to 127 can be addressed directly and indirectly as in the
80C51. Address pointers are R0 and R1 of the selected
registerbank. RAM 128 to 255 can only be addressed indirectly.
Address pointers are R0 and R1 of the selected registerbank. AUX-RAM 0 to 767 is also indirectly addressable as external
DATA MEMORY locations 0 to 767 via MOVX-Datapointer
instruction, unless it is disabled by setting ARD = 1.
AUX-RAM 0 to 767 is indirectly addressable via pageregister
(XRAMP) and MOVX-Ri instructions, unless it is disabled by
setting ARD = 1 (see Figure 5).
When executing from internal program memory, an access to
AUX-RAM 0 to 767 will not affect the ports P0, P2, P3.6 and P3.7.
An access to external DATA MEMORY locations higher than 767
will be performed with the MOVX @ DPTR instructions in the
same way as in the 80C51 structure, so with P0 and P2 as
data/address bus and P3.6 and P3.7 as write and read timing
signals. Note that the external DATA MEMORY cannot be
accessed with R0 and R1 as address pointer if the AUX-RAM is
enabled (ARD = 0, default). The Special Function Registers (SFR) can only be addressed
directly in the address range from 128 to 255 (see Table 5). Four register banks, each 8 registers wide, occupy locations 0
through 31 in the lower RAM area. Only one of these banks may
be enabled at a time. The next 16 bytes, locations 32 through 47,
contain 128 directly addressable bit locations.The stack can be
located anywhere in the internal 256 bytes RAM.The stack depth
is only limited by the available internal RAM space of 256 bytes
(see Figure 7).
All registers except the program counter and the four register
banks reside in the Special Function Register address space.
Table 1. Memory Access by the MOVC Instruction for Protected ROMs
NOTE: If the security feature has not been activated, there are no restrictions for MOVC instructions.
Table 2. Internal Data Memory Map
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.2.2.1 AUX-RAM Page Register XRAMP
The AUX-RAM Page Register is used to select one of three 256
bytes pages of the internal 768 bytes AUX-RAM for
MOVX-accesses via R0 or R1. Its reset value is (XXXXXX00).
Table 3. Description of XRAMP Bits
Table 4. Memory Locations for All Possible MOVX Accesses
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Table 5. Special Function Register Memory Map and Reset Values
NOTES: = Bit addressable register = Read only register = Undefined = FMCON only in P89C557E4
6.3 Addressing
The P8xC557E4 has five methods for addressing: Register Direct Register-Indirect Immediate Base-Register plus Index-Register-Indirect
The first three methods can be used for addressing destination
operands. Most instructions have a “destination/source” field that
specifies the data type, addressing methods and operands involved.
For operations other than MOVs, the destination operand is also a
Access to memory addresses is as follows: Register in one of the four register banks through Register, Direct
or Register-Indirect addressing 1024 bytes of internal RAM through Direct or Register-Indirect
addressing. Bytes 0–127 of internal RAM may be addressed
directly/indirectly. Bytes 128–255 of internal RAM share their
address location with the SFRs and so may only be addressed
indirectly as data RAM. Bytes 0–767 of AUX-RAM can only be addressed indirectly via
MOVX. Special Function Register through direct addressing at address
locations 128–255 (see Figure 8).
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.4 I/O Facilities
The P8xC557E4 has six 8-bit ports. Ports 0 to 3 are the same as in
the 80C51, with the exception of the additional functions of Port 1.
The parallel I/O function of Port 4 is equal to that of Ports 1, 2 and 3.
Port 5 has a parallel input port function, but has no function as an
output port.
The SDA and SCL lines serve the serial port SIO1 (I2C). Because
the I2C-bus may be active while the device is disconnected from
VDD, these pins, are provided with open drain drivers.
Ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions:
Port 0 : provides the multiplexed low-order address and data
bus used for expanding the P8xC557E4 with standard
memories and peripherals.
Port 1 : Port 1 is used for a number of special functions:
4 capture inputs (or external interrupt request inputs if
capture information is not utilized) external counter input external counter reset input
Port 2 : provides the high-order address bus when the
P8xC557E4 is expanded with external Program
Memory and/or external Data Memory.
Port 3 : pins can be configured individually to provide: external interrupt request inputs counter inputs receiver input and transmitter output of seri port
SIO 0 (UART) control signals to read and write external Data
Memory
Port 4 : can be configured to provide signals indicating a match
between timer counter T2 and its compare registers.
Port 5 : may be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs. As
Port 5 lines may be used as inputs to the ADC, these
digital inputs have an inherent hysteresis to prevent the
input logic from drawing too much current from the
power lines when driven by analog signals. Channel to
channel crosstalk should be taken into consideration
when both digital and analog signals are simultaneously
input to Port 5 (see DC characteristics).
All ports are bidirectional with the exception of Port 5 which is an
input port.
Pins of which the alternative function is not used may be used as
normal bidirectional I/Os.
The generation or use of a Port 1, Port 3 or Port 4 pin as an
alternative function is carried out automatically by the P8xC557E4
provided the associated Special Function Register bit is set HIGH.
The pull-up arrangements of Ports 1 – 4 are shown in Figure 9.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.5 Pulse Width Modulated Outputs
The P8xC557E4 contains two pulse width modulated output
channels (see Figure 13). These channels generate pulses of
programmable length and interval. The repetition frequency is
defined by an 8-bit prescaler PWMP, which supplies the clock for the
counter. The prescaler and counter are common to both PWM
channels. The 8-bit counter counts module 255, i.e., from 0 to 254
inclusive. The value of the 8-bit counter is compared to the contents
of two registers: PWM0 and PWM1. Provided the contents of either
of these registers is greater than the counter value, the
corresponding PWM0 or PWM1 output is set LOW. If the contents of
these registers are equal to, or less than the counter value, the
output will be HIGH. The pulse-width-ratio is therefore defined by the
contents of the registers PWM0 and PWM1. The pulse-width-ratio is
in the range of 0/255 to 255/255 and may be programmed in
increments of 1/255.
Buffered PWM outputs may be used to drive DC motors. The
rotation speed of the motor would be proportional to the contents of
PWMn. The PWM outputs may also be configured as a dual DAC. In
this application, the PWM outputs must be integrated using
conventional operational amplifier circuitry. If the resulting output
voltages have to be accurate, external buffers with their own analog
supply should be used to buffer the PWM outputs before they are
integrated. The repetition frequency fpwm, at the PWMn outputs is
give by:
fpwm fCLK(1 PWMP) 255
This gives a repetition frequency range of 123 Hz to 31.4 kHz (fCLK
= 16 MHz). By loading the PWM registers with either 00H or FFH,
the PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never
actually reach the value of the PWM registers when they are loaded
with FFH.
When a compare register (PWM0 or PWM1) is loaded with a new
value, the associated output is updated immediately. It does not
have to wait until the end of the current counter period. Both PWMn
output pins are driven by push-pull drivers. These pins are not used
for any other purpose.
Table 6. Description of PWMP Bits
NOTE: Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
Table 7. Description of PWM0 bits
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Table 8. Description of PWM1 bits
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.6 Analog/Digital Converter (ADC)
The P8xC557E4 A/D Converter is a 10-bit, successive
approximation ADC with 8 multiplexed analog input channels. It
additionally contains a high input impedance comparator, a DAC
built with 1024 series resistors and analog switches, registers and
control logic.
Input voltage range is from AVref– (typical 0V) to AVref+ (typical +5V).
A set of 8 buffer registers (10-bit) store the conversion results of the
proper analog input channel each.
11 Special Function Registers (SFR) perform the user software
interface to the ADC: a control SFR (ADCON), an analog port
scan-select SFR (ADPSS), 8 input channel related conversion result
SFR with the 8 lower result bits (ADRSL0...ADRSL7), one common
result SFR for the upper 2 result bits (ADRSH). An extra SFR (P5)
allows for reading digital input port data as an alternative function of
the 8 analog input pins.
In order to have a minimum of ADC service overhead in the
microcontroller program, the ADC is able to operate autonomously
within its user configurable autoscan function.
The functional diagram of the ADC is shown in Figure 15.
Feature Overview: 10-bit resolution. 8 multiplexed analog inputs. Programmable autoscan of the analog inputs. Bit oriented 8-bit scan-select register to select analog inputs. Continuous scan or one time scan configurable from 1 to 8 analog
inputs. Start of a conversion by software or with an external signal. Eight 10-bit buffer registers, one register for each analog input
channel. Interrupt request after one channel scan loop. Programmable prescaler (dividing by 2, 4, 6, 8) to adapt to
different system clock frequencies. Conversion time for one A/D conversion: 15 μs ... 50 μs Differential non-linearity : DLe ±1 LSB. Integral non-linearity : ILe ±2 LSB. Offset error : OSe ±2LSB. Gain error : Ge ±0.4 %. Absolute voltage error : Ae ±3 LSB. Channel to channel matching : Mctc ±1LSB. Crosstalk between analog inputs: Ct < –60dB. @100 kHz. Monotonic and no missing codes. Separated analog (AVDD, AVSS) and digital (VDD, VSS) supply
voltages. Reference voltage at two special pins : AVREF– and AVREF+.
For further information on the ADC characteristics, refer to the
“DC CHARACTERISTICS” section.
6.1.1 Functional description:
Table 9. A/D Special Function Registers
A/D Control Register ADCON
The Special Function Register ADCON contains control and status
bits for the A/D Converter peripheral block. The reset value of
ADCON is (00000000). Its hardware address is D7H. ADCON is not
bit addressable.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Table 10. Description of ADCON bits
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
A/D Input Port Scan-Select Register ADPSS
The Special Function Register ADPSS contains control bits to select
the analog input channel(s) to be scanned for A/D conversion. The
reset value of ADPSS is (00000000). Its hardware address is E7H.
ADPSS is not bit addressable.
If all bits are ‘0’ then no A/D conversion can be started. If ADPSS is
written while an A/D conversion is in progress (ADSST in the
ADCON register is ‘1’) then the autoscan loop with the previous
selected analog inputs is completed first. The next autoscan loop is
performed with the new selected analog inputs.
A/D Result Registers ADRSLn and ADRSH:
The binary result code of A/D conversions is accessed by these
Special Function Registers. The result SFR are read only registers.
The read value after reset is indeterminate. Their data are not
affected by chip reset. They are not bit addressable.
There are 8 Special Function Registers ADRSLn
(ADRSL0...ADRSL7) – A/D Result Low byte – and one general SFR
ADRSH – A/D Result High byte – . Each of ADRSLn is associated
with the coincidently indexed analog input channel ADCn
(ADC0/P5.0...ADC7/P5.7). Reading an ADRSLn register by
software copies at the same time the two highest bits of the 10-bit
conversion result into two latches, thus preserving them until the
next read of any ADRSLn register. These two latches form bit
positions 0 and 1 of SFR ADRSH, the upper 6 bits of ADRSH are
always read as ’0’.
Thus it is ensured to get the 10-bit result of the same single A/D
conversion by reading any register ADRSLn first and after it the
register ADRSH.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
Digital Input Port Register P5
Port 5 Special Function Register P5 always represents the binary
value of the logic level at input pins P5.0/ADC0...P5.7/ADC7. P5 is
not affected by chip reset. P5 is a read only register. Its hardware
address is C7H. P5 is not bit addressable.
Reading Special Function Register P5 does not affect A/D
conversions. But it is recommended to use the digital input port
function of the hardware Port 5 only as an alternative to analog input
voltage conversions. Simultaneous mixed operation is discouraged
for the sake of A/D conversion result reliability and accuracy.
For further information on Port 5, refer to the “I/O facilities” section.
For further information on A/D Special Function Registers, refer to
the “Internal Data Memory” section.
Reset
After a RESET of the microcontroller the ADCON and ADPSS
register bits are initialized to zero. Registers ADRSLn and ADRSH
are not initialized by a RESET.
Idle and Power-down Mode
The A/D Converter is active only when the microcontroller is in
normal operating mode. If the Idle or Power-down Mode is activated,
then the ADC is switched off and put into a power saving idle state –
a conversion in progress is aborted, a previously set ADSST flag is
cleared and the internal clock is halted. The conversion result
registers are not affected.
The interrupt flag ADINT will not be set by activation of Idle or
Power-down Mode. A previously set flag ADINT will not be cleared
by the hardware. (Note: ADINT cannot be cleared by hardware at
all, except for a RESET – it must be cleared by the user software.)
After a wakeup from Idle or Power-down Mode a set flag ADINT
indicates that at least one autoscan loop was finished completely
before the microcontroller was put into the respective power
reduction mode and it indicates that the stored result data may be
fetched now – if desired.
For further information on Idle and Power-down Mode, refer to the
“Power reduction modes” section.
Timing
A programmable prescaler is controlled by the bits ADPR1 and
ADPR0 in register ADCON to adapt the conversion time for different
microcontroller clock frequencies.
Table 11 shows conversion times (tconv) for one A/D conversion at
some convenient system clock frequencies (fclk) and ADC prescaler
divisors (m), which are user selectable by the bits ADCON.7/ADPR1
and ADCON.6/ADPR0.
For conversion times outside the limits for tconv the specified ADC
characteristics are not guaranteed; (prohibited conversion times are
put in brackets):
Table 11. Conversion time configuration
examples (tconv/μs)
Conversion time tconv = (6 m + 1) machine cycles
A conversion time tconv consists of one sample time period (which
equals two bit conversion times), 10 bit conversion time periods and
one machine cycle to store the result.
After result storage an extra initializing time period follows to select
the next analog input channel (according to the contents of SFR
ADPSS), before the input signal is sampled.
Thus the time period between two adjacent conversions within an
autoscan loop is larger than the pure time tconv. This autoscan cycle
time is ( 7 m ) machine cycles.
At the start of an autoscan conversion the time between writing to
SFR ADCON and the first analog input signal sampling depends on
the current prescaler value (m) and the relative time offset between
this write operation and the internal (divided) ADC clock. This gives
a variation range for the A/D conversion start time of ( m / 2 )
machine cycles.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
6.6.2 Configuration and Operation
Every A/D conversion is an autoscan conversion. The two user
selectable general operation modes are continuous scan and
one-time scan mode.
The desired analog input port channel/s for conversion is/are
selected by programming A/D input port scan-select bits in SFR
ADPSS. An analog input channel is included in the autoscan loop if
the corresponding bit in ADPSS is 1, a channel is skipped if the
corresponding bit in ADPSS is 0.
An autoscan is always started according to the lowest bit position of
ADPSS that contains a 1.
An autoscan conversion is started by setting the flag ADSST in
register ADCON either by software or by an external start signal at
input pin ADEXS, if enabled. Either no edge (external start totally
disabled), a rising edge or/and a falling edge of ADEXS is selectable
for external conversion start by the bits ADSRE and ADSFE in
register ADCON.
After completion of an A/D conversion the 10-bit result is stored in
the corresponding 10-bit buffer register. Then the next analog input
is selected according to the next higher set bit position in ADPSS,
converted and stored, and so on. When the result of the last
conversion of this autoscan loop is stored, flag ADCON.4/ADINT,
the ADC interrupt flag, is set. It is not cleared by interrupt hardware
– it must be cleared by software.
In continuous scan mode (ADCON.2/ADCSA=1) the ADC start and
status flag ADCON.3/ADSST retains the set state and the autoscan
loop restarts from the beginning. In one-time scan mode (ADCSA=0)
conversions stop after the last selected analog input was converted,
ADINT is set and ADSST is cleared automatically.
ADSST cannot be set (neither externally nor by software) as long as
ADINT=1, i.e. as long as ADINT is set, a new conversion start – by
setting flag ADSST – is inhibited; actually it is only delayed until
ADINT is cleared.
(If a ‘1’ is written to ADSST while ADINT=1, this new value is
internally latched and preserved, not setting ADSST until
ADCON.4/ADINT=0. In this state, a read of SFR ADCON will display
ADCON.3/ADSST=0, because always the effective ADC status is
read.)
Note that under software control the analog inputs can also be
converted in arbitrary order, when one-time scan mode is selected
and in SFR ADPSS only one bit is set at a time. In this case ADINT
is set and ADSST is cleared after every conversion.
6.6.3 Resolution and Characteristics
The ADC system has its own analog supply pins AVDD and AVSS. It
is referenced by two special reference voltage input pins sourcing
the resistance ladder of the DAC: AVref+ and AVref–. The voltage
between AVREF+ and AVREF– defines the full-scale range. Due to
the 10-bit resolution the full scale range is divided into 1024 unit
steps. The unit step voltage is 1 LSB, which is typically 5 mV
(AVref+ = 5.12 V, AVref– = 0 V = AVSS).
The DAC’s resistance ladder has 1023 equally spaced taps,
separated by a unit resistance ’R’. The first tap is located 0.5 x R
above AVref–, the last tap is located 1.5 x R below AVref+. This
results in a total ladder resistance of 1024 x R. This structure
ensures that the DAC is monotonic and results in a symmetrical
(AVref+ – 3/2 LSB) and AVref+ the 10-bit conversion result code will
be 11 1111 1111 B = 3FFH = 1023D.
The result code corresponding to an analog input voltage (AVin) can
be calculated from the formula:
ResultCode� 1024� AVIN�AVref�
AVref� �AVref�
The analog input voltage should be stable when it is sampled for
conversion. At any times the input voltage slew rate must be less
than 10 V/ms (5 V conversion range) in order to prevent an
undefined result.
This maximum input voltage slew rate can be ensured by an RC low
pass filter with R = 2k2 and C = 100 nF. The capacitor between
analog input pin and analog ground pin shall be placed close to the
pins in order to have maximum effect in minimizing input noise
coupling.
6.7 Timer/Counters
The P8xC557E4 contains three 16-bit timer/event counters: Timer 0,
Timer 1 and Timer T2 and one 8-bit timer, T3. Timer 0 and Timer 1
may be programmed to carry out the following functions: Measure time intervals and pulse durations Count events Generate interrupt requests
6.7.1 Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in SFR TMOD that selects
the timer or counter function of the corresponding timer.
In the timer function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 12 oscillator periods, the count rate is
1/12 of the oscillator frequency.
In the counter function, the register is incremented in response to a
1-to-0 transition at the corresponding external input pin, T0 or T1. In
this function, the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one cycle and a
LOW in the next cycle, the counter is incremented. Thus, it takes
two machine cycles (24 oscillator periods) to recognize a 1-to-0
transition. There are no restrictions on the duty cycle of the external
input signal, but to insure that a given level is sampled at least once
before it changes, it should be held for at least one full machine
cycle.
Timer 0 and Timer 1 can be programmed independently to operate
in one of four modes: Mode 0:
8-bit timer or 8-bit counter each with divide-by-32 prescaler Mode 1:
16-bit time-interval or event counter Mode 2:
8-bit time-interval or event counter with automatic reload
upon overflow Mode 3:
–Timer 0: one 8-bit time-interval or event counter and
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When Timer 0 is in Mode 3, Timer 1 can be programmed to operate
in Modes 0, 1 or 2 but cannot set an interrupt request flag or
generate an interrupt. However the overflow from Timer 1 can be
used to pulse the serial port baud-rate generator.
With a 16 MHz crystal, the counting frequency of these
timer/counters is as follows: In the timer function, the timer is incremented at a frequency of
1.33 MHz – a division by 12 of the system clock frequency 0 Hz to an upper limit of 0.66 MHz (1/24 of the system clock
frequency) when programmed for external inputs
Both internal and external inputs can be gated to the counter by a
second external source for directly measuring pulse durations.
When configured as a counter, the register is incremented on every
falling edge on the corresponding input pin, T0 or T1. The
incremented register value can be read earliest during the second
machine cycle after that one, during which the incrementing pulse
occurred.
The counters are started and stopped under software control. Each
one sets its interrupt request flag when it overflows from all HIGHs
to all LOWs (or automatic reload value), with the exception of mode
3 as previously described.
Table 12. Description of TMOD bits
Table 13. Timer 0 / Timer 1 operation select
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Table 14. Description of TCON bits
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6.7.2 Timer T2
Timer T2 is a 16 bit timer/counter which has capture and compare
facilities. The operational diagram is shown in Figure 21.
The 16 bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of the
prescaler is clocked with 1/12 of the clock frequency, or by an
external source connected to the T2 input, or it is switched off. The
maximum repetition rate of the external clock source is fCLK/12,
twice that of Timer 0 and Timer 1. The prescaler is incremented on a
rising edge. It is cleared if its division factor or its input source is
changed, or if the timer/counter is reset (see also Figure 22:
TM2CON). T2 is readable ’on the fly’, without any extra read
latches; this means that software precautions have to be taken
against misinterpretation at overflow from least to most significant
byte while T2 is being read. T2 is not loadable and is reset by the
RST signal or at the positive edge of the input signal RT2, if
enabled. In the Idle or Power-down Mode the timer/counter and
prescaler are reset and halted.
T2 is connected to four 16-bit Capture Registers: CT0, CT1, CT2
and CT3. A rising or falling edge on the inputs CT0I, CT1I, CT2I or
CT3I (alternative function of Port 1) results in loading the contents of
T2 into the respective Capture Registers and an interrupt request.
Using the Capture Register CTCON (see Figure 23), these inputs
may invoke capture and interrupt request on a positive, a negative
edge or on both edges. If neither a positive nor a negative edge is
selected for capture input, no capture or interrupt request can be
generated by this input.
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Table 15. Description of TM2CON bits
Table 16. Timer 2 prescaler select
Table 17. Timer 2 mode select
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Table 18. Description of CTCON bits
The contents of the Compare Registers CM0, CM1 and CM2 are
continuously compared with the counter value of Timer T2. When a
match occurs, an interrupt may be invoked. A match of CM0 sets
the bits 0–5 of Port 4, a CM1 match resets these bits and a CM2
match toggles bits 6 and 7 of Port 4, provided these functions are
enabled by the STE respectively RTE registers. A match of CM0
and CM1 at the same time results in resetting bits 0–5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
Table 19. Description of TM2IR bits
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Table 20. Description of STE bits
Table 21. Description of RTE bits
For more information concerning the TM2CON, CTCON, TM2IR and
the STE/RTE registers see IC20 handbook, chapter “80C51 family
hardware description”.
Port 4 can be read and written by software without affecting the
toggle, set and reset signals. At a byte overflow of the least
significant byte, or at a 16-bit overflow of the timer/counter, an
interrupt sharing the same interrupt vector is requested. Either one
or both of these overflows can be programmed to request an
interrupt.
All interrupt flags must be reset by software.
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6.8 Watchdog Timer T3
In addition to Timer T2 and the standard timers, a watchdog timer
(T3) consisting of an 11-bit prescaler and an 8-bit timer is also
incorporated (see Figure 27).
The timer is incremented every 1.5 ms, derived from the system
clock frequency of 16 MHz by the following:timer� fCLK
12� 2048
When a timer overflow occurs, the microcontroller is reset and a
reset output pulse is generated at pin RSTOUT. Also the PLL control
register is reset.
To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software
malfunction, the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the processor
running out of control.
The watchdog timer can only be reloaded if the condition flag
WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the occurrence
of a reset depends on the reloaded value. For example, this may
range from 1.5 ms to 0.375 s when using an oscillator frequency of
16 MHz.
In the Idle state the watchdog timer and reset circuitry remain active.
The watchdog timer is controlled by the watchdog enable pin (EW).
A LOW level enables the watchdog timer and disables the
Power-down Mode. A HIGH level disables the watchdog timer and
enables the Power-down Mode.
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6.9 Serial I/O
The P8xC557E4 is equipped with two independent serial ports:
SIO0 and SI01. SIO0 is the full duplex UART port, identical to the
PCB80C51 serial port. SIO1 is an I2 C-bus serial I/O interface with
byte oriented master and slave functions.
6.9.1 SIO0 (UART)
SIO 0 is a full duplex serial I/O port – it can transmit and receive
simultaneously. This serial port is also receive-buffered. It can
commence reception of a second byte before the previously
received byte has been read from the receive register. If, however,
the first byte has still not been read by the time reception of the
second byte is complete, one of the bytes will be lost. The SIO0
receive and transmit registers are both accessed via the S0BUF
special function register. Writing to S0BUF loads the transmit
register, and reading S0BUF accesses to a physically separate
receive register. SIO0 can operate in 4 modes:
Mode 0: Serial data is transmitted and received through RXD.
TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at 1/12 of the oscillator frequency. A write into
S0CON should be avoided during a transmission to
avoid spikes on RXD/TXD.
Mode 1: 10 bits are transmitted via TXD or received through
RXD: a start bit (0), 8 data bits (LSB first), and a
stop bit(1). On receive, the stop bit is put into RB8
(S0CON special function register). The baud rate is
variable.
Mode 2: 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On
transmit, the 9th data bit (TB8 in S0CON) can be
assigned the value of 0 or 1. With nominal software,
TB8 can be the parity bit (P in PSW). During a
receive, the 9th data bit is stored in RB8 (S0CON),
and the stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 of the oscillator
frequency.
Mode 3: 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). Mode
3 is the same as Mode 2 except the baud rate which
is variable in Mode 3.
In all four modes, transmission is initiated by any instruction that
writes to the S0BUF function register. Reception is initiated in Mode
0 when RI = 0 and REN = 1. In the other three modes, reception is
initiated by the incoming start bit provided that REN = 1.
Modes 2 and 3 are provided for multiprocessor communications. In
these modes, 9 data bits are received with the 9th bit written to RB8.
The 9th bit is followed by the stop bit. The port can be programmed
so that with receiving the stop bit, the serial port interrupt will be
activated if, and only if RB8 = 1.
This feature is enabled by setting bit SM2 in S0CON. This feature
may be used in multiprocessor systems.
For more information about how to use the UART in combination
with the registers S0CON, PCON, IEN0, S0BUF and Timer register
refer to the 80C51 Data Handbook IC20.
Table 22. Description of S0CON bits
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Table 23. Description of S0CON bits
6.9.2 SIO1 (I2 C-bus Interface)
The SIO1 of the P8xC557E4 provides the fast-mode, which allows a
fourthfold increase of the bitrate up to 400 kHz. Nevertheless it is
downward compatible, i.e. it can be used in a 0 to 100 Kbit/s I2 C bus
system.
Except from the bit rate selection (see Table 25) and the timing of
the SCL and SDA signals (see AC electrical characteristics in
section 11) the SIO circuit is the same as described in detail in the
80C51 Data Handbook IC20 for the 8xC552 microcontroller.
The I2 C-bus is a simple bidirectional 2-wire bus for efficient inter-IC
data exchange. Features of the I2 C-bus are: Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA) Each device connected to the bus is software addressable by a
unique address Masters can operate as Master-transmitter or as Master-receiver It’s a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus ICs can be added to or removed from an I2C-bus system without
affecting any other circuit on the bus Fault diagnostics and debugging are simple; malfunctions can be
immediately traced
For more information on the I2C-bus specification (including
fast-mode) please refer to the Philips publication number 9398 393
40011 and/or the 80C51 Data Handbook IC20.
The on-chip I2 C logic provides a serial interface that meets the2 C-bus specification, supporting all I2 C-bus modes of operation,
they are: Master transmitter Master receiver Slave transmitter Slave receiver
The SI01 logic performs a byte oriented data transport, clock
generation, address recognition and bus control arbitration are all
controlled by hardware. Via two pins the external I2 C-bus is
interfaced to the SIO1 logic:
SCL serial clock I/O and SDA serial data I/O, (see Special Function
Register bit S1CON.6/ENS1 for enabling the SIO1 logic).
The SIO1 logic handles byte transfer autonomously. It keeps track of
the serial transfers, and a status register (S1STA) reflects the status
of SIO1 and the I2C-bus.
Via the following four Special Function Registers the CPU interfaces
to the I2C logic.
S1CON control register. Bit addressable by the CPU
S1STA status register whose contents may be used as a
vector to service routines.
S1DAT data shift register. The data byte is stable as long
as S1CON.3/SI=1.
S1ADR slave address register. It’s LSB enables/ disables
general call address recognition.
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The Control Register, S1CON:
The CPU can read from and write to this 8-bit, directly addressable
SFR. Two bits are affected by the SIO1 hardware: the SI bit is set
when a serial interrupt is requested, and the STO bit is cleared when
a STOP condition is present on the I2C bus. The STO bit is also
cleared when ENS1 = 0.
Table 24. Description of S1CON bits
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When SIO1 is in a master mode serial clock frequency is
determined by the clock rate bits CR2, CR1 and CR0. The various
bit rates are shown in Table 25.
Table 25. Selection of I2 C-bus bit rate
NOTE: These bit rates are for “fast-mode” I2 C bus applications and cannot be used for bit rates up to 100 kbit/sec.
The data shown in Table 25 do not apply to SIO1 in a slave mode. In
the slave modes, SIO1 will automatically synchronize with any clock
frequency up to 400kHz.
Serial status register S1STA
S1STA is a read only register.
The contents of the status register may be used as a vector to a
service routine. This optimizes the response time of the software
and consequently that of the I2C-bus.
Table 26. Description of S1STA bits
The following is a list of the status codes:
Table 27. MST/TRX mode
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Table 28. MST/REC mode
Table 29. SLV/REC mode
Table 30. SLV/TRX mode
Table 31. Miscellaneous
Abbreviations used:
SLA : 7-bit slave address : Read bit : Write bit
ACK : Acknowledgement (acknowledge bit = 0)
ACK : Not acknowledgement (acknowledge bit = 1)
DATA : 8-bit data byte to or from I2C-bus
MST : Master
SLV : Slave
TRX : Transmitter
REC : Receiver
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The data shift register S1DAT
This register contains the serial data to be transmitted or data which
has been received. Bit 7 is transmitted or received first; i.e., data is
shifted from right to left.
The address register S1ADR
This 8-bit register may be loaded with the 7-bit slave address to
which the controller will respond when programmed as a slave
receiver/transmitter. The LSB (GC) is used to determine whether the
general call address is recognized.
Table 32. Description of S1ADR bits
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6.10 Interrupt System
External events and the real-time-driven on-chip peripherals require
service by the CPU asynchronously to the execution of any
particular section of code. To tie the asynchronous activities of these
functions to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided. Interrupt
response time in a single-interrupt system is in the range from
2.25μs to 6.75μs when using a 16MHz crystal. The latency time
depends on the sequence of instructions executed directly after an
interrupt request.
The P8xC557E4 acknowledges interrupt requests from 15 sources
as follows (see Figure 34): INT0 and INT1 external interrupts Timer 0 and Timer 1 internal timer/counter interrupts Timer 2 internal timer/counter byte and/or 16-bit overflow, 3
compare and 4 capture interrupts (or 4 additional external
interrupts) 1 UART serial I/O port receive/transmit interrupt I2C-bus interface serial I/O interrupt ADC autoscan completion interrupt ‘Seconds’ timer interrupt SEC (ored with INT1).
For details about seconds timer interrupts, please refer to chapter
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits IT0 and IT1
in register TCON. The flags that actually generate these interrupts
are bits IE0 and IE1 in TCON. When an external interrupt is
generated, the corresponding request flag is cleared by the
hardware when the service routine is vectored to only if the interrupt
was transition-activated. If the interrupt was level-activated then the
interrupt request flag remains set until the external interrupt pin INTx
goes high. Consequently the external source has to hold the request
active until the requested interrupt is actually generated. Then it has
to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated. As these
external interrupts are active LOW a “wire-ORing” of several
interrupt sources to one input pin allows expansion.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,
which are set by a rollover in their respective timer/counter register
(except for Timer 0 in Mode 3 of the serial interface). When a Timer
interrupt is generated, the flag that generated it is cleared by the
on-chip hardware when the service routine is vectored to.
The eight Timer/Counter T2 Interrupt sources are: 4 capture
Interrupts (1), 3 compare interrupts and an overflow interrupt. The
appropriate interrupt request flags must be cleared by software.
The UART Serial Port Interrupt is generated by the logical OR of RI
and TI. Neither of these flags is cleared by hardware. The service
routine will normally have to determine whether it was RI or TI that
generated the interrupt, and the bit will have to be cleared by
software.
The I2C Interrupt is generated by bit SI in register S1CON. This flag
has to be cleared by software.
The ADC Interrupt is generated by bit ADINT, which is set when of
all selected analog inputs to be scanned, the conversion is finished.
ADINT must be cleared by software. It cannot be set by software.
The ’Seconds’ timer Interrupt is generated by bit SECINT in register
PLLCON. This flag has to be cleared by software. Note that the
’Seconds’ timer can only be used with the
32 kHz PLL oscillator.
All of the bits that generate interrupts can be set or cleared by
software, with the same result as though it had been set or cleared
by hardware (except the ADC interrupt request flag ADINT, which
cannot be set by software). That is, interrupts can be generated or
pending interrupts can be cancelled in software.
The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are capable to
terminate the Idle Mode.
Interrupt Enable Registers
Each interrupt source can be individually enabled or disabled by
setting or clearing a bit in the interrupt enable special function
registers IEN0 and IEN1. All interrupt sources can also be globally
disabled by clearing bit EA in IEN0. The interrupt enable registers
are described in Figures 34 and 36.
Interrupt Priority Structure
Each interrupt source can be assigned one of two priority levels.
Interrupt priority levels are defined by the interrupt priority special
function registers IP0 and IP1. IP0 and IP1 are described in Figures
37 and 38.
Interrupt priority levels are as follows:
“0”—low priority
“1”—high priority
A low priority interrupt may be interrupted by a high priority interrupt.
A high priority interrupt cannot be interrupted by any other interrupt
source. If two requests of different priority occur simultaneously, the
high priority level request is serviced. If requests of the same priority
are received simultaneously, an internal polling sequence
determines which request is serviced. Thus, within each priority
level, there is a second priority structure determined by the polling
sequence. This second priority structure is shown in Table 37.
Interrupt Handling
The interrupt sources are sampled at S5P2 of every machine cycle.
The samples are polled during the following machine cycle. If one of
the flags was in a set condition at S5P2 of the previous machine
cycle, the polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service routine, provided this
hardware- generated LCALL is not blocked by any of the following
conditions: An interrupt of higher or equal priority level is already in
progress. The current machine cycle is not the final cycle in the execution
of the instruction in progress. (No interrupt request will be
serviced until the instruction in progress is completed.) The instruction in progress is RETI or any access to the interrupt
priority or interrupt enable registers. (No interrupt will be serviced
after RETI or after a read or write to IP0, IP1, IE0, or IE1 until at
least one other instruction has been subsequently executed.)
