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P80C552EFA-P80C552IBA
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
Product data
Supersedes data of 1998 Aug 13
2002 Sep 03
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
DESCRIPTIONThe 80C552/83C552 (hereafter generically referred to as 8XC552)
Single-Chip 8-Bit Microcontroller is manufactured in an advanced
CMOS process and is a derivative of the 80C51 microcontroller
family. The 8XC552 has the same instruction set as the 80C51.
Three versions of the derivative exist: 83C552—8 kbytes mask programmable ROM 80C552—ROMless version of the 83C552 87C552—8 kbytes EPROM (described in a separate chapter)
The 8XC552 contains a non-volatile 8k × 8 read-only program
memory (83C552), a volatile 256 × 8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit timer
coupled to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure, an 8-input ADC, a dual
DAC pulse width modulated interface, two serial interfaces (UART
and I2C-bus), a “watchdog” timer and on-chip oscillator and timing
circuits. For systems that require extra capability, the 8XC552 can
be expanded using standard TTL compatible memories and logic.
In addition, the 8XC552 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial ports, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)
crystal, 58% of the instructions are executed in 0.75 μs (0.5 μs) and
40% in 1.5 μs (1 μs). Multiply and divide instructions require 3 μs
(2 μs).
FEATURES• 80C51 central processing unit 8k × 8 ROM expandable externally to 64 kbytes ROM code protection An additional 16-bit timer/counter coupled to four capture registers
and three compare registers Two standard 16-bit timer/counters 256 × 8 RAM, expandable externally to 64 kbytes Capable of producing eight synchronized, timed outputs A 10-bit ADC with eight multiplexed analog inputs Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs I2C-bus serial I/O port with byte oriented master and slave
functions Full-duplex UART compatible with the standard 80C51 On-chip watchdog timer Three speed ranges:
3.5 to 16 MHz
3.5 to 24 MHz (ROM, ROMless only) Three operating ambient temperature ranges:
P83C552xBx: 0 °C to +70°C
P83C552xFx: –40 °C to +85°C
(XTAL frequency max. 24 MHz)
P83C552xHx: –40 °C to +125°C
(XTAL frequency max. 16 MHz)
LOGIC SYMBOL
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
PIN CONFIGURATIONS
Plastic Leaded Chip Carrier* Do not connect.
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Plastic Quad Flat Pack* Do not connect.
IC = Internally connected (do not use).
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
BLOCK DIAGRAM
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
ORDERING INFORMATION
NOTE: xxx denotes the ROM code number. For EPROM device specification, refer to 87C552 datasheet.
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
PIN DESCRIPTION
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
PIN DESCRIPTION (Continued)
NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS – 0.5 V,
respectively.
OSCILLATOR CHARACTERISTICSXTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol, page 2.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESETA reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VDD and RST must come up at the same time for a proper start-up.
IDLE MODEIn the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
POWER-DOWN MODEIn the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
ROM CODE PROTECTION (83C552)The 83C552 has an additional security feature. ROM code
protection may be selected by setting a mask–programmable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.
The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is “don’t care” after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.
Table 1. External Pin Status During Idle and Power-Down Modes
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Serial Control Register (S1CON) – See Table 2S1CON (D8H)
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
NOTES: These frequencies exceed the upper limit of 100kHz of the I2 C-bus specification and cannot be used in an I2 C-bus application. At fOSC = 24 MHz the maximum I2 C bus rate of 100kHz cannot be realized due to the fixed divider rates.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
DEVICE SPECIFICATIONS
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
DC ELECTRICAL CHARACTERISTICSVSS, AVSS = 0 V; VDD, AVDD = 5 V ± 10%
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
DC ELECTRICAL CHARACTERISTICS (Continued)
NOTES FOR DC ELECTRICAL CHARACTERISTICS: See Figures 10 through 15 for IDD test conditions. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;
VIH = VDD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;
VIH = VDD – 0.5 V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;
EA = RST = STADC = XTAL1 = VSS. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2 V. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the
address bits are stabilizing. The following condition must not be exceeded: VDD – 0.2 V < AVDD < VDD + 0.2 V.
10.Conditions: AVREF– = 0 V; AVDD = 5.0 V, AVREF+ (80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
Philips Semiconductors Product data
80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
14.The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 1.)
15.The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
16.The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
