OP176-GBC ,Bipolar/JFET, Audio Operational AmplifierCHARACTERISTICSOutput Voltage Swing V R = 2 kΩ, –40°C ≤ T ≤ +85°C –13.5 +13.5 VO L AR = 600 Ω, V = ..
OP176GP ,Bipolar/JFET, Audio Operational AmplifierSpecifications subject to change without notice.–2– REV. 0OP176(@ V = ±15.0 V, T = +25°C unless oth ..
OP176GS ,Bipolar/JFET, Audio Operational AmplifierCHARACTERISTICSSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V ..
OP176GS ,Bipolar/JFET, Audio Operational Amplifierfeatures the Butler Amplifier front-end. This new front-end maintaining low distortion. THD + Noise ..
OP177 ,Ultra-Precision Operational Amplifierfeatures the highest precision performance of anyalternative to chopper-stabilized amplifiers. The ..
OP177AZ ,Ultraprecision Operational AmplifierSpecifications subject to change without notice.–2–REV. BOP177(@ V = 615 V, T = +258C, unless other ..
P2821 , POWERLINE CARRIER ISOLATION TRANSFORMERS
P2824 , POWERLINE CARRIER ISOLATION TRANSFORMER
P28F001BX-B120 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
P28F001BX-T120 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
P28F001BX-T150 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
P28F001BX-T150 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
OP176-GBC-OP176GP-OP176GS
Bipolar/JFET, Audio Operational Amplifier
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
Bipolar/JFET,
Audio Operational Amplifier
FEATURES
Low Noise: 6 nV/√Hz
High Slew Rate: 25 V/μs
Wide Bandwidth: 10 MHz
Low Supply Current: 2.5 mA
Low Offset Voltage: 1 mV
Unity Gain Stable
SO-8 Package
APPLICATIONS
Line Driver
Active Filters
Fast Amplifiers
Integrators
PIN CONNECTIONS
8-Lead Narrow-Body SO8-Lead Epoxy DIP
(S Suffix)(P Suffix)
GENERAL DESCRIPTIONThe OP176 is a low noise, high output drive op amp that
features the Butler Amplifier front-end. This new front-end
design combines both bipolar and JFET transistors to attain
amplifiers with the accuracy and low noise performance of
bipolar transistors, and the speed and sound quality of JFETs.
Total Harmonic Distortion plus Noise equals previous audio
amplifiers, but at much lower supply currents.
Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input
offset voltage is guaranteed at 1 mV and is typically less than
200 μV. This allows the OP176 to be used in many dc coupled
or summing applications without the need for special selections
or the added noise of additional offset adjustment circuitry.
The output is capable of driving 600 Ω loads to 10 V rms while
maintaining low distortion. THD + Noise at 3 V rms is a low
0.0006%.
The OP176 is specified over the extended industrial (–40°C to
+85°C) temperature range. OP176s are available in both plastic
DIP and SO-8 packages. SO-8 packages are available in 2500
piece reels. Many audio amplifiers are not offered in SO-8
surface mount packages for a variety of reasons, however, the
OP176 was designed so that it would offer full performance in
surface mount packaging.
*. Patent No. 5101126.
Simplified Schematic
ELECTRICAL CHARACTERISTICS
Specifications subject to change without notice.
OP176–SPECIFICATIONS
(@ VS = ±15.0 V, TA = +25°C unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±22 V
Input Voltage2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . .±7.5 V
Output Short-Circuit Duration to GND . . . . . . . . . .Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range
OP176G . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . .+300°C
NOTESAbsolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.For input voltages greater than ±7.5 V limit input current to less than 5 mA.θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC
package.
(@ VS = ±15.0 V, TA = +25°C unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP176 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.Guaranteed by CMR test.
OP176 Die Size 0.069 × 0.067 Inch, 4,623 Sq. Mils.
Substrate (Die Backside) Is Connected to V–.
Transistor Count, 26.
WAFER TEST LIMITS
DICE CHARACTERISTICS
Figure 3.Input Bias Current vs. TemperatureFigure 6.Supply Current per Amplifier vs. Supply Voltage
OP176–Typical Characteristics
Figure 1.Input Offset Voltage Drift Distribution @ ±15 VFigure 4.Maximum Output Swing vs. Frequency
Figure 2.Output Swing vs. TemperatureFigure 5.Maximum Output Swing vs. Load Resistance
120
60
20
40
100
80 54362C VOS – μV/°CAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
16 10010k1k
12
14
10
ΩLOAD RESISTANCE – Ω
OUTPUT SWING – Volts
2.50
1.50 ±25±
2.25
1.75
±5±
2.00
±15±±20±±10±
SUPPLY VOLTAGE – V
SUPPLY CURRENT – mA
TEMPERATURE – °C
ABSOLUTE OUTPUT VOLTAGE – V
30
15
10k10M1M100k1k
10
20
25
FREQUENCY – Hz
MAXIMUM OUTPUT SWING – Volts
300
150
50
100
250
200 50250
TEMPERATURE – °C
INPUT BIAS CURRENT – nA
Figure 10.Power Supply Rejection vs. FrequencyFigure 7.Short Circuit Current vs. Temperature @ ±15 V
Figure 8.Open-Loop Gain & Phase vs. FrequencyFigure 11.Open-Loop Gain vs. Temperature
Figure 12.Closed-Loop Output Impedance vs. FrequencyFigure 9. Closed-Loop Gain vs. Frequency
120
60 1M100k10k100
40
20
80
100
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
FREQUENCY – Hz
GAIN – dB
120
100
–60 10k100M10M1M100k
80
60
40
20
–20
–40
90
135
180
225
PHASE – Degrees
50
10
–30 10k100M10M1M100k
20
30
40
–20
–10
FREQUENCY – Hz
GAIN – dB
2000
500
250
1000
750
1250
1500
1750 50250
TEMPERATURE – °C
OPEN-LOOP GAIN – V/mV
80
20
10
40
30
50
60
70 50250
TEMPERATURE – °C
ABSOLUTE OUTPUT CURRENT – mA
OP176
Figure 16.Gain Bandwidth Product & Phase Margin vs.
Temperature
Figure 13.Common-Mode Rejection vs. Frequency
Figure 14.Small Signal Overshoot vs. Load CapacitanceFigure 17.Slew Rate vs. Load Capacitance
Figure 18.Slew Rate vs. TemperatureFigure 15.Slew Rate vs. Differential Input Voltage
50
30
10
20
40
LOAD CAPACITANCE – pF
SLEW RATE – V/µ
140
100 1M100k10k100
120
60
80
20
40
FRERQUENCY – Hz
COMMON-MODE REJECTION – dB
1001000
LOAD CAPACITANCE – pF
OVERSHOOT – %
35
15
10
30
20
25
SLEW RATE – V/µ
DIFFERENTIAL INPUT VOLTAGE – V
Figure 22.Large Signal Transient Response
25
20 10010k1k
15
10
FREQUENCY – Hz
VOLTAGE NOISE – nV/ Hz
Figure 21.Current Noise Density vs. FrequencyFigure 19.Voltage Noise Density vs. Frequency
Figure 20.Small Signal Transient Response
TIME – 500ns/DIV
VOUT
(5V/DIV)AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VOUT
(50mV/DIV)
TIME –100ns/DIV
OP176
APPLICATIONS
Short Circuit Protection
The OP176 has been designed with output short circuit
protection. The typical output drive current is ±50 mA. This
high output current and wide output swing combine to yield an
excellent audio amplifier, even when driving large signals, at low
power and in a small package.
Total Harmonic Distortion
Total Harmonic Distortion + Noise (THD + N) of the OP176
is well below 0.001% with any load down to 600 Ω. However,
this is dependent upon the peak output swing. In Figure 23 it is
seen that the THD + Noise with 3 V rms output is below
0.001%. In the following Figure 24, THD + Noise is below
0.001% for the 10 kΩ and 2 kΩ loads but increases to above
0.01% for the 600Ω load condition. This is a result of the
output swing capability of the OP176. Notice the results in
Figure 25, showing THD vs. VIN (V rms).
FIGURE 23. THD + Noise vs. Frequency
Figure 24. THD + Noise vs. RLOAD
Figure 25. THD + Noise vs. Output Amplitude (V rms)
The output of the OP176 is designed to maintain low harmonic
distortion while driving 600 Ω loads. However, driving 600 Ω
loads with very high output swings results in higher distortion if
clipping occurs.
To attain low harmonic distortion with large output swings,
supply voltages may be increased. Figure 26 shows the perfor-
mance of the OP176 driving 600Ω loads with supply voltages
varying from ±18 volts to ±20 volts. Notice that with ±18 volt
supplies the distortion is fairly high, while with ±20 volt supplies
it is a very low 0.0007%.
Figure 26. THD + Noise vs. Supply Voltage
Noise
The voltage noise density of the OP176 is below 6 nV/√Hz from
30 Hz. This enables low noise designs to have good perfor-
mance throughout the full audio range. Figure 27 shows a
typical OP176 with a 1/f corner at 6 Hz.
Figure 27.1/f Noise Corner
Noise Testing
For audio applications the noise density is usually the most
important noise parameter. For characterization the OP176 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure
accurately. For the OP176 the noise is gained by approximately
1020 using the circuit shown in Figure 28. Any readings on the
Audio Precision must then be divided by the gain. In imple-
menting this test fixture, good supply bypassing is essential.
Figure 28.Noise Test
Upgrading “5534‘’ Sockets
The OP176 is a superior amplifier for upgrading existing
designs using the industry standard 5534. In most application
circuits, the OP176 can directly replace the 5534 without any
modifications to the surrounding circuitry. Like the 5534, the
OP176 follows the industry standard, single op amp pinout. The
difference between these two devices is the location of the null
pins and the 5534’s compensation capacitor.
The 5534 normally requires a 22 pF capacitor between Pins 5
and 8 for stable operation. Since the OP176 is internally
compensated for unity gain operation, it does not require
external compensation. Nevertheless, if the 5534 socket already
includes a capacitor, the OP176 can be inserted without
removing it. Since the OP176’s Pin 8 is a “NO CONNECT’’
pin, there is no internal connection to that pin. Thus, the 22 pF
capacitor would be electrically connected through Pin 5 to the
internal nulling circuitry. With the other end left open, the
capacitor should have no effect on the circuit. However, to
avoid altogether any possibility for noise injection, it is recom-
mended that the 22 pF capacitor be cut out of the circuit
If the original 5534 socket includes offset nulling circuitry, one
would find a 10 kΩ to 100 kΩ potentiometer connected between
Pins 1 and 8 with said potentiometer’s wiper arm connected to
V+. In order to upgrade the socket to the OP176, this circuit
should be removed before inserting the OP176 for its offset
nulling scheme uses Pins 1 and 5. Whereas the wiper arm of the
5534 trimming potentiometer is connected to the positive
supply, the OP176’s wiper arm is connected to the negative
supply. Directly substituting the OP176 into the original socket
would inject a large current imbalance into its input stage. In
this case, the potentiometer should be removed altogether, or, if
nulling is still required, the trimming potentiometer should be
rewired to match the nulling circuit as illustrated in Figure 29.
Figure 29.Offset Voltage Nulling Scheme
Input Overcurrent Protection
The maximum input differential voltage that can be applied to
the OP176 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differen-
tial input voltage to ±7.5 V. This is to prevent emitter-base
junction breakdown from occurring in the input stage of the
OP176 when very large differential voltages are applied.
However, in order to preserve the OP176’s low input noise
voltage, internal resistances in series with the inputs were not
used to limit the current in the clamp diodes. In small signal
applications, this is not an issue; however, in applications where
large differential voltages can be inadvertently applied to the
device, large transient currents can flow through these diodes.
Although these diodes have been designed to carry a current of
±5 mA, external resistors as shown in Figure 30 should be used
in the event that the OP176’s differential voltage were to exceed
±7.5 V.
Figure 30. Input Overcurrent Protection
–VS
ΩP1 = 10kΩ
VOS TRIM RANGE = ±2mV OUTPUT
100Ω
OP176
Figure 33.Unity Gain Follower
Figure 34.Unity Gain Inverter
In inverting and noninverting applications, the feedback
resistance forms a pole with the source resistance and capaci-
tance (RS and CS) and the OP176’s input capacitance (CIN), as
shown in Figure 35. With RS and RF in the kΩ range, this pole
can create excess phase shift and even oscillation. A small
capacitor, CFB, in parallel with RFB eliminates this problem. By
setting RS (CS + CIN) = RFB CFB, the effect of the feedback pole is
completely removed.
Figure 35.Compensating the Feedback Pole
Output Voltage Phase Reversal
Since the OP176’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP176 may exhibit phase reversal if either
of its inputs exceeds the specified negative common-mode input
voltage. This might occur in some applications where a trans-
ducer, or a system, fault might apply very large voltages upon
the inputs of the OP176. Even though the input voltage range
of the OP176 is ±10.5 V, an input voltage of approximately
–13.5 V will cause output voltage phase reversal. In inverting
amplifier configurations, the OP176’s internal 7.5 V clamping
diodes will prevent phase reversal; however, they will not
prevent this effect from occurring in noninverting applications.
For these applications, the fix is a 3.92 kΩ resistor in series
with the noninverting input of the device and is illustrated in
Figure 31.
Figure 31.Output Voltage Phase Reversal Fix
Overdrive Recovery
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to a rated output
level from a saturated condition. This recovery time is impor-
tant in applications where the amplifier must recover quickly
after a large abnormal transient event. The circuit shown in
Figure 32 was used to evaluate the OP176’s overload recovery
time. The OP176 takes approximately 1μs to recover to VOUT =
+10 V and approximately 900 ns to recover to VOUT = –10 V.
Figure 32.Overload Recovery Time Test Circuit
High Speed Operation
As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement.
Recommended circuit configurations for inverting and
noninverting applications are shown in Figure 33 and Figure 34.
VIN
R2
Ω10kΩ
R1
Ω1kΩ
4Vp-p
@100Hz
+15V
10µF
0.1µF
VIN
VOUT
–15V
CFB
ΩRS
3.92kΩ
RFB*
VIN
*RFB IS OPTIONAL
Attention to Source Impedances Minimizes Distortion
Since the OP176 is a very low distortion amplifier, careful
attention should be given to source impedances seen by both
inputs. As with many FET-type amplifiers, the p-channel
JFETs in the OP176’s input stage exhibit a gate-to-source
capacitance that varies with the applied input voltage. In an
inverting configuration, the inverting input is held at a virtual
ground and, as such, does not vary with input voltage. Thus,
since the gate-to-source voltage is constant, there is no distor-
tion due to input capacitance modulation. In noninverting
applications, however, the gate-to-source voltage is not
constant. The resulting capacitance modulation can cause
distortion above 1 kHz if the input impedance is > 2 kΩ and
unbalanced.
Figure 36 shows some guidelines for maximizing the distortion
performance of the OP176 in noninverting applications. The
best way to prevent unwanted distortion is to ensure that the
parallel combination of the feedback and gain setting resistors
(RF and RG) is less than 2 kΩ. Keeping the values of these
resistors small has the added benefits of reducing the thermal
noise of the circuit and dc offset errors. If the parallel combina-
tion of RF and RG is larger than 2kΩ, then an additional
resistor, RS, should be used in series with the noninverting
input. The value of RS is determined by the parallel combina-
tion of RF and RG to maintain the low distortion performance of
the OP176. For a more generalized treatment on circuit
impedances and their effects on circuit distortion, please review
the section on Active Filters at the end of the Applications
section.
Driving Capacitive Loads
As with any high speed amplifier, care must be taken when
driving capacitive loads. The graph in Figure 14 shows the
OP176’s overshoot versus capacitive load. The test circuit is a
standard noninverting voltage follower; it is this configuration
that places the most demand on an amplifier’s stability. For
capacitive loads greater than 400 pF, overshoot exceeds 40%
and is roughly equivalent to a 45° phase margin. If the applica-
tion requires the OP176 to drive loads larger than 400 pF, then
external compensation should be used.
Figure 37 shows a simple circuit which uses an in-the-loop
compensation technique that allows the OP176 to drive any
capacitive load. The equations in the figure allow optimization
of the output resistor, RX, and the feedback capacitor, CF, for
optimal circuit stability. One important note is that the circuit
bandwidth is reduced by the feedback capacitor, CF, and is
given by:1
Figure 37. In-the-Loop Compensation Technique for
Driving Capacitive Loads
APPLICATIONS USING THE OP176
A High Speed, Low Noise Differential Line Driver
The circuit of Figure 38 is a unique line driver widely used in
many applications. With ±18 V supplies, this line driver can
deliver a differential signal of 30V p-p into a 2.5 kΩ load. The
high slew rate and wide bandwidth of the OP176 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 15nV/√Hz. The circuit is capable of driving lower
impedance loads as well. For example, with a reduced output
level of 5V rms (14 V p-p), the circuit exhibits a full-power
bandwidth of 190 kHz while driving a differential load of 249 Ω!
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer-based design, either output
can be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can
be set according to the equation in the diagram. This allows the
design to be easily set for noninverting, inverting, or differential
operation.
Figure 38. A High Speed, Low Noise Differential Line
VIN
VOUT
RF RG
FOR MINIMUM DISTORTION
Figure 36. Balanced Input Impedance to Mininize
Distortion in Noninverting Amplifier Circuits
RX = RO RG
RFRF
VOUT
WHERE RO = OPEN-LOOP OUTPUT RESISTANCE
VIN
CF=I+(I
|ACL|)(RF +RG)CLRO[ ]
