OP15 ,Precision JFET-Input Operational AmplifiersCHARACTERISTICSS A OP15A, OP15E OP15F OP15G OP17A, OP17E O ..
OP15AJ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSapplications
and the OP-215 data sheet for a dual configuration of the
OP-15.
NONINVEHTING i ..
OP15AZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSFEATURES (All Devices)
0 Significant Performance Advantages over LF155, 156 and
tttr Devices.
..
OP15FP ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSapplications requiring high closed-loop gain with high
speed. See the OP-42 data sheet for unity g ..
OP15FZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSGENERAL DESCRIPTION
The PMI JFET-input series of devices offer clear advantages
over industry-g ..
OP15FZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSfeatures of
the OP-15.
The OP-17 has a slew rate of 60V/pS and is the best choice
for
P2803NVG , N- & P-Channel Enhancement Mode Field Effect Transistor
P2803NVG , N- & P-Channel Enhancement Mode Field Effect Transistor
P2804ND5G , N- & P-Channel Enhancement Mode Field Effect Transistor_Preliminary
P2821 , POWERLINE CARRIER ISOLATION TRANSFORMERS
P2824 , POWERLINE CARRIER ISOLATION TRANSFORMER
P28F001BX-B120 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
OP15
Precision JFET-Input Operational Amplifiers
REV.A
Precision JFET-Input
Operational AmplifiersFigure 1.Simplified Schematic
FEATURES
Significant Performance Advantages over LF155 and
LF157 Devices
Low Input Offset Voltages: 500 �V Max
Low Input Offset Voltage Drift: 2.0 �V/�C
Minimum Slew Rate Guaranteed on All Models
Temperature-Compensated Input Bias Currents
Bias Current Specified Warmed-Up Over Temperature
Internal Compensation
Low Input Noise Current: 0.01 pA/÷÷÷÷÷Hz
High Common-Mode Rejection Ratio: 100 dB
Models with MIL-STD 883 Processing Available
OP15
156 Speed with 155 Dissipation: 80 mW Typ
Wide Bandwidth: 6 MHz
High Slew Rate: 13 V/�s
Fast Settling to ±0.1%: 1,200 ns
OP17
Highest Slew Rate: 60 V/�s
Fastest Settling to ±0.1%: 600 ns
Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz
Guaranteed Input Bias Current @ 125�C
GENERAL DESCRIPTIONThe ADI-JFET input series of devices offer clear advantages over
industry-generic devices and are superior in both cost and perfor-
mance to many dielectrically-isolated and hybrid op amps. All devices
offer offset voltages as low as 0.5 mV with TCVOS guaranteed to
5 mV/∞C. A unique input bias cancellation circuit reduces the IB
by a factor 10 over conventional designs. In addition ADI specifies
IB and IOS with the devices warmed up and operating at 25∞C ambient.
These devices were designed to provide real precision performance
along with high speed. Although they can be nulled, the design
objective was to provide low offset-voltage without nulling. Systems
generally become more cost effective as the number of trim circuits
is decreased. ADI achieves this performance by use of an improved
bipolar compatible JFET process coupled with on chip, zener-zap
offset trimming.
The OP15 provides an excellent combinations of high speed and
low input offset voltage. In addition, the OP15 offers the speed
of the 156A op amp with the power dissipation of a 155A. The
combination of a low input offset voltage of 500 mV, slew rate of
13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15
an op amp of both precision and speed. The additional features
of low supply current coupled with an input bias current makes
the OP15 ideal for a wide range of applications.
The OP17 has a slew rate of 60 V/ms and is the best choice for
applications requiring high closed-loop gain with high speed. See
OP42 datasheet for unity gain applications and the OP215 datasheet
for a dual configuration of the OP15.
OP15/OP17–SPECIFICATIONSNOTESInput bias current is specified for two different conditions. The TJ = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. IB and
IOS are measured at VCM = 0.Settling time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltages at the inverting input pit
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.Sample tested.Settling time is defined here for AV = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
ELECTRICAL CHARACTERISTICS(@ VS = �15 V, TA = 25�C, unless otherwise noted)
OP15/OP17
Electrical CharacteristicsNOTESSample tested.Input bias current is specified for two different conditions. The TJ = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of IB versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. IB and
IOS are measured at VCM = 0.
(@ VS = ±15 V, –55�C £ TA £ 125�C, unless otherwise noted.)NOTESSample tested.Input bias current is specified for two different conditions. The TJ = 25∞C specification is with the junction at ambient temperature; the device operating specification
ELECTRICAL CHARACTERISTICS
(@ VS = �15 V, 0�C £ TA £ 70�C for E and F grades, –40�C £ TA £ 85�C for G grades
unless otherwise noted)
OP15/OP17–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1Supply Voltage
All Devices Except C, G (Packaged)
and GR Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±22 V
C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . .±18 V
Operating Temperature
A Grade . . . . . . . . . . . . . . . . . . . . . . . . . .–55∞C to +125∞C
E, F Grades . . . . . . . . . . . . . . . . . . . . . . . . . . .0∞C to 70∞C
G Grade . . . . . . . . . . . . . . . . . . . . . . . . . . .–40∞C to +85∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . .150∞C
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Devices Except C, G Grades . . . . . . . . . . . . . . . .±40 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±30 V
Input Voltage2
All Devices Except C, G Grades . . . . . . . . . . . . . . . .±20 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±16 V
Input Voltage
OP15E, OP15F . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 V
OP15G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±16 V
OP17A, OP17E, OP17F . . . . . . . . . . . . . . . . . . . . . .±20 V
OP17G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±16 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . .300∞C
NOTES
*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
*�JA is specified for worst-case mounting conditions, i.e., �JA is specified for device
in socket for CERDIP and PDIP packages; �JA is specified for device soldered to
printed circuit board for SO packages.
ORDERING GUIDEFor military processed devices, please refer to the Standard Microcircuit Drawing
(SMD) available at www.dscc.dl.mil/programs/milspec/default.asp.
8-Lead CERDIP
(Z-Suffix)
8-Lead SOIC
(S-Suffix)
8-Lead TO-99
(J-Suffix)Figure 2.Burn-In Circuit
TPC 1.Maximum Output Swing vs. Load Performance
TPC 2.Common-Mode Input Voltage Range vs. Supply
Voltage
TPC 3.Voltage Noise vs. Source Resistance
TPC 4.Input Bias Current vs. Common-Mode Voltage
TPC 5.Open-Loop Voltage Gain vs. Supply Voltage
TPC 6.Output Voltage Swing vs. Supply Voltage
OP15/OP17TPC 7.Nulled Offset Voltage Drift vs. Potentiometer Size
TPC 8.Offset Voltage Drift vs. Temperature of
Representative Units
TPC 9.Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
TPC 10.OP15 Bias Current vs. Time in Free Air
TPC 11.OP17 Bias Current vs. Time in Free Air
TPC 12.OP15 Input Bias Current vs. Ambient Temperature
(Units Warmed Up in Free Air)
