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NVT2003DP
Bidirectional voltage-level translator for open-drain and push-pull applications
1. General descriptionThe NVT2003/04/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain or
push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level translation
application with transmission speeds <33 MHz for an open-drain system with a 50 pF
capacitance and a pull-up of 197.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits Provides bidirectional voltage translation with no direction pin Less than 1.5 ns maximum propagation delay Allows voltage level translation between: 1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B) 1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B) 1.8 V Vref(A) and 3.3 V or 5 V Vref(B) 2.5 V Vref(A) and 5 V Vref(B) 3.3 V Vref(A) and 5 V Vref(B)
NVT2003/04/06
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 5 — 19 February 2014 Product data sheet
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator Low 3.5 ON-state connection between input and output ports provides less signal
distortion5 V tolerant I/O ports to support mixed-mode signal operation High-impedance An and Bn pins for EN= LOW Lock-up free operation Flow through pinout for ease of printed-circuit board trace routing ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Packages offered: TSSOP10, HXSON12, DHVQFN16, HVQFN16, TSSOP16
3. Ordering information
3.1 Ordering options
Table 1. Ordering informationNVT2003DP N2003 3 TSSOP10 plastic thin shrink small outline package; 10 leads;
body width3 mm
SOT552-1
NVT2004TL N4 4 HXSON12 plastic, thermal enhanced extremely thin small outline
package; no leads; 12 terminals; body 1.35 2.50.5 mm
SOT973-2
NVT2006BQ N2006 6 DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
NVT2006BS N06 6 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body33 0.85 mm
SOT758-1
NVT2006PW NVT2006 6 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Table 2. Ordering optionsNVT2003DP NVT2003DP,118 TSSOP10 Reel 13” Q1/T1 *Standard mark SMD 2500 Tamb = 40 C to +85C
NVT2004TL NVT2004TL,115 HXSON12 Reel 7” Q1/T1 *Standard mark SMD 4000 Tamb = 40 C to +85C
NVT2006BQ NVT2006BQ,115 DHVQFN16 Reel 7” Q1/T1
*Standard mark SMD
3000 Tamb = 40 C to +85C
NVT2006BS NVT2006BS,118 HVQFN16 Reel 13” Q1/T1 *Standard mark SMD 6000 Tamb = 40 C to +85C
NVT2006PW NVT2006PW,118 TSSOP16 Reel 13” Q1/T1 *Standard mark SMD 2500 Tamb = 40 C to +85C
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
4. Functional diagram
5. Pinning information
5.1 Pinning
5.1.1 3-bit in TSSOP10 package
5.1.2 4-bit in HXSON12 packageNXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packagesNXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
5.2 Pin description[1] 3-bit NVT2003 available in TSSOP10 package.
[2] 4-bit NVT2004 available in HXSON12 package.
[3] 6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.
6. Functional descriptionRefer to Figure 1 “Logic diagram of NVT2003/04/06 (positive logic)”.
6.1 Function table[1] EN is controlled by the Vref(B) logic levels and should be at least 1 V higher than Vref(A) for best translator
operation.
Table 3. Pin descriptionGND 1 1 1 15 ground (0V)
VREFA 2 2 2 16 low-voltage side reference
supply voltage for An 3 3 3 1 low-voltage side; connect to VREFA
through a pull-up resistorA2 4 4 4 2 5 5 5 3 - 6 6 4 - - 7 5 - - 8 6 8 10 14 12 high-voltage side; connect to VREFB
through a pull-up resistorB2 7 9 13 11 6 8 12 10 - 7 11 9 - - 10 8 - - 9 7
VREFB 9 11 15 13 high-voltage side reference
supply voltage for Bn 10 12 16 14 switch enable input; connect to VREFB
and pull-up through a high resistor
Table 4. Function selection (example)H= HIGH level; L= LOW level.
HAn=Bn disconnect
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7. Application design-in informationThe NVT2003/04/06 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2003/04/06 is
ideal for use in applications where an open-drain driver is connected to the data I/Os. The
NVT2003/04/06 can also be used in applications where a push-pull driver is connected to
the data I/Os.
7.1 Enable and disableThe NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
[1] All typical values are at Tamb =25C.
Table 5. Application operating conditionsRefer to Figure7.
Vref(B) reference voltage (B) Vref(A) +0.6 2.1 5 V
VI(EN) input voltage on pin EN Vref(A) +0.6 2.1 5 V
Vref(A) reference voltage (A) 0 1.5 4.4 V
Isw(pass) pass switch current - 14 - mA
Iref reference current transistor - 5 - A
Tamb ambient temperature operating in
free-air
40 - +85 C
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translatorNXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.2 Bidirectional translationFor the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to Vpu(D)). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (Vref(A)) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(A) is set between 1.0 V and (Vpu(D)1 V), the output of each An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to Vpu(D).
7.3 Bidirectional level shifting between two different power domains
nominally at the same potentialThe less obvious application for the NVT2003 is for level shifting between two different
power domains that are nominally at the same potential, such as a 3.3 V system where
the line crosses power supply domains that under normal operation would be at 3.3 V, but
one could be at 3.0 V and the other at 3.6 V, or one could be experiencing a power failure
while the other domain is trying to operate. One of the NVT2003 three channel transistors
is used as a second reference transistor with its B side connected to a voltage supply that
is at least 1 V (and preferably 1.5 V) above the maximum possible for either Vpu(A) or
Vpu(B). Then if either pull-up voltage is at 0 V, the channels are disabled, and otherwise the
channels are biased such that they turn OFF at the lower pull-up voltage, and if the two
pull-up voltages are equal, the channel is biased such that it just turns OFF at the
common pull-up voltage.
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.4 How to size pull-up resistor valueSizing the pull-up resistor on an open-drain bus is specific to the individual application and
is dependent on the following driver characteristics:
The driver sink current
The VOL of driver
The VIL of the driver
Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 6, Table 7 and Table 8 contain suggested minimum values of pull-up resistors for
the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same.
VOL =VIL =0.1 VCC and accounts for a 5%VCC tolerance of the supplies, 1%
resistor values. It should be noted that the resistor chosen in the final application should
be equal to or larger than the values shown in Table 6, Table 7 and Table 8 to ensure that
the pass voltage is less than 10 % of the VCC voltage, and the external driver should be
able to sink the total current from both pull-up resistors. When selecting the minimum
resistor value in Table 6, Table 7 or Table 8, the drive current strength that should be
chosen should be the lowest drive current seen in the application and account for any
drive strength current scaling with output voltage. For the GTL devices, the resistance
table should be recalculated to account for the difference in ON resistance and bias
voltage limitations between VCC(B) and VCC(A).
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Table 6. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx
Table 7. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.5 How to design for maximum frequency operationThe maximum frequency is limited by the minimum pulse width LOW and HIGH as well as
rise time and fall time. See Equation 1 as an example of the maximum frequency. The rise
and fall times are shown in Figure 11.
(1)
The rise and fall times are dependent upon translation voltages, the drive strength, the
total node capacitance (CL(tot)) and the pull-up resistors (RPU) that are present on the bus.
The node capacitance is the addition of the PCB trace capacitance and the device
capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component of the rise and fall times is the RC time constant of the bus line when
the device is in its two primary operating states: when device is in the ON state and it is
low-impedance, the other is when the device is OFF isolating the A-side from the B-side.
A description of the fall time applied to either An or Bn output going from HIGH to LOW is
as follows. Whichever side is asserted first, the B-side down must discharge to the VCC(A)
voltage. The time is determined by the pull-up resistor, pull-down driver strength and the
Table 8. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translatorcapacitance. As the level moves below the VCC(A) voltage, the channel resistance drops
so that both A and B sides equal. The capacitance on both sides is connected to form the
total capacitance and the pull-up resistors on both sides combine to the parallel equivalent
resistance. The Ron of the device is small compared to the pull-up resistor values, so its
effect on the pull-up resistance can be neglected and the fall is determined by the driver
pulling the combined capacitance and pull-up resistor currents. An estimation of the actual
fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A)
voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.
A description of the rise time applied to either An or Bn output going from LOW to HIGH is
as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides
are essentially one node. They will rise together with an RC time constant that is the sum
of all the capacitance from both sides and the parallel of the resistance from both sides.
As the signal approaches the VCC(A) voltage, the channel resistance goes up and the
waveforms separate, with the B side finishing its rise with the RC time constant of the side. The rise to VCC(A) is essentially the same for both sides.
There are some basic guidelines to follow that will help maximize the performance of the
device:
Keep trace length to a minimum by placing the NVT device close to the processor.
The signal round trip time on trace should be shorter than the rise or fall time of signal
to reduce reflections.
The faster the edge of the signal, the higher the chance for ringing.
The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher
the frequency the device can use.
The system designer must design the pull-up resistor value based on external current
drive strength and limit the node capacitance (minimize the wire, stub, connector and
trace length) to get the desired operation frequency result.
8. Limiting values[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
[2] Low duty cycle pulses, not DC because of heating.
Table 9. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Vref(A) reference voltage (A) 0.5 +6 V
Vref(B) reference voltage (B) 0.5 +6 V input voltage 0.5[1] +6 V
VI/O voltage on an input/output pin 0.5[1] +6 V
Ich channel current (DC) - 128 mA
IIK input clamping current VI <0V 50 - mA
IOK output clamping current [2] 50 +50 mA
Tstg storage temperature 65 +150 C
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
9. Recommended operating conditions[1] Vref(A) Vref(B)1 V for best results in level shifting applications.
10. Static characteristics[1] All typical values are at Tamb =25C.
[2] Not production tested, maximum value based on characterization data of typical parts.
[3] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two terminals.
[4] See curves in Figure 12 for typical temperature and VI(EN) behavior.
[5] Guaranteed by design.
Table 10. Operating conditionsVI/O voltage on an input/output pin An, Bn 0 5.5 V
Vref(A) reference voltage (A) VREFA [1] 05.4 V
Vref(B) reference voltage (B) VREFB [1] 05.5 V
VI(EN) input voltage on pin EN 0 5.5 V
Isw(pass) pass switch current - 64 mA
Tamb ambient temperature operating in free-air 40 +85 C
Table 11. Static characteristicsTamb= 40 C to +85 C, unless otherwise specified.
VIK input clamping voltage II= 18 mA; VI(EN) =0V - - 1.2 V
IIH HIGH-level input current VI =5 V; VI(EN)=0V --5 A
Ci(EN) input capacitance on pin EN VI=3 V or 0V - 12 - pF
Cio(off) off-state input/output capacitance An, Bn; VO =3V or0V;
VI(EN) =0V 57pF
Cio(on) on-state input/output capacitance An, Bn; VO =3V or0V;
VI(EN) =3V
-11.5 13[2] pF
Ron ON-state resistance An, Bn; VI =0V;IO =64mA;
VI(EN) =4.5V
[3][4][5] 12.4 5.0 =2.4 V; IO =15mA;
VI(EN) =4.5V
[3][4] -4.8 7.5
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
11. Dynamic characteristics
11.1 Open-drain drivers[1] See graphs based on Ron typical and Cio(on) +CL =50pF.
Table 12. Dynamic characteristics for open-drain driversTamb= 40 Cto+85 C; VI(EN) =Vref(B); unless otherwise specified.
Figure15tPLH LOWto HIGH
propagation delay
from (input) Bn (output) An
[1] Ron (CL + Cio(on))ns
tPHL HIGHto LOW
propagation delay
from (input) Bn (output) An
Ron (CL + Cio(on))ns
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
12. Performance curvestPLH up-translation is typically dominated by the RC time constant, i.e.,
CL(tot) RPU =50pF 197= 9.85 ns, but the Ron CL(tot) =50pF5 =0.250 ns.
tPHL is typically dominated by the external pull-down driver + Ron, which is typically small
compared to the tPLH in an up-translation case.
Enable/disable times are dominated by the RC time constant on the EN pin since the
transistor turn off is on the order of ns, but the enable RC is on the order of ms.
Fall time is dominated by the external pull-down driver with only a slight Ron addition.
Rise time is dominated by the RPU CL.
Skew time within the part is virtually non-existent, dominated by the difference in bond
wire lengths, which is typically small compared to the board-level routing differences.
Maximum data rate is dominated by the system capacitance and pull-up resistors.
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
13. Package outline
