NTHD5903T1G ,Power MOSFET Dual P-Channel ChipFET™ 2.1 A, 20 V2REV. AAND8061/D200Junction–to–Ambient Thermal Resistance(dependent on the pcb size)Min. FootprintT ..
NTHD5904NT1 ,Power MOSFET 20 V, 3.1 A, N-Channel Dual ChipFET™ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Test Condition M ..
NTHD5904NT1G ,Power MOSFET 20 V, 3.1 A, N-Channel Dual ChipFET™APPLICATION NOTECHARACTERISTICS DESCRIPTIONThe attached SPICE Model describes typical electrical• N ..
NTHD5904T1 ,Power MOSFET Dual N-ChannelELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Test Condition M ..
NTHD5905T1 ,OBSOLETEELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Test Condition M ..
NTHS2101PT1 ,Power MOSFET 8 V P-Channel Single ChipFET™ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Test Condition M ..
OV6680 , optimal low-light sensitivity and pixel performance for video conferencing cameras in 3G mobile phones
OV6680 , optimal low-light sensitivity and pixel performance for video conferencing cameras in 3G mobile phones
OV7411 , SINGLE-CHIP CMOS COLOR PAL CAMERA
OV-7604-C7 , Low Power Clock Oscillator 32.768 kHz
OV7670 , 1/6 inch VGA CameraChip for ultra-thin camera modules
OV7670 , 1/6 inch VGA CameraChip for ultra-thin camera modules
NTHD5903T1-NTHD5903T1G
Power MOSFET Dual P-Channel ChipFET™ 2.1 A, 20 V
features the same outline as popular 1206A Figure 2, on the following page. This is sufficient for lowresistors and capacitors but provide all the performance of power dissipation MOSFET applications, but powertrue power semiconductor devices. The 1206A ChipFET semiconductor performance requires a greater copper padhas the same footprint as the body of the LITTLE FOOT area, particularly for the drain leads.TSOP–6, and can be thought of as a leadless TSOP–6 forThe minimum recommended pad pattern shown inpurposes of visualizing board area, but its thermalFigure 3 improves the thermal area of the drain connectionsperformance bears comparison with the much larger SO–8.(pins 5 and 6, pins 7 and 8) while remaining within theThis technical note discusses the dual ChipFET 1206Aconfines of the basic footprint. The drain copper area ispin–out, package outline, pad patterns, evaluation board0.0019 sp. in. or 1.22 sq. mm. This will assist the powerlayout, and thermal performance.dissipation path away from the device (through the copperleadframe) and into the board and exterior chassis (ifPin–Outapplicable) for the dual device. The addition of a furtherFigure 1 shows the pin–out description and Pin 1copper area and/or the addition of vias to other board layersidentification for dual–channel 1206A ChipFET device.will enhance the performance still further. An example ofThe pin–out is similar to the TSOP–6 configuration, withthis method is implemented on the ON Semiconductortwo additional drain pins to enhance power dissipation andEvaluation Board described in the next section (Figure 4).thus thermal performance. The legs of the device are veryshort, again helping to reduce the thermal path to theexternal heatsink/pcb and allowing a larger die to be fittedin the device if necessary.STYLE 2:PIN 1. SOURCE 18 2. GATE 1 3. SOURCE 4. GATE 2 5. DRAIN 1 6. DRAIN 11 7. DRAIN 2 8. DRAIN 2Figure 1. Dual 1206A ChipFET Semiconductor Components Industries, LLC, 20011 Publication Order Number:May, 2001 – Rev. 0 AND8061/DAND8061/D80 mil 80 mil28 mil1 81 825 mil 43 mil25 mil2 72 73 63 618 mil 4 518 mil4 510 mil26 mil26 milFigure 2. Basic Pad Layout Figure 3. Minimum Recommended Pad PatternThe ON Semiconductor Evaluation Board Thermal Performancefor the Dual 1206AJunction–to–Foot Thermal Resistance (the PackageThe dual ChipFET 1206A evaluation board measures 0.6Performance)in. by 0.5 in. Its copper pad pattern consists of an increasedThermal performance for the 1206A ChipFET measuredpad area around each of the two drains leads on the topas junction–to–foot thermal resistance is 30°C/W typical,side– approximately 0.0246 sq. in. or 15.87 sq. mm–and40°C/W maximum for the dual device. The “foot” is thevias added through to the underside of the board, again withdrain lead of the device as it connects with the body. Thisa maximized copper pad area of approximately theis indexical to the dual SO–8 package R performance, ajaθboard–size dimensions, split into two for each of the drains.feat made possible by the shortening the leads to the whereThe outer package outline is for the 8–pin DIP, which willthey become only a small part of the total footprint area.allow test sockets to be used to assist in testing.The thermal performance of the 1206A on this board hasbeen measured with the results following on the next page.The testing included comparison with the minimumrecommended footprint on the evaluation board–size pcband the industry standard one–inch square FR4 pcb withcopper on both sides of the board.Front of Board Back of BoardChipFETS1 D1G1 D1S2 D2G2 D21206–8 DUALFigure 4. Evaluation Board
