NSC810AN ,NSC810A RAM -I/OElectrical Characteristics vac: 5V :10%, GND=0V, unless otherwise specified.
Symbol Parameter Co ..
NSCB100AT , SPECIFICATIONS FOR NICHIA CHIP TYPE BLUE LED
NSCW455AT , TYPE WHITE LED
NSCW505CT , TYPE WHITE LED
NSD03A10 , Low Forward Voltage Drop Diode
NSD03A40 , Low Forward Voltage Drop Diode
OPA2336UAG4 ,Single-Supply, MicroPower CMOS Operational Amplifiers MicroAmplifier Series 8-SOIC -40 to 85MAXIMUM RATINGSELECTROSTATICSupply Voltage .. 7.5VDISCHARGE SENSITIVITY(2)Signal Input Terminals, V ..
OPA2336UG4 ,Single-Supply, MicroPower CMOS Operational Amplifiers MicroAmplifier Series 8-SOIC -40 to 85)OPA336for design analysis.Out 1 5 V+OPA4336V– 2Out A 1 16 Out D+In 3 4 –In–In D–In A 2 15ADSOT23-5 ..
OPA2337EA ,Brown Corporation - MicroSIZE, Single-Supply CMOS OPERATIONAL AMPLIFIERS MicroAmplifier ™ Series
OPA2337EA ,Brown Corporation - MicroSIZE, Single-Supply CMOS OPERATIONAL AMPLIFIERS MicroAmplifier ™ Series
OPA2337EA ,Brown Corporation - MicroSIZE, Single-Supply CMOS OPERATIONAL AMPLIFIERS MicroAmplifier ™ Series
OPA2337EA/250G4 ,MicroSIZE, Single-Supply CMOS Operational Amplifier MicroAmplifier Series 8-SOT-23 ""#$ %""#""&$ %""&
NSC810AN
NSC810A RAM -I/O
NSC81OA
National .
i Semiconductor
NSC81OA RAM-I/O-Timer
General Description
The NSC810A, the luxury model of our NSCBOOTM peripher-
al line, sports triple ported I/O, dual 16-bit timers and a
1024-bit static storage area. The three ports can be com-
bined for a total of 22 general purpose l/C) lines. In addition,
port A has several strobed mode operations. Note the sin-
gle instruction i/O bit operations for quick and efficient data
handling from the ports. The timers feature 6 modes of op-
eration and prescalers for those complicated timing tasks.
The NSC810A comes in two models: the Dual-ln-Line (DIP)
and the surface mount chip carrier (LCC). It also comes in
three exciting temperature ranges (Commercial, Industrial,
and Military) and two reliability flows (extended burn-in and
military class B in accordance with Method 6004 of MIL.
STD-883). This is brought to you through the microCMOS
silicon gate technology of National Semiconductor.
Features
I: Three programmable I/O ports
I: Dual 16-bit programmable counter/timers
" 2.4V-6.0V power supply
I: Very low power consumption
a Fully static operation
a Single-instruction I/O bit operations
I: Timer operation-DC to 5 MHz
" Bus compatible with NSCBOOTM family
" Speed: compatible with NSC800
NSC810A-4 - NSCBOO-4 a 4.0 MHz
NSC810A-3 - NSCSOO © 2.5 MHz
NSC810A-1 - NSC800-1 tit 1.0 MHz
NSC810A Connection Diagram
tro-ii:
cu MOT " vac min (I) Rt min (I)
- INTI A0tl-T 4='c'h=--tr Amq POITA
i3) um
_ W. l. C (3)
“4, -"'"-ts
- m m 4=""-tr you n
' m ' CE nswu um
- " M e M I/tt TIOUT "-ls.
uscaoo WI 4 WI mm m
q-SI (m, mu -
- m Abe ALE m m FORT
Eu 1an ' mm] STE n2. um
‘m ESET our - nesn " m I
- w m E.
- " TMor- I'M"
m; . t. merTg m _,Tmenu
Ttlk - Ill us a
TL/C/5517-1
This Material Copyrighted By Its Respective Manufacturer
Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS 9.0 FUNCTIONAL DESCRIPTION
2.0 OPERATING CONDITIONS 9.1 Random Access Memory (RAM)
9.2 D t il Bl k .
3.0 cc ELECTRICAL CHARACTERISTICS t9 ttt ed oc Diagram
9.3 I/O Ports
4.0 AC ELECTRICAL CHARACTERISTICS 9.3.1 Registers
5.0 TIMER Ac ELECTRICAL CHARACTERISTICS 9.3.2 Modes
tho TIMING WAVEFORMS 9.4 Timers
7.0 pm DESCRIPTIONS 9.4.1 Registers
9.4.2 Timer Pins
7,1 Input Signals 9.4.3 Timer Modes
7.2 Output Signals 9 4 4 Timer Programmlng
7.3 Power Supply Signals ' .
7.4 Input/Output Signals 10.0 NSCB10/883 M1LAmN883/CLASS B SCREENING
8.0 CONNECTION DIAGRAMS 11.0 BUHN-IN CIRCUIT
12.0 TIMING DIAGRAM
13.0 ORDERING INFORMATION
14.0 RELIABILITY INFORMATION
This Material Copyrighted By Its Respective Manufacturer
VOIBOSN
NSC810A
1.0 Absolute Maximum Ratings
(Note 1)
" Mllltary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutors for avallablllty and speclflcatlons.
Storage Temperature Range -65''C to + 15ty'C
Voltage at Any Pin with Respect
2.0 Operating Conditions
Vcc = 5V i 10%
NSCB10A-1 - ty'C to +70°C
-40oC to +85°C
NSC810A-3 - 0°C to +70°C
-40°C to +85°C
-55°C to + 125°C
to Ground -0.3V to Vcc + 0.3V NSC810A-4 _ 0°C to + 70°C
Vcc 7V -40''C to +tMPC
Power Dissipation IW -55 C to + 125 C
Lead Temperature (Soldering, 10 seconds) 300°C
3.0 DC Electrical Characteristics vcc=5v 110%. GND--OV, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
VIH Logical 1 Input Voltage 0.8 V60 Vcc V
" Logical 0 Input Voltage 0 0.2 Vcc V
VOH Logical 1 OutputVoltage 10H : - 1.0 mA 2.4 V
IOUT = -10 [J.A VcC-0.5 V
VOL Logical 0 Output Voltage '0L = 2 mA 0 0.4 V
IOUT = 10 “A o 0.1 v
IIL Input Leakage Current 0 S VIN s Vcc -10.0 10.0 w/k
IOL Output Leakage Current o S VIN g Vcc -10.0 10.0 WA
'00 Active Supply Current IOUT = 0, Timer = Mode 1, TOIN = TIIN = 2.5 Mhz, 8 10 mA
twcy = 750 ns, TA == 25°C
la QuiescentCurrent No lnputswitchi1iy TA =_25°C, - 10 100 pA
RESET=0,l0/M--1,HD--1, R=1,ALE=1,
VIN == Vcc, W = 0 Hz, tOUT = 0
cm Input Capacitance 7 pF
COUT Output Capacitance 10 pF
Vcc Power Supply Voltage (Note 2) 2.4 5 6 V
Vtorw Data Retention Voltage 1.8 V
not tested.
lcc—SUPPLY CURRENT (mA)
Icc vs Speed
MAXIMUM
4500 3000 1500 1000 750
NICV ing)
il 1 2 3 4
Mscsoo CLOCK span" mm)
TL/C/5517-2
'When NSCB10A is used with NSCBOO
Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed, Continuous operation at these limits is not
intended; operation should be limited to those conditions specified under DC Electrical Characteristics.
Note 2: Operation at lower power supply voltages will reduce the maximum operating speed. Operation at voltages other than 5V i 10% is guaranteed by design,
This Material Copyrighted By Its Respective Manufacturer
4.0 AC Electrical Characteristics vcc=5v A10%, GND=0V
Symbol Parameter Condltlons NSC810AM "SCMOA'S "scam": Unlts
Mln Max Mln Max Mln Max
tACC Access Time from ALE th. = 150 pF 1000 400 300 ns
tAH ADO-7, GE, tOT/ha Hold Time 100 60 30 ns
tALE ALE Strobe Width (High) 200 125 100 ns
tARw ALE to W or ilflA Strobe 150 120 75 ns
tAs ADO-7, CE, iOT/Vh Set-Up Time 100 45 25 ns
tDH Data Hold Time 150 90 40 ns
too Port Data Output Valid 350 310 300 ns
tDs Data Set-Up Time 100 80 50 ns
tPE Peripheral Bus Enable 320 200 200 ns
tpH Peripheral Data Hold Time 150 125 100 ns
tps Peripheral Data Set-Up Time 100 75 50 ns
tpz Peripheral Bus Disable (T RI-STATE') 150 150 150 ns
tRB m to BF Invalid 300 300 300 ns
tRD Read Strobe Width 400 320 185 as
1990 Data Bus Disable 0 100 0 100 0 75 ns
tm Al5 to IN-TR Output 320 320 300 ns
IRWA tTr5 or W to Next ALE 125 100 75 ns
tSB W to BF Valid 300 300 300 ns
tSH Peripheral Data Hold with Respect to gtg 150 125 100 ns
tty tTN to FtrA Output 300 300 300 ns
tss Peripheral Data Set-Up with Respect to Trg 100 75 50 ns
tsw m Width 400 320 220 ns
twa ihM to BF Output 340 340 300 ns
tw, W to W Output 320 320 300 ns
twn Fim Strobe Width 400 320 220 ns
twcy Width of Machine Cycle 3000 1200 750 ns
Note: Test conditions: twcy = 3000 ns tor NSC810A-1, 1200 ns for NSCB10A-3, 750 ns for NSCS10A-4
5.0 Timer AC Electrical Characteristics
Symbol Parameter Conditions Mln Typ Max Units
Fc Clock Frequency DC 2.5 MHz
Fcp Clock Frequency Prescale Selected DC 5.0 MHz
tcw Clock Pulse Width 150 ns
tcwp Clock Pulse Width Prescale Selected 75 ns
tas Gate Set-Up Time With Respect to Negative Clock Edge 100 ns
tGH Gate Hold Time With Respect to Negative Clock Edge 250 ns
tco Clock to Output Delay CL = 100 pF 350 ns
AC TESTING INPUT/OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT
Ila Vac " 1ted DEVICE
0.2 V " ll UNDER
TLfG/5tit7-3 TESI 1
= TL/C/5517-4
This Material Copyrighted By Its Respective Manufacturer
VOLQOSN
6.0 Timing Waveforms
Tlmer Waveforms
NSC81OA
ttt iic_r'-"hc_,y'"'"""""h_,,,.
In ten
OUTPUT X-"-'.
(ACTIVE UNO h-..,,-,.,-,?
Road Cyclo (Road from RAM, Port or Tlmer)
TL/C/5517-6
tttttR um -0 tht 1
M (0-7) ms: ' m can VALID
-m ucc I
Wm Moo
7lll'fltsk DATA VALID
In -_--- m
TL/C/5517-8
Note: Diagonal lines indicate interval ot invalid data.
Write Cycle (Write to RAM, Port or Tlmer)
L, Nev
m l _l m :w.
MI too
PERIPHERAL y
(roan nus
TLft3/5517-7
Note: Diagonal lines Indicate Interval of invalid data.
This Material Copyrighted By Its Respective Manufacturer
6.0 Timing Waveforms (Continued)
tsig -
Strobed Mode Input
PERIPHERAL
(PORT A) aus
DATA VALID A
"11'l "lllF%lllllllllllllllllllllllllllllllllmlll%h 1llllmllll,
Au (0-7) '%%ll0li%iilllllllll,
-''""'""71 tst 7:
iiiiiiiiiiii
/_\___
PORT A
ADDRESS VALID
'%llllalll%lllllllllllC= HKD---
Note: Diagonal lines indicate interval ot invalid data.
's,,-....,.)'-
TL/C/551 7-8
Strobed Mode Output
mfg? ////////// 'lllllllllllllllllllllllllllll%lllllaaaalllllallllMalh,
AO (0-7) "lllllllh Cmkissvii?lilllllililllr, 'llllllllllllllllllllllllllllllllllllllmllmllh
ALE _\
""-"-""-""""L.,-/'"
'c-j- "c)
""-j-t mid E
L--ts-
ACTIVE ("ODE t)
OLD DATA
NE:W um
PORT A 31181
TRl-STATE (MODE 3)
Note: Diagonal lines indicate interval of invalid data.
TL/Cf5517-t?
This Material Copyrighted By Its Respective Manufacturer
VOLSOSN
NSC810A
7.0 Pin Descriptions
The function and mnemonic for the NSCB10A signals are
described below:
7.1 INPUT SIGNALS
Reset (RESET): RESET is an active-high input that resets
all registers to o (low). The RAM contents remain unaltered.
lnput/Output Timer or RAM Select tityr/My tOT/V/ is an
l/O memory select input line. A logic 1 (high) input selects
the I/O-timer portion of the chip; a logic 0 (low) input selects
the PAM portion of the chip. IOT/M is latched at the falling
edge of ALE.
Chip Enable (CE): CE is an active-high input that allows
access to the NSC81OA. CE is latched at the falling edge of
Read (W): The AD is an active-Iow input that enables a
read operation of the RAM or IIO-timer location.
Write (W): The W is an active-low input that enables a
write operation to RAM or I/O-timer locations.
Address Latch Enable (ALE): The falling edge of the ALE
input latches ADO-AD?, CE and lOT/V inputs to form the
address for RAM, I/O or timer.
Timer 0 Input (TOIN): TOIN is the clock input tor timer 0.
7.2 OUTPUT SIGNALS
Tlmer 0 Output (TOOUT): TOOUT is the programmable out-
put of timer 0. After reset, TOOUT is set high.
7.3 POWER SUPPLY SIGNALS
Positive Dc Voltage (Vcc): Vcc is the 5V supply pin.
Ground (GND): Ground reference pin.
8.0 Connection Diagrams
DuaI-ln-Llne Package
PC3/TB - , 0 V " w-.- Vcc
PCQI‘HIN - 2 38 - PCZ/STB
WIN - 3 38 - PCI/BF
RESET - a 37 - Psalm
PCS/TIOUT - 5 38 - P37
TNUT -- ti 35 - Pti6
IOT/H - 7 34 k-- PBS
CE - tt 33 i-- FBI
M --u g 32 - P33
W = 10 "scum 31 - P82
ALE - 11 30 - P31
ADO -- It 29 - P80
AM-x 13 28 - PAY
A02 - " 27 - m
A03 - " " - ms
AN - " " - PM
Atm - " " - H3
I06 - " " _ PR2
A07 - " " _.-.. PM
tmo - " " _ PM)
TL/C/5517-10
Top View
Order Number NSC$10AD or NSCMOAN
See NS Package Number mac or N40A
TA INPUT/OUTPUT SIGNALS
Address/Data Butt (ADO-ADT): The multiplexed bidirec-
tional address/data bus; ADO-AD? pins, are in the high im-
pedance state when the NSC810A is not selected.
ADO-AD7 will latch address inputs at the falling edge of
ALE. The address will designate a location in RAM, I/O or
timer. W input enables 8-bit data to be written into the
addressed location. tTO input enables 8-bit data to be read
from the addressed location. Tho AO or BTA- inputs occur
while ALE is low.
Port A, 0-7 (PAO-PA7): Port A is an 8-bit basic mode in-
put/output port, also capable of strobed mode " utilizing
three control signals from port G. Strobed mode of opera-
tion on port A has three different modes; strobed input,
strobed output with active peripheral bus, strobed output
with TRl-STATE peripheral bus.
Port B, 0-7 (PBO-PB7): Port B is an 8-bit basic mode in-
put/output port.
Port C, 0-5 (PCO-PCS): Port C is a 6-bit basic mode I/O
port. Each pin has a programmable second function, as lol-
PCO/INTR: INTR is an active-low, strobed mode interrupt
request to the Central Processor Unit (CPU).
PCOBF: BF is an active-high, strobed mode, buffer full
output to peripheral devices.
P02ISTB: STB is an active-low, strobed mode input from
peripheral devices.
P03/TG: TG is the timer gating signal.
PCd/Tth: T1lN is the clock input for timer 1.
PC5fT1OUTrT1OUT is the programmable output of tim-
Chip Carrier
PCS/TIDU‘I tom Til Vcc PCi/BF
"ssssss''s1'ss1iss,):'t"C " l PCZIV Peo/im m
stts1sl l / Ua-tf---""
6 5 4 3 2 1 " 43 " 41 4tl
mom 7 o " m
IOT/M a 38 P85
CE 9 37 P34
M 10 " P33
Wii 11 35 932
" It NSCBIOA M MI
ALE 13 33 Pat
ADO " " m
A01 15 at m
Mt 16 30 FAG
A03 l? 29 ms
" 19 20 2122 23 " " tii " tlt
,////f t l t,INN,
AN A05 Athi A07 tmo " PM PM Ph? PA3 PA!
TLfC/5517-t1
Top View
NC-no connect
Order Number NSC810AE or NSCMOAV
See NS Package Number EMB or V44A
This Material Copyrighted By Its Respective Manufacturer
9.0 Functional Description
Figure 1 is a detailed block diagram of the NSCB10A. The
functional description that follows describes the RAM, I/O
and TIMER sections.
9.1 RANDOM ACCESS MEMORY (RAM)
The memory portion of the RAM-l/O-tir- is accessed by _a
7-bit address input to pins ADO through A06. The IOT/M
9.2 DETAILED BLOCK DIAGRAM
input must be low (RAM select) and the CE input must be
high at the falling edge of ALE to address the RAM. Address
bit AD? is a "don't care" for RAM addressing. Timing for
RAM read and write operations is shown in the timing dia-
grams. The RAM is 128 x 8.
INIEBNAL
ct mun
Rh - l
, HANDSHAKE l D
tit) - comm LOGIC
- 7 me 21-N
IOT/M _ 4=z===-=-ts PORT A 4 Ir-'-""--,' , PAD-PA7
ALE lo
nesa _
i 29-35
mm a @=> m-m
1024 ans 4:=ts
nzaxa) Mtl _
12-19 ADDRESS/ 37-39. 1. t. 5
ADO-AD? 4='r4ts om
aumns mo PORT c 4===tr
LATCHES
nun NANDSHAKE
c - AND TIMER
ruucrmns
TIMER MODE
REGISTERS r
T1 COMMAND <=> 4==ty n oausn
Low TI
m comm Fly Ft), Tt 0am - mescm
mm _ m PRESCALE 4==ty TO mlm = roour
masons 4==ts To mm
yes j 0 DE
tmo--.
TL/C/5517-12
FIGURE 1
This Material Copyrighted By Its Respective Manufacturer
VOL8OSN
NSC810A
9.0 Functional Description (Continued)
9.3 vo PORTS
The three I/O ports, labeled A, B, and C, can be pro-
grammed to be almost any combination of Input and Output
bits. Ports A and B are configured as 8 bits wide, while port
C is 6 bits. There are four different modes of operation for
the ports. Three of the modes are for timed transfer of data
between the peripheral and the NSC810A, this is called
strobed l/O. The fourth mode is for direct transfer without
handshaking with the peripheral.
The NSCS1OA can be programmed to operate in four differ-
ent modes. One of these modes (Basic IIO) allows direct
transfer of I/O data without any handshaking between the
NSC810A and the peripheral. The other three modes
(Strobed l/O) provide for timed transfers of HO data with
handshaking between the NSCB10A and the peripheral.
The determination of the mode, data direction and data is
done by five registers which are, handily, under program
control. The Mode Definition Register (MDR), oddly enough,
determines which mode the device will operate in, while the
Data Direction Register (DDR) establishes the direction of
the data transfer. The Data register contains the data that is
being sent or has been received. The other two registers
(bit-set, bit-clear) allow the individual bits in the data register
to be set or cleared without affecting the other bits. Each
port has its own set of these registers, except the MDR
which affects ports A and C only.
In the strobed l/O modes, port C bits 0, 1 and 2 function as
INTR (for the processor), BF, and STB respectively.
9.3.1 Registers
As can be seen in Table l, all the registers affecting IIO
transfer are grouped at the lower address locations, this
allows quicker handling and more maneuverability in tight
data transfers. Also note in Table I that the NSCB1OA uses
23 VD addresses out of a block of 26. The upper three bits
of the address are determined by the chip enable address.
. Mode DtHittitlort Register (MDR)
As noted above this register defines the operating mode for
ports A and C (port B is always in the basic I/O mode), The
upper 3 bits of port C will also be in the basic I/O mode
even when the lower 3 bits are being used for handshaking.
The four modes are as follows:
Mode o-Basic I/O (Input or Output)
Mode 1-Strobed Mode Input
Mode 2--Strobed Mode Output (Active Peripheral Bus)
Mode 34trobed Mode Output (TRI-STATE Peripheral
The address assignment of the MDR is mom 11 as shown
in Table I. Table II specifies the data that must be loaded
into the MDR to select the mode.
. Data Direction Registers (DDR)
Each port has a DDR that determines whether an individual
port bit will be an input or an output. This can be considered
the traffic light for the transfer of data between the CPU and
the peripheral. Each port bit has a corresponding bit in this
register. If the DDR bit is set (1) the port bit is an output; if it
is cleared (O) the port bit is an input. The DDR bits cannot
be written to individually. The register as a whole must be
set to be consistent with all desired port bit directions.
TABLE I. vo and Tlmer Address Designations
8-Blt Adages Field Designation R (Read)
7 6 5 4 3 2 , 0 I/O Port,Tlmar,ete. W(erte)
x x x 0 o 0 t) O PortA(Data) R/W
x x x o 0 O 0 1 PortB(Data) R/W
x x x 0 0 0 1 o PortC(Data) R/W
x It x 0 0 0 1 1 NotUsed ..
x x x 0 010 0 DDH-PortA W
x x x 0 0 1 0 1 DDR-PortB W
x x x o o 1 1 0 DDR-PortC W
x x It O 0 1 1 1 Mode Definition Reg. W
x x x 0 1 o O 0 PortA-Bit-Clear W
x x x 0 1 0 O 1 PortB-Bit-Clear W
x x x 0 1 o 1 0 PortC-Bit-Clear W
x x x o 1 O 1 1 NotUsed ..
x x x 0 1 1 0 0 PortA-Bit-Set W
x x x 0 1 1 0 1 PortB-Bit-Set W
x x x 0 1 1 1 0 PortC-Bit-Set W
x x x 0 1 1 1 1 NotUsed ..
x x x 1 0 0 0 0 Timer0(LB) .
x x x 1 0 0 0 1 Timer0(HB) .
x x x 1 0 0 1 o Timer1(LB) .
x x x 1 0 o 1 1 Timer1(HB) .
x x x 1 O 1 o 0 STOPTimerO w
x x x 1 O 1 0 1 STARTTimerO w
x x x 1 0 1 1 0 STOPTimer1 W
x x x 1 0 1 1 1 STARTTimer1 W
x x x 1 1 0 o 0 TimerOMode R/W
x It x 1 1 O 0 1 TimertMode R/W
x x x 1 1 0 1 0 NotUsed ..
x x x 1 1 0 1 1 NotUsed ..
x x x 1 1 1 0 o NotUsed ..
x x x 1 1 1 O 1 NotUsed ..
It x x 1 1 1 1 O NotUsed ..
x x x 1 1 1 1 1 NotUsed ..
x =don'tcare
LB " low-order byte
HB -- high-order byte
. A write accesses the modulus register, a read the read butter.
.. A read from an unused location reads invalid data, a write does not tttttttgt
any operation ot NSC8t0A.
TABLE II. Mode Definition Register Bit Assignments
_b_|—A° o
XXXXO’
XXXXUI
.w—AOX.‘
This Material Copyrighted By Its Respective Manufacturer
9.0 Functional Description (Continued)
Any write or read to the port bits contradicting the direction
established by the DDR will not affect the port bits output or
input. However, a write to a port bit, defined as an input, will
modify the output latch and a read to a port bit, defined as
an output, will road this output latch. See Figure 2.
. Data Registers
These registers contain the actual data being transferred
between the CPU and the peripheral. ln Basic vo, data
presented by the peripheral (read cycle) will be latched on
the falling edge of A25. Data presented by the CPU (write
cycle) will be valid after the rising edge 01% (see AC char-
acteristics for exact timing).
During Strobed vo, data presented by the peripheral must
be valid on the rising edge of STE Data received by the
peripheral will be valid on the rising edge of ST_B. Data
latched by the port on the rising edge of wrg will be we
served until the next CPU read or TN signal.
q Bit Set-Ciear Registers
The " features of the RAM-I/O-timer allow modification of
a single bit or several bits of a port with the Bit-Set and Bit-
Ciear commands. The address selected indicates whether a
Bit-Set or Clear will take place. The incoming data on the
address/data bus is latched at the trailing edge of the W
strobe and is treated as a mask. All bits containing " will
cause the indicated operation to be performed on the corre-
sponding port bit. All bits of the mask with os cause the
corresponding port bits to remain unchanged. Three sample
operations are shown in Table Ill using port B as an ex-
ample.
lNTERNAL
DATA BUS WMSET)
WK WMCLRI
OUTPUT DATA
TABLE III. Blt-Set and Clear Examples
Operation Clear Bit Set B4, Ba
Port B Set B? and BO and 81
Address )oo<01101 m01001 m01101
Data 10000000 00000101 0001 101 o
Port Pins
Prior State 00001111 10001111 10001010
Next State 10001111 10001010 10011010
9.3.2 Modes
Two data transfer modes are implemented: Basic vo and
Strobed l/O. Strobed l/O can be further subdivided into
three categories: Strobed input, Strobed Output (active pe-
ripheral bus) and Strobed Output (T Rl-STATE peripheral
bus). The following descriptions detail the functions of these
categories.
q Basic vo
Basic I/O mode uses the FTG and wm CPU bus signals to
latch data at the peripheral bus. This mode is the permanent
mode of operation for ports B and C. Port A is in this mode if
the MDR is set to mode 0. Read and write byte operations
and bit operations can be done in Basic l/O. Timing for
these modes is shown in the AG Characteristics Table and
described with the data register definitions.
When the NSC810A is reset, all registers are cleared to
zero. This results in the basic mode of operation being se-
lected, all port bits are made inputs and the output latch for
each port bit is cleared to zero. The NSC810A, at this point,
can read data from any peripheral port without further set-
up. If outputs are desired, the CPU merely has to program
the appropriate DDR and then send data to the data ports.
WMDDH)
[DATIt DIRECTION)
DATA LITE"
TL/Cf5517-13
FIGURE 2
This Material Copyrighted By Its Respective Manufacturer
VOLSOSN
NSC810A
9.0 Functional Description (Continued)
0 Strobed I/O
Strobed I/O Mode uses the Trg, BF and INTR signals to
latch the data and indicate that new data is available for
transfer. Port A is used for the transfer of data when in any
of the Strobed modes. Port B can still be used for Basic l/O
and the lower 3-bits of port C are now the three handshake
signals for Strobed I/O. Timing for this mode is shown in the
AC Characteristic Tables.
Initializing the NSCB10A for Strobed I/O Mode is done by
loading the data shown in Table IV Into the specified regis-
ter. The registers should be loaded in the order (left to right)
that they appear in Table IV.
TABLE IV. Mode Definition Register Configurations
Port C
Output
DDR DDR
Mode MDR PortA Ponc
Basic IIO xxxxxxx0 Port bit directions are
determined by the bits of
each port's DDR
Strobedlnput xxxxxx01 00000000 xxx011 xxx1xx
Strobed Output xxxxx011 11111111 xxx011 xxxIxx
(Active)
StrobedOutput xx>oo<111 11111111 xxx011 xxx1xx
(T RI-STATE)
0 Strobed Input (Mode 1)
During strobed input operations, an external device can load
data into port A with the grB signal. Data is input to the
Example Mode 1 (Strobed Input):
PAO-? input latches on the leading (negative) edge of m.
causing BF to go high (true). On the trailing (positive) edge
of "tT'rt5 the data is latched and the interrupt signal, lNTR,
becomes valid indicating to the CPU that new data is avail-
able. iNTR becomes valid only if the interrupt is enabled,
that is the output data latch for P02 is set to I.
When the CPU reads port A, address x'00, the trailing edge
of the Ttf strobe causes BF and INTR to become inactive,
indicating that the strobed input cycle has been completed.
q Strobed output-Ache (Mode 2)
During strobed output operations, an external device can
read data from port A using the STE signal. Data is initially
loaded into port A by the GPU writing to l/O address x'oo.
On the trailing edge of W, INTR is set inactive and BF
becomes valid indicating new data is available for the exter-
nal device. When the external device is ready to accept the
data in port A it pulses the SW signal. The rising edge of
trrB- resets BF and activates the INTR signal. INTR be-
comes valid only if the interrupt is enabled, that is the output
latch for PC2 is set to 1. INTR in this mode indicates a
condition that requires CPU intervention (the output ot the
next byte of data).
. Strobed output-crm-STATE (Mode 3)
The Strobed Output TRI-STATE Mode and the Strobed Out-
put active (peripheral) bus mode function in a similar man-
ner with one exception. The exception is that the data sig-
nals on PAO-? assume the high impedance state at all
times except when accessed by the m signal. Strobed
Mode 3 is identical to Strobed Mode 2, except as indicated
above.
Action Taken W BF Results of Action
INITIALIZATION
Reset NSCB10A H L Basic input mode all ports.
Load 01'H into H L Strobed input mode entered; no byte loads to port C
MDR after this step; bit-set and clear commands to IN-TR
and BF no longer work.
Load OO'H into H L Sets data direction register for port A to input;
DDR A data from port A peripheral bus is available
to the CPU if the W signal is used, other
handshake signals aren't initialized, yet.
Load 03'H into H L Sets data direction register of port C; buffer full
DDR C signal works after this step and it is unaffected
by the bit-set and clear registers.
Load 04'H into H L Sets output latch (PC2) to enable WTA; INTF7 will
Port C Bit-Set latch active whenever W goes low; BCTA can be
Register disabled by a bit-clear to PG2.*
OPERATION
Atty pulses low L H Data on peripheral bus is latched into port A;
Wm is cleared by a GPU read of port A or a
bit-clear of Ttri.
CPU reads Port A H L CPU gets data from port A; WTA is cleared;
peripheral is signalled to send next byte via
an inactive BF signal. Repeat last two steps until
EOT at which time CPU sends bit-clear to the
output latch (P62).
. Port C can be read by the CPU at anytime, allowing polled operation instead of interrupt driven operation.
This Material Copyrighted By Its Respective Manufacturer
9.0 Functional Description (Continued)
Example Mode 2 (Strobed Output-active peripheral bus):
Actlon Taken INTFt BF Results of Action
INITIALIZE
Reset NSC810A H L basic input mode all ports.
Load 03'H into H L strobed output mode entered; no byte loads to
MDR port C after this step; bit-set and clear
commands to INTR and BF no longer work.
Load FF'H into H L Sets data direction register for port A to output:
DDR A data from port A is available to the peripheral
if the 19tTy signal is used other handshake
signals aren't initialized, yet.
Load 03'H into H L Sets data direction register of port C; buffer
DDR C full signal works after this step and it is
unaffected by the bit-set and clear registers
Load 04'H into L L Sets output latch (P02) to enable W;
Port C Bit-Set active NT-R indicates that CPU
Register should send data; FNT-R becomes inactive
whenever the CPU loads port A; FCTT1' can
be disabled by a bit-clear to BTN
OPERATION
CPU writes to H H Data on CPU bus is latched into port A;
Port A Ir-Orr-l is set by the CPU write to port A; active
m pulses low L L BF indicates to peripheral that
data is valid; Peripheral gets data from port A;
Wrr:f is reset active; The active TWA' signals the
CPU to send the next byte. Repeat last two
steps until EOT at which time CPU sends
bit-clear to the output latch (P02).
'Port C can be read by the CPU at any time, allowing polled operation instead of interrupt driven operation.
In addition to its timing function, TN enables port A outputs
to active logic levels. This Mode 3 operation allows other
data sources, in addition to the NSC810A, to access the
peripheral bus.
q Handshaklng Signals
In the Strobed mode of operation, the lower 3-bits of port G
transmit/receive the handshake signals (PCO=W,
PC1= BF, PC2r--trtT3),
Fir) (Strobe Mode Interrupt) is an active-low interrupt from
the NSC810A to the CPU. In strobed input mode, the
CPU reads the valid data at port A to clear the inter-
rupt. In strobed output mode. the CPU clears the inter-
rupt by writing data to port A.
The INTR output can be enabled or disabled, thus
giving it the ability to control strobed data transfer. It is
enabled or disabled, respectively, by setting or clear-
ing bit 2 of the port C output data latch (W).
PC2 is always an input during strobed mode of opera-
tion, its output data latch is not needed. Therefore,
during strobed mode of operation it is internally gated
with the interrupt signal to generate the INTR output.
Reset clears this bit to zero, so it must be set to one to
enable the INTR pin for strobed operation.
Once the strobed mode of operation is programmed,
the only way to change the output data latch of PC2 is
by using the Bit-Set and Clear registers. The port G
byte write command will not alter the output data latch
of PC2 during the strobed mode of operation.
TTT? (Strobe) is an active low input from the peripheral de-
vice, signalling a data transfer. The NSC810A latches
data on the rising edge of tYT-Ty if the port bit is an input
and the peripheral should latch data on the rising
edge of W if the port bit is an output.
BF (Buffer Full) is a high active output from the NSC81 0A.
For input port bits, it indicates that new data has been
received from the peripheral. For output port bits, it
indicates that new data is available for the peripheral.
Note: In either input or output mode the BF may be
cleared by rewriting the MDR.
9.4 TiMERS
The N80810A has two timers. These are independently
programmable, 16-bit binary down-counters. Full count is
reached at n + 1, where n is the count loaded into the modu-
lus registers. Timer outputs provide six distinct modes of
operation and allow the CPU to check the present count at
anytime. Each timer has an independent clock input and
output. Start and stop words from the CPU can individually
start and stop the timers in any of the modes. A common
gate signal can start and stop both timers in three of the six
modes. Timer 0 has three possible input clock prescalers
+1, +2 and +64. Timer 1 has two possible input clock
prescalers +1 and +2,
Primary components of one timer are shown in Figure 3.
The timer mode register is a read/write register providing
This Material Copyrighted By Its Respective Manufacturer
VOLBOSN
NSCB10A
9.0 Functional Description (Continued)
the primary characterization of the timer output. The start/
stop logic and Prescaler block divides the clock input by the
INTCLK and can be read without stopping the timers (see
singIe/double precision).
prescale factor, passing the output (INTCLK) to the binary
down-counter. This block also gates the clock input signal
(T IN) with the timer gate signal (T G). The timer block loads
the modulus from the modulus register and uses (INTCLK)
to count to zero. It loads the current count into the read
buffer block where the CPU can access it at anytime. This
timer block also indicates to the output control logic when
the modulus is loaded (or reloaded) and when the count
reaches 0. The output control logic block drives the output
pins according to the timer mode register and the timer
block. The output of the timer block (Figure 3) (terminal
count) is related to the input TIN by:
p[2(m + 1)]
0 Timer Mode Register
The timer mode register determines the operating configu-
ration and the active input and output signal levels. Each
timer has its own timer mode register, allowing independent
operation.
The timer mode register (T MR) may be written or read at
any time; however, to assure accurate timing it is important
to modify the mode only when the timer is stopped (see
Timer Programming). The timer mode is selected from one
of six modes by TMR bits o, 1, and 2 (see Table V). Bits 3
and 4 select the prescale value if the prescaler is to be
used. Bits 5, 6 and 7 select the modulus width (8- or 16-
bits), gate input polarity, and timer output polarity (active-
high or low), respectively. The bit functions of the TMR are
illustrated in Figure 4.
terminal count =
where:
TIN = the inputfrequency
p the programmed prescale
m the modulus
This relationship can be seen directly (T OUT) in Mode 5
(square wave) as it is not masked by the subsequent output
logic.
TMR76543210
mscm VALUE
SlNGLE/DOUBLE PRECISION
w: mm muam
mm aumt POLMH’Y
TL/G/5517-1 5
FIGURE 4. Timer Mode Register
TABLE V. Mode Selection
9.4.1 Heglsters
There are five control registers for each timer. These are
shown in the second group of Table I. They determine all
timer functions and outputs.
q Modulus Registers and Read Buffer Blt 2 1 o - Tlmer Functlon
There are two modulus registers per timer (low byte, high o 0 o - Timer Stopped and Reset
byte). These are write only registers, and the two 8-bit val- 0 O 1 - Event Counter
ues loaded by the CPU are combined into a 16-bit modulus O 1 o - Event Timer (Stopwatch)
for the timer's down counter. O 1 1 - Event Timer (Resetting)
When the CPU reads from the modulus register addresses, 1 0 0 - One Shot
it actually accesses the read buffers. These contain the low 1 o 1 - Square Wave
and high byte of the decremented modulus. This count is 1 1 o - Iulse Generator
constantly updated by the timer block on the falling edge of 1 1 1 - Timer Stopped and Reset
- INTERNAL nus
I ii a I, 5!! a
(man now mum [Low
M none
- asnlsm _ am) am) _ me me
lim -+ (mm
_ munutus amsm nun norm
c,,,,,,, t6
TIMCLttl-+ mmsm Loon:
TBiBATE) - AND "I, TIMER 16
wn...’ msscmn (16)
15mm“.
contact
LOGIC - TOUT
' isms)
co m TLfth6617-14
FIGURE 3. Timer Internal Block Diagram (One of Two Timers)
This Material Copyrighted By Its Respective Manufacturer
9.0 Functional Description (Continued)
- Timer Prescaler
There is a prescale function associated with each timer. It
serves as an additional divisor to lengthen the counts for
each timer circuit. The value of the divisor is fixed and se-
lectable in each TMR, as shown below.
TMRO 4 3 Prescale
O 0 + 1
0 1 :- 2
1 1 + 64
The +64 is not available on timer I; TMRI bit 4 is a "don't
care."
TMR1 4 3 Preacale
x o + 1
x 1 _ 2
The timer prescale divides the input clock (T IN) and pro-
vides the output (INTCLK) to the drive the timer block (Fig-
ure B).
- SIngle/Double Precision
Bit 5 of the TMR determines whether a single or double byte
can be accurately read from the read buffer. This option
does not affect the use of the modulus registers by the timer
block (i.e., the modulus used is always a double byte regard-
less of the precision mode selected).
The read buffer keeps track of the count and is constantly
being updated by the timer block. In order to allow the CPU
to read the read buffer, the NSC810A must discontinue up-
dates to this buffer during the read. The precision bit deter-
mines whether one or two bytes in the read buffer will be
frozen during the read process. In double precision mode,
the NSC810A freezes high and low bytes in the read buffer
for two consecutive read cycles. In the single precision
mode, the NSCB10A freezes the read butter for only one
read cycle. Read accesses should be done as follows.
When the TMR bit 5 is:
o- (double byte) read or write the low byte first, then
the high byte to maintain proper read/write com-
munications.
I- (single byte) In this mode either the high or low byte
of the count can be read at any given instant but
not both bytes consecutively. Always write the low
byte first, then the high byte to load the modulus.
The following example illustrates this point. If the read buffer
had a value of 0200 when the low byte was read and the
down-counter decremented to 01 FF before the high byte
was read, then in the double precision mode the GPU would
have read 00 and 02, respectively. In the single precision
mode the CPU would have read 00 and 01.
NOTE: In the double precision mods, the high byte should be read Immedi-
ately after the low byte, Do not access any other registers or unused
address locations between the reads.
- Gate Input Polarity
In modes 2, 3 and 4, the TG input is the common hardware
control for starting and stopping the timers.
The polarity of the gate input may be selected by the con.
tents of bit 6 of the TMR. If bit 6 equals o, the gate signal will
be active-high or positive edge for mode 4; it bit 6 equals l,
the gate polarity will be active-Iow or negative edge for
mode 4. Modes 2 and 3 are level sensitive. Mode 4 is edge
sensitive.
- Timer Output Polarity
Like the gating function, the polarity of the output signal is
programmable via bit 7 of the TMR, A zero will cause an
active-low output; a one will generate an active-high output.
The output for T1 is multiplexed with port C, bit 5. (Similarly
T1IN is multiplexed with port C. bit 4,) When any timer mode
other than 0 or 7 is speeified for T1, or when mode 2, mode
3, or mode 4 is specified for T0, the three port C pins, bit 3,
bit 4, and bit 5, become TG, TIIN and T1OUT, respectively.
. Start and Stop Registers
This is the software start and stop for the timers. There is
one start and one stop register for each timer. Writing any
data to the start register of a timer starts that timer or trans-
fers start and stop control to TG (in the gated modes 2, 3
and 4). Writing any data to the stop register stops the timer
and removes start and stop control from TG (in the gated
modes 2, 3 and 4). Restarting the timers causes the modu-
lus to be reloaded for all gated timer modes (2, 3 and 4).
During software restarts of the timers (write to the STOP
register and then to the START register) the modulus will be
reloaded only if the internal clock signal (INTCLK) is in the
high level or makes at least one transition to the high level
between the time that the STOP and START registers are
written. If INTCLK doesn't meet one of these criteria then
the modulus will not be reloaded and the timer will continue
to count down trom where it was stopped.'
Since it is difficult, if not impossible, to know the level of
INTCLK in non-gated modes the recommended practice for
restart operation is to reload the modulus after stopping the
timer using the 4 step programming procedure in the Timer
Programming section of this datasheet. In gated modes
INTCLK always stops high.
"NOTE: INTCLK is coupled via the prescaier to TIN and reacts to the TIN
clock input regardless ot whether the timer is started or stopped.
- Start/Stop Tlmlng
Figure 5 shows the relationships between the WA signal
(start register), TIN and INTCLK for both the non-gated and
gated modes. The TG signal is only sampled during the pos-
itive half of the TIN cycle. This means that when the gated
modes are used the internal clock (INTCLK) is never
stopped in the low state. Hence, when TG goes active high
INTCLK is restarted on the next high-to-low transition of
TIN. When TG goes inactive low INTCLK will stop as soon
as TIN is high.
9.4.2 Timer Pins
TIN, TOUT, and TG
Timer 0 has dedicated pins for its clock. TOIN. and its out-
put, TOOUT. Timer 1 must borrow its input and output pins
from port C. This is accomplished by writing to the TMR for
timer I. If mode l, 2, 3, 4, 5 or 6 is specified in TMRI, the
pins from port C (P03, P04 and PCS) are automatically
made available to the timer(s) tor gating (T G), T1IN and
TIOUT, respectively. These pins are also taken from port G
any time timer 0 is in mode 2, 3, 4, so that it has a TG pin. In
order to change pins P03. PC4 and PCS back to their origi-
nal configuration as Basic l/O, the timer mode registers
must be reset by selecting mode 0 or 7.
TG (PCS). the timer gate, is used for hardware control to
start/stop (or trigger) the timers. The timer gate may be
used individually by either timer or simultaneously by both
timers.
For modes 2 and 3, the timer starts on the gate-active tran-
sition assuming the start address was previously written. If
This Material Copyrighted By Its Respective Manufacturer
VOlBOSN
This Material Copyrighted By Its Respective Manufacturer
NSCB10A
mama. u)
9.0 Functional Description (Continued)
TL/Cl5517-16
FIGURE 5. Start/Stop Tlmlng
twsp—WTR‘ set-up lat stopping timer 150 ns.
tGST—TG (gate) set-up for starting timer 100 ns.
thp—TG (gate) set-up for stopping timer 100 ns.
Note: Diagonal lines indicate intewal of invalid data.
For mode 4 (one shot). onry start-timing applies.
tws-p—V—Vfi setup for statting time! 150 ns.
This Material Copyrighted By Its Respective Manufacturer
ONE CYCLE
"m“ L] LI ‘ nnn VT!!—
4 I I t {—‘4 a 2 1 o t a z 1 o 4 a 2
sum mlm §
ma sums A
(mlvs-lm H , ~ . I
TL/C/5517-17
FIGURE 6a. Even! Counter Mode (Mode 1)
"m“- L] Ll'l Ll Ll—l 4-
‘ I ‘r—" 3 Z 1 0 t 3 2 Z 2 (+2 1 0 4
9.0 Functional Description (Continued)
nun BUFFER
(Acnvs-meu)
ourrut
[ACTIVE-LOW L» ‘ i
FIGURE 6b. Accumulative Timer (Mode 2)
TL/C/5517—18
m_Lh Ln Ln * LJLJ gm:
4 ‘ Ir—v‘ 3 Z 1 U 4 3 4 d 4
START flEGISYEfl
READ BUFFER
[lETIVE-HIGH)
OUTPUT g.“
IACI'IVE-LW)
TL/C/5517—19
FIGURE 6c. Restartable Tlmlng
VOlBOSN
NSC810A
9.0 Functional Description (Continued)
TABLE VI. Timer Programming Selection Example
Mode Register Bit Timer Tlmer
(TMR) Out ut Gate Mode Descrlptlon
p Slngle/Double Prescale Timing Port c DDR
Polarity Polarity Precision Value Mode 543210
7 8 ti 4 3 2 1 0 Active Active S ID
L/H L/H
TIMER o
x x x x x 0 0 0 x x x x O x x x x x x
o x 0 0 O o o 1 L x D + 1 1 x x x x x x
1 x 0 1 1 1 1 0 H x D + 64 6 x x x x x x
1 O o 0 1 1 0 O H H D + 2 4 1 o 0 x x x
0 1 1 0 0 0 1 0 L L S + 1 2 1 0 0 x x x
TIMER 1
x x x x x 1 1 1 x x x x 7 x x x x x x
0 x o x 0 O 0 1 L x D + 1 1 1 o 0 x x x
1 0 1 x 1 1 0 1 H H S + 2 5 1 0 0 x x x
0 1 O x 0 0 1 1 L L D -:- 1 3 1 0 0 x x x
the timer gate makes an active transition prior to a write to
the start register’s address, the trailing edge of the WA
strobe starts the timer. However, for mode 4 the timer al-
ways waits for an active gate edge following a write to the
start address before it begins counting.
The DDR for port G must be programmed with the correct
l/O direction for TG, T1IN and T1OUT of timer 1. See Table
VI for programming examples.
9.4.3 Tlmer Modes
The low-order three bits (bits o, 1, 2) of the timer mode
registers (T MR) define the mode of operation for the timers.
Each TMR may be written to, or read from, at any time.
However, to ensure accurate timing, it is important to modify
the mode of the timer only when the timer is stopped. Inputs
of 000 or 111 define a NOP (no operation) mode. In either of
these modes (0 or 7) the timer is stopped, INTCLK is high,
and the output is inactive. Inputs of 001 through 110 will
select one of six distinct timer functions.
In the explanations that follow, assume that the modulus
register for the timer was loaded with the appropriate value
(0004) by writing to the low and high bytes of each timer
modulus register. Assume also, that the prescale is + 1.
q Event Counter (mode 1 TMR blts = 001)
In this non-gated mode the count is decremented for each
clock period (INTCLK) input to the timer block (see Figure
tia). When the count reaches zero, the output goes valid
and remains valid, until the read buffer is read by the CPU or
the timer stop register is written.
At the terminal count (0) the modulus is reloaded into the
timer block and the count continues even when the output is
valid. This mode can be used to cause periodic interrupts to
the CPU.
. Accumulative Timer (mode 2, TMR blts = 010)
In this gated mode, the counter will decrement only when
the gate input is active (see Figure tm J. If the gate becomes
inactive, the counter will hold at its present value and con-
tinue to decrement when the gate again becomes active.
When the count decrements to zero, the output becomes
valid and remains valid until the count is read by the GPU or
the timer is stopped.
At the terminal count the timer is reloaded and the count
continues as long as the gate is active.
This mode can be used to time processor independent
events and to interrupt the CPU when they occur. The pre-
scale and modulus need to be longer than the expected
event duration and the gate should go inactive at the event,
to preserve the read buffer count for the CPU.
q Retttartttttle Timer (mode 3, TMR bits = 011)
In this gated mode, the counter will decrement only when
the gate input is active. If the gate becomes inactive, the
counter will reload the modulus and hold this value until the
gate again becomes active (see Figure 6c). If the timer is
read when the gate is inactive, you will always read the
value the timer has counted down to, not the value the timer
has been reloaded with.
At terminal count the output becomes valid and the timer is
reloaded. The timer will continue to run as normal, the only
difference is the output is valid. The output remains valid
until the count is read by the CPU or the timer stop register
is written.
NOTE: The gate inactive time must be longer than the high time of the
internal clock (lNTCLK) on the chip. Therefore, with + 64 prescele
selected the gate inactive time must be 33 input clocks or greater.
This Material Copyrighted By Its Respective Manufacturer
This Material Copyrighted By Its Respective Manufacturer
ONE CYCLE
4 4 4 4 4 3 2 1 4 3 2 1 D 0 0 U 0
SIAM REGISTER
(lCTIVE-HIGH) 9) RETRIGGEE
(ACTIVE-LOVI)
FIGURE 6d. One Shot (Mode 4)
TL/C/5517—20
9.0 Functional Description (Continued)
m_h *' n- mum muu—
STMV IEBISI'EI
OUTPUI g
(mm LOW)
TL/C/5517—21
FIGURE 6e. Square Wave (Mode 5)
f on: CYCLE
.11 ‘I L] ‘ LI LfifiJ—Ll—Ll J—
4 4 4 3 2 I ll 4 3 Z 1
SIAM REGISI’EI
(acme LOW) ‘” L'
TL/C/5517-22
FIGURE 61‘. Pulse Generator (Mode 6)
VOLSOSN
NSC810A
9.0 Functional Description (Continued)
. One Shot Mode (mode 4, TMR Bits = 100)
In this gated mode, the timer holds the modulus count until
the active gate edge (see Figure 6d). The output immedi-
ately becomes valid and remains valid as the counter decre-
ments. The gating signal may go inactive without affecting
the count. If TG (the gate) becomes inactive and returns
active prior to the terminal count, the modulus will be reload.
ed, retriggering the one shot period. When the timer reach-
es the terminal count, the output becomes inactive (see
NOTE). The gate, in this mode, is edge sensitive; the active
edge is defined by the TMR.
NOTE: The one shot cannot be retrlggered during its last internal count
(lNTCLK) regardless of prescaler selected. Therefore, using the di-
vide by 1 prescaler. it cannot be retriggered during the last clock
TIN), using the divide by 2 prescaler during the last two clocks (T IN)
and using the divide by 64 prescaler during the last 64 clocks (T IN).
0 Square Wave Mode (mode 5, THE bits = 101)
in this non-gated mode, the output will go active as soon as
the timer is started. The counter decrements for each clock
period (INTCLK) and complements its output when zero is
reached (see Figure 69 ). The modulus is then reloaded and
counting continues. Assuming a regular clock input, the out-
put will then be a square wave with a period equal to twice
the prescale value times the value loaded into the modulus
+1 (see equation Timer section intro.). Therefore, varying
the modulus will vary the period of the square wave.
0 Pulse Generator (mode 6, TMR bits = 110)
In this non-gated mode, the counter decrements for each
period of INTCLK (see Figure 6f). When the terminal count
is reached the output becomes valid for y, of the TIN clock
width for a prescale of +1. for one full TIN clock width for a
prescale of + 2 and for 32 TIN clock widths for a prescale of
+64. The modulus is then reloaded and the sequence is
repeated. Varying the prescale and modulus varies the fre-
quency of the pulse.
9.4.4 Timer Programming
The following is the proper sequence to program the timer
and should always be used:
1. Write timer mode register selecting mode 0 or 7. This
stops the timer, resets the prescaler. and sets internal
clock high.
2. Write timer mode register again, this time loading it tor
your requirements.
3. Write the modulus values, low byte first, high byte
second.
4. Start the timers.
The timer read buffer is only updated when the internal tim-
er clock (INTCLK) makes a negathm-going transition. There-
fore, enough input clock cycles (T IN) must occur to cause a
transition of INTCLK given the programmed pre-scaler. Af-
ter the first transition, the new modulus will be loaded into
the read buffer and it can then be read by the CPU.
To guarantee the integrity of the data during a read opera-
tion, updates to the timer read buffer are blocked out. If an
update is blocked out due to a mad, the read buffer will not
be updated until the next active transition of INTCLK. Thus,
it would appear as if a count was skipped between reads.
For example, if the output latches were FF when a block out
(read) occurred, the next update could occur at FD, thereby
giving an appearance that the count FE was skipped. In
actuality the correct number of clocks has occurred for the
read buffer to hold FD.
Writing the modulus value when the timer is running does
not update the timer immediately. The new value written will
get into the timer when the timer reaches its terminal count
and reloads its value. If the timer is stopped and a modulus
is written the new modulus value will get into the timer when
the internal clock is high during the modulus write or on the
next low to high internal clock transition. The next time the
timer reaches its terminal count it will load the new modulus
into the timer. One way to guarantee the new modulus will
get into the timer is to follow steps 1 through 4. Although
this procedure guarantees that the data will get into the tim-
er you will not be able to read it back until you get a nega-
tive-going transition on the internal clock.
Rewriting modulus does not reset the prescaler. The only
way to reset the prescaler is to write the mode register and
have the internal clock signal be high for some period be-
tween the write of the mode register and the start of the
timer. Once again, steps 1 through 4 will reset the prescaler.
This Material Copyrighted By Its Respective Manufacturer
10.0 NSC810A/883 MlL-STD-883 Class B Screening
National Semiconductor offers the NSC810AD and Electrical testing is performed in accordance with
NSCB10AE with full class B screening per MIL-STD-883 for RETS810AX, which tests or guarantees all of the electrical
Military/Aerospace programs requiring high reliability. In ad- performance Characteristics of the NSCB10A data sheet. A
dition, this screening is available for all of the key NSCBOO copy of the current revision of RETSB10AX is available
peripheral devices. upon request. The following table is the MIL-STD-883 flow
as of the date of publication.
Test MIL-STD-883 Method/Conditlon Requirement
Internal Visual 2010 B 100 %
Stabilization Bake 1008 C 24 Hrs. tit + 150°C 100%
Temperature Cycling 1010 C 10 Cycles -65'Cf + 150°C 100%
Constant Acceleration 2001 E 30,000 G's, Y1 Axis 100%
Fine Leak 1014AorB 100%
Gross Leak 1014 C 100%
Burn-ln 1015 160 Hrs. © + 125°C (using 100%
burn-in circuits shown below)
Final Electrical + 25''C DC per RETSB10AX 100%
PDA 5% Max
+ 125°C AC and DC per RETSB10AX 100%
- 55''C AC and DC per RETS810AX 100%
+ 25'C AC per RETS810AX 100%
QA Acceptance 5005 Sample per
Quality Conformance 5056 Method 5005
External Visual 2009 100%
11.0 Burn-In Circuit 12.0 Timing Diagram
5242HR
NStNMOAD/883B (Dual-ln-Llne) Input Clocks
" lla; t " trs
IO 4.5V -
1 " CLOEK 1
2 39 t u I ' "
3 " 4.5V
cum 1 'Gs-- 4 37 CLOCK 2 av
5 35 3 Fs
6 35 adilt
CLOCK 3
7 M av - - - - -
51 a 33 s sa--] --l 1 "
CLOCKS - ' 32
cum t -.. 51 " 30 TLftV5517-24
" " Note P. All resistors t 5%, Ya watt unless otherwise designated. 125''C op-
" 25 crating life circuit.
" " Note 2: E package burn-in circuit 5244HR is functionalry identical to the D
" " package.
" tt Note 3: Ail resistors 2.7 kn unless marked otherwise.
t 20 21 Note 4: All clocks 0V to 4.5V.
Note 5: Device to be cooled down under power after burn-in.
TL/C/5517-23
This Material Copyrighted By Its Respective Manufacturer
VOLBOSN
13.0 Ordering Information
NSC810A
"t'moNi. X X X
IA + = A + Reliability Screening
I883 == MIL-STD-sea Screening (Note I)
I = Industrial Temperature (- MPC to + 65°C)
M = Military Temperature ( - 55‘C to + 125°C)
No Doslgnation = Commercial Temperature (tPC to 70°C)
- 1 = 1 MHz Clock Output
-3= 2.5 MHz Clock Output
- 4 = 4 MHz Clock. Output
D = Ceramic Package
N == Plastic Package
14.0 Reliability Information
Gate Count
Transistor Count
E = Ceramic Leadless Chip Carrier (LCC)
V = Ptastic Leaded Chip Carrier (PCC)
TUC/5517-25
Note t.. Do not specify a temperature option; all parts are scteened to military temperature.
14,000
This Material Copyrighted By Its Respective Manufacturer
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NSC810AV-1l/A - product/nscS10av-1i/a?HQS=T|-nu|l-null-dscatalog-df-pf—nuII-wwe
NSC810AD-1M/883 - product/n30810ad-1m/883?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nulI-wwe
NSC810AN-1I/A - product/nsc810an-1i/a?HQS=T|—nuIl-nu|I-dscataIog-df-pf-null-wwe
NSC810AV-3WA - product/nsc810av—3m/a?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
NSC810AV-4l/883 - product/n30810av-4i/883?HQS=T|-null-nuIl-dscatalog-df-pf-nulI-wwe
NSC810AN-1l/883 - productlnsc810an-1i/883?HQS=T|—nu||-nu|I-dscatalog-df-pf-null-wwe
NSC810AE-1M/A - product/nsc81an—1m/a?HQS=T|-nu|I-nulI-dscatalog-df—pf-nuII-wwe
NSC810AE-3l/883 - product/nsc81an—3i/883?HQS=TI-nu|I-null-dscataIog-df—pf-null-wwe
NSC810AE-3l/A - product/nsc810ae—3i/a?HQS=T|-null-nuIl-dscatalog-df-pf-nu||-wwe
NSC810AV-1I/883 - product/nsc810av-1i/883?HQS=Tl-nulI-nuIl-dscatalog-df-pf-nulI-wwe
NSC810AV-4l/A - product/nsc810av—4i/a?HQS=T|-nu|I-nuII-dscatalog-df—pf—nuII-wwe
NSC810AV-4M/883 - product/nsc810av—4m/883?HQS=T|—nu||—nu|I-dscatalog-df—pf-nulI-wwe
NSC810AV-4WA - product/nscS10av-4m/a?HQS=T|-nu|I-nu|I-dscataIog-df-pf-null-wwe
NSC810AD-3I/A - product/nsc810ad-3i/a?HQS=TI-nu||-nu|I-dscataIog-df-pf-null-wwe
NSC810AV-1M/883 - product/nsc810av—1m/883?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
NSC810AD-3M/883 - product/nsc810ad-3m/883?HQS=Tl—nu|I—nu|I—dscatalog-df-pf-nulI-wwe
NSC810AV-1WA - product/n50810av-1m/a?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
NSC810AV-31/A - product/nsc810av—3i/a?HQS=T|-nu|I-nuII-dscatalog-df—pf—nuII-wwe
NSC810AE-3M/883 - product/nsc810ae-3m/883?HQS=TI-nu|I-null-dscatalog—df—pf—nuII-wwe
NSC810AE-3WA - product/nsc81an—3m/a?HQS=T|—null-nulI-dscataIog-df-pf-null-wwe
NSC810AE-4l/883 - product/nsc81an—4i/883?HQS=T|—nuIl-nu|I-dscatalog-df-pf-nuII-wwe
NSC810AE-4I/A - product/nsc810ae—4i/a?HQS=T|—null-nuIl-dscatalog-df-pf-nuIl-wwe
NSC810AE-4M/883 - product/nsc810ae-4m/883?HQS=TI-nu|I-null-dscatalog—df—pf—nuII-wwe
NSC810AE-4WA - product/nsc81an—4m/a?HQS=T|—null-nulI-dscataIog-df-pf-null-wwe
NSC810AD-3WA - product/nsc810ad-3m/a?HQS=T|-null-nulI-dscatalog-df—pf—nu||-wwe
NSC810AD-4I/883 - product/nsc810ad-4i/883?HQS=TI-nuII-nulI-dscatalog-df-pf-null-wwe
NSC810AN - product/nsc810an?HQS=TI-nu|I-nuII-dscatalog-df—pf-nuII-wwe
NSC810AV-31/883 - product/nsc810av—3i/883?HQS=T|-null-nuIl-dscatalog-df-pf-nulI-wwe
NSC810AN-3WA - product/nsc810an-3m/a?HQS=T|-null-nulI-dscatalog-df—pf—nu||-wwe
NSC810AN-1WA - product/nsc810an-1m/a?HQS=T|-null-nulI-dscatalog-df—pf—nuII-wwe
NSC810AN-3l/883 - product/n50810an-3i/883?HQS=T|-nu||-nu|I-dscataIog-df-pf-null-wwe
NSC810AN-4WA - product/nsc810an-4m/a?HQS=T|-null-nulI-dscatalog-df—pf—nu||-wwe
NSC810AV-3M/883 - product/nsc810av—3m/883?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
NSC810AD-1WA - product/nsc810ad-1m/a?HQS=TI-nuIl-nulI-dscatalog-df-pf-nuII-wwe
NSC810AD-4l/A - product/nsc810ad-4i/a?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
NSC810AD-4M/883 - product/n30810ad-4m/883?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nulI-wwe
NSC810AD-4M/A - product/nsc810ad-4m/a?HQS=T|-null-nulI-dscatalog-df—pf—nuII-wwe
NSC810AE-1l/883 - product/nsc81an—1i/883?HQS=TI-nu|I-null-dscataIog-df—pf-null-wwe
NSC810AE-1l/A - product/nsc810ae—1i/a?HQS=T|-null-nuIl-dscatalog-df-pf-nu||-wwe
NSC810AE-1M/883 - product/nscB10ae—1m/883?HQS=T|-nu||-null-dscatalog-df—pf—nuII-wwe
NSC810AN-3I/A - product/nsc810an-3i/a?HQS=T|—nuIl-nu|I-dscataIog-df-pf-null-wwe
NSC810AN-3M/883 - product/nsc810an-3m/883?HQS=Tl—nu|I—nu|I—dscatalog-df-pf-nulI-wwe
NSC810AD-1l/883 - product/n30810ad-1i/883?HQS=TI-nu||-nu|l-dscataIog-df-pf-null-wwe
NSC810AN-4l/883 - product/nsc810an-4i/883?HQS=TI-nuII-nulI-dscatalog-df-pf-null-wwe
NSC810AN-4I/A - product/nsc810an-4i/a?HQS=T|—nuIl-nu|I-dscataIog-df-pf-null-wwe
NSC810AN-4M/883 - product/nsc810an-4m/883?HQS=Tl—nu|I—nu|I—dscatalog-df-pf-nulI-wwe
NSC810AD-3I/883 - product/nsc810ad-3i/883?HQS=T|—null-nulI-dscataIog-df-pf-null-wwe
NSC810AD-1I/A - product/nsc810ad-1i/a?HQS=T|—nu||-nu|I-dscataIog-df-pf-null-wwe
NSC810AN-1M/883 - productlnsc810an-1m/883?HQS=T|—nuIl-nu|I-dscatalog-df-pf-nulI-wwe
