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NSBMC096VF-33
Burst Memory Controller [Life-time buy]
TL/V/11805
NSBMC096-16/-25/-33
Burst
Memory
Controller
August 1993
NSBMC096-16/-25/-33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controllerisan integrated
circuit which implementsall aspectsof DRAM controlfor
high performance systems using an i960É CA/CF
SuperScalar Embedded Processor.The NSBMC096is func-
tionally equivalenttothe V96BMCTM.
The extremely high instructionrate achievedby these proc-
essors placeextraordinary demandson memory systemde-
signif maximum throughputistobe sustained and costs
minimized.
Static RAM offersa simple solutionfor high speed memory
systems. However, high costandlow density makethisan
expensiveand space consumptive choice.
Dynamic RAMsarean attractive alternative withhigherden-
sityandlow cost. Their drawbacksare, slower access time
and more complex control circuitry requiredto operate
them.
The access time problemis solvedif DRAMsare usedin
page mode.Inthis mode, access times rival thatof static
RAM. The control circuit problemis resolvedby the
NSBMC096.
The function thatthe NSBMC096 performsisto optimally
translatethe burst access protocolofthe i960 CA/CF tothe
page mode access protocol supportedby dynamic RAMs.
The device manages oneor two-way interleaved arrange-
mentsof DRAMs suchthat during burstaccess, datacanbe
read,or written,atthe rateofone wordper system clock
cycle.
The NSBMC096has beendesigned toallow maximum flexi-
bilityinits application.Thefull rangeof processor speedsis
supportedfora wide rangeof DRAM speeds, sizesandor-
ganizations. glue logicis required becausethebus interfaceis cus-
tomizedtothe i960 CA/CF. System integrationis further
enhancedby providinga 24-bit heartbeat timer andabus
watch timer on-chip.
The NSBMC096 ispackagedas a132-pinPQFPwith afoot-
printof only1.3 square inches.It reduces design complexi-
ty, space requirementsandis fully deratedfor loading, tem-
peratureand voltage.
Features Interfaces directlytothe i960CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer/Drivers Supports DRAMs trom 256kBto64MBBit counter/timer Non-interleavedortwo way interleaved operation 5-BitBus Watch Timer Software-configured operational parameters High-Speed/Low Power CMOS technology
Block Diagram
TL/V/11805–1
This document containsinformation concerning aproductthathas beendevelopedby National Semiconductor Corporation/V3 Corporation.Thisinformation
isintendedtohelpin evaluatingthisproduct.NationalSemiconductorCorporation/V3 Corporationreservestheright tochangeandimprovethespecificationsthis productwithout notice.
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
NSBMC096TM andWATCHDOGTMare trademarks ofNationalSemiconductor Corporation.
i960Éisa registeredtrademark ofIntelCorporation.
V96BMCTMisatrademark ofV3Corporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
