NS32FX210V ,Facsimile/Data Modem Analog Front End (AFE)applications. Using advanced Transmit power amplifier drives 300n
switched capacitor techniques, A ..
NS32FX210V ,Facsimile/Data Modem Analog Front End (AFE)Block Diagram
LOOPBACK
IL5 in IL} in In " 0ND Van
FIGURE 1
TL/H/10781-i
TRI-STATE. i ..
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OPA2132P A ,High speed FET-input dual operational amplifierFeatures... 1 8 Application and Implementation...... 118.1 Application Information........ 112 Appl ..
OPA2132PA ,High speed FET-input dual operational amplifierElectrical Characteristics....... 511.3 Related Links.. 166.5 Typical Characteristics. 711.4 Tradem ..
OPA2132PA ,High speed FET-input dual operational amplifierSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareOPA132,OPA2132,OPA41 ..
OPA2132PAG4 ,High Speed FET-Input Operational Amplifiers 8-PDIP Pin Functions OPA2132 and OPA4132 (continued)PINI/O DESCRIPTIONOPA2132 OPA4132NAMENO. NO.+In C – 10 ..
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NS32FX210J-NS32FX210V
Facsimile/Data Modem Analog Front End (AFE)
APR u. we:
National PRELIMINARY
Eil Semiconductor November 1990
N332FX210 Facsimile/Data Modem
Analog Front End (AFE)
General Description Features
The NS32FX210 is a highly integrated A/D and D/A Con- n Transmit and receive PCM channel filters
verters with Filtering device optimized for FAX and data mo- l: p-law companding encoder and decoder
dem analog front end applications. Using advanced a Transmit power amplifier drives 3000
switched capacitor techniques, AFE combines receive u 1.536 MHz serial PCM data
bandpass and transmit Iowpass channel filters with a com- I: Programmable Functions:
panding PCM encoder and decoder. The device employs a - Receive gain: 25.4 dB range, tht dB steps
conventional serial PCM interface capable of being clocked - Transmit gain: 25.4 dB range, 0.1 dB steps
at 1.536 MHz. A number of programmable functions may be - Hybrid balance Cancellation filter
controlled via a serial control port. - 6 interface latches
Channel gains are programmable over a 25.4 dB range in - Analog loopback
each direction, and a programmable: filter is included to en- - Digital loopback
able Hybrid Balancing to be adjusted to suit a wide range of a Direct interface to single secondary winding line
loop impedance conditions. Both transformer and active transformer
Data Access Arrangement (DAA) circuits with real or com-
plex termination impedances can be balanced by this filter, .
with Cancellation in excess of 30 dB being readily achiev- a 80 mW operating power (typ)
able when measured across the passband against standard a 1.5 mW standby power '(WP) . . _
test termination networks. I: TTL and CMOS compatible digital interfaces
a Standard serial control interface
To enable AFE to interface to the DAA circuit, six program-
mable latches are included; each may be configured as ei-
ther an input or an output.
Block Diagram
.._.- ---------------- J ----------..------ -..---
ENCODER
I)latAL
L00 PBACK
ANALOG I 0x
LOOPBACK '
vrxo t MCLK
t t F- MR
---l-irs
" " CONTROL A----.--'
mmnc: LATCHES _ r mm _ co
---i-t,
'--------- ----------------—-n -—-‘
IL5 iu IL3 in In " 0ND Van
FIGURE 1
TL/H/10781-1
TRI~STATED is a rog'stelod Indemwi of mm Selma! thmxxation,
©1990 National Samietmdut;tor Corporation TLIHIIDTM l RHtNB20Mt 10/Ptirttattin U. S. A.
(adv) pua IUOH Baleuv wapow eiea/aliwisoed mzxazssmi
Connection Diagrams
sun- 1 28 "-ot/
wrt)- 2 27 -ve
vane s 26 -rlc
NC-I 4 25 -ILO
ILS- 5 24 -ILI
L2- s 23 -IL4
Feix- 7 22 -ILli
Msszrxm
NC- a 21 -%
Dx- 9 20 -NC
co- 10 19 -q,
tl- 11 18 -NC
CCLK- 12 17 ---13R
tTs- 13 16 -MCLK
ue- 14 15 -iktk
TLIH/10781-7
Order Number N532FX210J
See NS Package Number J28A
4 3 2 1 28 27 26
M 5 -IL1
tL3 ti 1-114
1L2 7 '-tt5
rsx 8 NSSZFXZIO 22 -%
NC 9 21 -tl0
ox 10 20 -rsit
co 11 19 t-NC
13 14 1s
t.-peiltl'h'e.i5,c'f
_l .140
d'oxe-:,'d
TL/H/1078t-2
Order Number NSSZFX210V
See NS Package Number V28A
Pin Descriptions
Description
+ 5V 1 5% power supply.
-5)/ 1- 5% power supply.
Ground. All analog and digital signals are refer-
enced to this pin.
Receive Frame Sync Input. Normally a pulse or
squarewave with an 8 kHz or 9.6 kHz repetition
rate is applied to this input to define the start of the
receive time slot assigned to this device.
Transmit Frame Sync Input. Normally a pulse or
squarewave with an 8 kHz or 9.6 kHz repetition
rate is applied to this input to define the start of the
transmit time slot assigned to this device.
IL5-lL0
Bit clock input used to shift PCM data into and out
of the Dx and Dre pins. BCLK may vary from 64 kHz
to 4.096 MHz in 8 kHz increments, and must be
synchronous with MCLK.
Master clock input used by the switched capacitor
filters and the encoder and decoder sequencing
logic. Must be 1.536 MHz and synchronous with
The Receive analog high-impedance input. Voice
frequency signals present on this input are encod-
ed as a p-law PCM bit stream and shifted out on
the th, pin.
The Transmit analog power amplifier output, capa-
ble of driving load impedances as low as soon
(depending on the peak overtoad ievel required).
PCM data received on the Dx pin is decoded and
appears at this output as voice frequency signals.
This Receive Data TRl-STATE® output remains in
the high impedance state except during the re-
ceive time slot during which the receive PCM data
byte is shifted out on the rising edges of BCLK.
Normally this open-drain output is floating in a high
impedance state. It pulls low when a time-slot is
active on the Dn output.
This transmit data input is inactive except during
the transmit time slot when the transmit POM data
is shifted in on the falling edges of BCLK.
Control Clock Input. This clock shifts serial control
information into or out from CI and CO when the
ug input is low, depending on the current instruc-
tion. CCLK may be asynchronous with the other
system clocks.
Serial contr_o| data is shifted into the AFE via this
pin when CS is low. It can be connected to CO if
required.
Serial control data is read out of AFE via this pin
when a is low and a read has been requested in
Byte 1 of the control instruction. It can be connect-
ed to Cl if required.
Chip Select input. When this pin is low, control in-
formation can be written to or read from AFE via
the CI and co pin.
Each Interface Latch IIO pin may be individually
programmed as an input or an output determined
by the state of the corresponding bit in the Latch
Direction Register (LDR). For pins configured as
inputs, the logic state sensed on each input is
latched into the Interface Latch Register (ILR)
whenever control data is written to the AFE, while
E is low, and the information is shifted out on the
CO pin. When configured as outputs, control data
written into the ILR appears at the corresponding
IL pins.
This logic input must be pulled low for normal oper-
ation of the AFE. When pulled momentarily high (at
least 1 ps), all programmable registers in the de-
vice are reset to the states specified under "Pow-
er-On Initialization".
No Connection. Do not connect to this pin. Do not
route traces through this pin.
Functional Description
.POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry initializ-
es the AFE and puts it into the power-down state. The gain
control registers for the transmit and receive gain sections
are programmed to OFF (00000000), the hybrid balance cir-
cuit is turned off and the power amp is disabled. The Latch
Direction Register (LDR) is pre-set with all IL pins pro-
grammed as inputs, placing the DAA interface pins in a high
impedance state. Other initial states in the Control Register
are indicated in Section 2.0.
A reset to these same initial conditions may also be forced
by driving the MR pin momentarily high. This may be done
either when powered-up or down. For normal operation this
pin must be pulled low. It not used, MH should be hard-
wired to ground.
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the "P"
bit set to "I " as indicated in Table l. It is recommended that
the chip be powered down before writing any additional in-
structions. in the power-down state, all non-essential circuit-
ry is de-activated and the DR output is in the high imped-
ance TRl-STATE condition.
The coefficients stored in the Hybrid Balance circuit and the
Gain Control registers, the data in the LDR and ILR, and all
control bits remain unchanged in the power-down state un-
less changed by writing new data via the serial control port,
which remains active. The outputs of the Intertace Latches
also remain active, maintainng the ability to monitor and
control the DAA.
RECEIVE FILTER AND ENCODER
The receive section input, l/FRI, is a high impedance sum-
ming input which is used as the differencing point tor the
internal hybrid balance cancellation signal. No external
components are necessary to set the gain. Following this
circuit is a programmable gain amplifier which is controlled
by the contents of the Receive Gain Register (see Program-
mable Functions section). An active pre-filter then precedes
the 3rd order high-pass and 5th order Iow-pass switched
capacitor filters. The A/D converter has a compressing
characteristic according to the standard p.255 coding law. A
precision on-chip voltage reference ensures accurate and
highly stable transmission levels. Any offset voltage arising
in the gain-set amplifier, the filters or the comparator is can-
celed by an internal auto-zero circuit.
Each encode cycle begins immediately following the Re-
ceive time-slot. The total signal delay referenced to the start
of the time-slot is approximately 165 its (due to the Receive
Filter) plus 125 its (due to encoding delay), which totals
290 p.s. Data is shifted out on Da during the time slot on
eight rising edges ot BCLK.
DECODER AND TRANSMIT FILTER
PCM data is shifted into the Decoder's Transmit PCM Reg-
ister via the Dx pin during the time-slot on the 8 falling edg-
es of BCLK. The Decoder consists of an expanding DAC
with p255 law decoding characteristic. Following the De-
coder is a 5th order Iow-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz or 9.6 kHz sample
and hold. A programmable gain amplifier, which must be set
by writing to the Transmit Gain Register, is inctuded, and
finally a Power Amplifier capable of driving a 3000 load to
i 3.5V, a 6000 load to +_3.8V or a 15 kn load to t 40V at
peak overload.
A decode cycle begins immediately after the transmit time-
slot, and 10 ps later the Decoder DAC output is updated.
The total signal delay is 10 MS plus 120 ps (iilter delay) plus
62.5 p.s (V, frame) which gives approximately 190 p5.
PCM INTERFACE
The FSn and FSx frame sync inputs determine the begin-
ning of the 8-bit receive and transmit time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW.
Two different relationships may be established between the
frame sync inputs and the actual time-stots on the PCM
busses by setting bit 3 in the Control Register (see Table Il).
ln Non-delayed Data Timing mode, time-slots begin nomi-
nally coincident with the rising edge of the appropriate FS
input. The alternative is to use Delayed Data Timing mode in
which each FS input must be high at least a half-cycle of
BCLK earlier than the time-slot.
Receive and Transmit frames and time-slots may be
skewed from each other by any number of BCLK cycles.
During each Receive time-slot, the Dre output shifts data out
from the PCM register on the rising edges of BCLK. TSP.
also pulls low for the first 7% bit times of the time-slot.
Serial PCM data is shifted into the Dx input during each
Transmit time-slot on the falling edges of BCLK.
Functional Description (Continued)
SERIAL CONTROL PORT
Control information and data are written into or read-back
from the AFE via the serial control port consisting of the
control clock CCLK, the serial data input, Cl, and output,
co, and the Chip Select input, cs. All control instructions
require 2 bytes, as listed in Table l, with the exception of a
single byte power-up/down command. The byte 1 bits are
used as follows: bit 7 specifies power up or power down;
bits 6, 5, 4, and 3 specify the register address; bit 2 specifies
whether the instruction is read or write; bit 1 specifies a one
or two byte instruction; and bit 0 is not used.
To shift control data into the AFE, CCLK must be pulsed 8
times while cg is low. Data on the Cl input is shifted into the
serial input register on the falling edge of each CCLK pulse.
After all data is shifted in, the contents of the input shift
register are decoded, and may indicate that a 2nd byte of
control data will follow. This second byte may either be de-
fined by a second byte-wide t5g pulse or may follow the first
contiguously, i.e., it is not mandatory for cs to return high
between the first and second control bytes. At the end of
CCLK8 in the 2nd control byte the data is loaded into the
appropriate programmable register. c-s may remain low
continuously when programming successive registers, if de-
sired. However, cg should be set high when no data trans-
fers are in progress.
To readback Interface Latch data or status information from
the AFE, the first byte of the appropriate instruction is
strobed in during the first cs pulse, as defined in Table l. E
must then be taken low for a further 8 CCLK cycles, during
which the data is shifted onto the CO pin on the rising edges
of CCLK. When a is high the CO pin is in the high-imped-
ance TRI-STATE, enabling the co pins of many devices to
be bussed together.
Programmable Functions
1.0 POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control
instuctions listed in Table I into the AFE with the "P" bit set
to "0" for power-up or "I'' for power-down. Normally it is
recommended that all programmable functions be initially
programmed while the device is powered down. Power state
control can then be included with the last programming in..
struction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the de-
vice is powered-up or down by setting the "P" bit as indicat-
ed. When the power-up or down control is entered as a
single byte instruction, bit one (1) must be reset to a 0.
When a power-up command is given, all de-activated cir-
cuits are activated, but the TRI-STATE PGM output, DR, will
remain in the high impedance state until the second FSR
pulse after power-up.
2.0 CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction for the Con-
trol Register is as shown in Table I. The second byte has the
bit functions shown in Table il.
TABLE I. Programmable Register Instructions
Byte 1 (Note 1) Byte 2 (Note I)
Function 7 6 s 4 3 2 1 o 7 s 5 4 a 2 1 o
Single Byte Power-Up/Down P X X X X X 0 X None
Write Control Register P 0 0 0 0 O 1 X See Table II
Read-Back Control Register P 0 0 0 0 1 1 X See Table "
Write to Interface Latch Register P 0 O 0 1 0 1 X See Table V
Read Interface Latch Regiser P 0 0 0 1 1 1 X See Table V
Write Latch Direction Register P 0 0 1 0 0 1 X See Table IV
Read Latch Direction Register P 0 0 1 0 1 1 X See Table IV
Write Transmit Gain Register P 0 1 0 0 0 1 X See Table VIII
Read Transmit Gain Register P O 1 0 0 1 1 X See Table Vlll
Write Receive Gain Register P 0 0 1 0 1 X See Table VII
Read Receive Gain Register P 0 0 1 1 1 X See Table VII
Write Transmit PCM Enable/Disable P 1 0 0 1 0 1 X (Note 4)
Read Transmit PCM Enable/Disable P 1 0 0 1 1 1 X (Note 4)
Write Receive PCM Enable/Disable P 1 0 1 0 0 1 X (Note 4)
Read Receive PCM Enable/Disable P 1 0 1 0 1 1 X (Note 4)
Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the Cl or CO pin. X = don't care.
Note 2: "P" is the power-up/down control bit, see "Power-Up/Down Control" section. ("0" = Power Up, "I" = Power Down)
Note & Three additional registers are provided for the Hybrid Balance Fitter, see Section 8.0. Other register address codes are invalid and should not be used.
Note 4: Enable code = 1000 0000, Disable Code ' 0000 0000
Programmable Functions (Continued)
TABLE II. Control Register Byte 2 Functions
Bit Number
Function
(Note 1)
Delayed Data Timing
Non-Delayed Data Timing'
Normal Operation'
Digital Loopback
Analog Loopback
Power Amp Enabled in PDN
Power Amp Disabled in PDN'
' = State at powei-on initialization (Bits 7, 6, 5, 4 = l, 0, o, 0).
Note 1: Bits 7, 6, 5, 4 must always be programmed to O, 1, O. o.
2.1 Analog Loopback
Analog Loopback mode is entered by setting the "AL" and
"DL" bits in the Control Register as shown in Table II. In the
analog loopback mode, the Receive input VFRI is isolated
from the input pin and internally connected to the VFxO
output, forming a loop from the Transmit PCM Register back
to the Receive PCM Register. The VFxO pin remains active,
and the programmed settings of the Receive and Transmit
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Hybrid balance must be disabled tor meaningful analog
loopback function.
2.2 Digital Loopback
Digital Loopback mode is entered by setting the "AL" and
"DL" bits in the Control Register as shown in Table II. This
mode provides another stage of path verification by en-
abling data written into the Transmit PCM Register to be
read back from that register in the Receive time-slot at DR.
In digital loopback, the decoder will remain functional and
output a signal at VFxO. If this is undesirable, the transmit
output can be turned off by programming the transmit gain
register to all zeros.
TABLE III. Coding Law Convention
p.255 Law
MSB LSB
VIN = 'Full Scale 1 0 O 0 0 0 0 o
1 1 1 1 1 1 1 1
" - 0V ( o 1 1 1 1 1 1 1
Ihr: = -Full Scale o 0 O 0 0 0 0 0
Note P. The MSB is always the first PCM bit shifted in or out of the AFE.
3.0 INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each 1L pin may be individually pro-
grammed as a logic input or output by writing the appropri-
ate instruction to the LDR, see Tables I and IV. For minimum
power dissipation, unconnected latch pins should be pro-
grammed as outputs.
Bits Ls-Lo must be set by writing the specified instruction to
the LDR with the L bits in the second byte set as follows:
TABLE IV. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
7 6 5 4 3 2
Lo L1 L2 La L4 Ls X
Ln Blt IL Direction
0 Input
1 Output
X == Don't Care
4.0 INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (lLFl) as shown in
Tables I and V. Latches configured as inputs will sense the
state applied by an external source, such as the ring detect
output of a DAA. All bits of the ILR, i.e.. sensed inputs and
the programmed state of outputs, can be read back in the
2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed
first, followed immediately by the Latch Direction Register.
TABLE V. Interface Latch Data Bit Order
Bit Number
T 6 5 4 3 2 1 o
Do D1 Da 03 D4 Ds X
Programmable Functions (Continued)
5.0 RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB steps by
writing to the Receive Gain Register as defined in Tables I
and VI. This corresponds to a range of 0 dBmO levels at
VFRI between 1.619 Vrms and 0.087 Vrms (equivalent to
+6.4 dBm to -19.0 dBm in 6000).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBmo level in Vrms, take the nearest
integer to the decimal number given by:
200 M log1o(V/0.08595)
and convert to the binary equivalent. Some examples are
given in Table VI.
TABLE VI. Byte 2 of Receive Gain Instruction
Bit Number o dBmO Test Level (Vrms)
7 6 5 4 3 2 1 0 at VFRI
0 0 0 0 0 0 0 0 No Output
0 0 0 0 0 0 0 1 0.087
0 0 o 0 0 0 1 0 0.088
1 1 1 1 1 1 1 0 1.600
1 1 1 1 1 1 1 1 1.619
6.0 TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Tables I
and VII. Note the following restrictions on output drive capa-
bility:
a. 0 dBmO levels s; 1.96 Vrms at VFxO may be driven into
a load of 2 15 kn to GND; transmit gain set to 0 dB
b. O dBmO levels g 1.85 Vrms at VFxO may be driven into
a load of 2 6000 to GND; transmit gain set to -0.5 dB
c. 0 dBmO levels 3 1.71 Vrms at VFxO may be driven into
a load of it 3000 to GND; transmit gain set to _ 1.2 as
To calculate the binary code for byte 2 of this instruction for
any desired output 0 dBmO level in I/rms, take the nearest
integer to the decimal number given by:
200 x 10910 (V/0.1043)
and convert to the binary equivalent. Some examples are
given in Table VII.
TABLE VII. Byte 2 of Transmit Instruction
Bit Number 0 dBmO Test Level (Vms)
7 6 5 4 3 2 1 0 at VFxO
O 0 0 0 0 0 0 0 No Output (Low Z to GND)
0 0 0 0 0 0 0 1 0.105
o 0 0 0 0 0 1 0 0.107
1 1 1 1 1 1 1 0 1.941
1 1 1 1 1 1 1 1 1.964
7.0 PCM INTERFACE ENABLEIDISABLE
When power is first applied to the device pins, the PCM
interface is disabled. To enable the PCM interface, both
transmit and receive PCM Enable/Disable registers must be
written with the enable code (1000 0000). See Table i.
8.0 HYBRID BALANCE FILTER
The Hybrid Balance Filter on the AFE is a programmable
filter consisting of a second-order section, Hybal1, followed
by a first-order section, Hybal2, and a programmable attenu-
ator. Either of the filter sections can be bypassed if only one
is required to achieve good cancellation. A selectable 180
degree inverting stage is included to compensate for inter-
face circuits which also invert the receive input relative to
the transmit output signal. The 2nd order section is intended
mainly to balance low frequency signals across a transform-
er DAA, and the first order section to balance midrange to
higher audio frequency signals.
As a 2nd order section, Hybalt has a pair of low frequency
zeroes and a pair of complex conjugate poles. When contig-
uring Hyball, matching the phase of the hybrid at low to
mid-band frequencies is most critical. Once the echo path is
correctly balanced in phase, the magnitude of the cancella-
tion signal can be corrected by the programmable attenua-
The 2nd order mode of Hybalt is most suitable for batanc-
ing interfaces with transformers having high inductance of
1.5 Henries or more. An alternative configuration for smaller
transformers is available by converting Hybal1 to a simple
tirst-order section with a single real low-frequency pole and
zero. In this mode, the pole/zero frequency may be pro-
grammed.
Many line interfaces can be adequately balanced by use of
the Hybalt section only, in which case the Hybaiz filter
should be de-selected to bypass it.
Hybal2, the higher frequency first-order section, is provided
for balancing an electronic DAA and is also helpful with a
transformer DAA in providing additional phase correction for
mid and high-band frequencies, typically 1 kHz to 3.4 kHz.
Such a correction is particularly useful if the test balance
impedance includes a capacitor of 100 nF or less. Indepen-
dent placement of the pole and zero location is provided.
Figure 2 shows a simplified diagram of the locai echo path
for a typical application with a transformer interface. The
magnitude and phase of the local echo signal, measured at
VFRI are a function of the termination impedance Zr, the
line transformer and the impedance of the 2W loop, ZL. It
the impedance reflected back into the transformer primary
is expressed as h' then the echo path transfer function
from VFxO to VFRI is:
H(w) = Zi.‘/(ZT + ZL') (1)
8.1 Programming the Filter
When power is first applied, the Hybrid Balance filter is dis-
abled. Before the hybrid balance filter can be programmed it
is necessary to design the transformer and termination im-
pedance in order to meet system 2W input return loss speci-
fieations, which are normally measured against a fixed test
impedance (600n or 9000 in most countries). Only then
can the echo path be modeled and the hybrid balance filter
programmed. Hybrid balancing is also measured against a
fixed test impedance. This test impedance is ZL in Figure 2.
The echo signal and the degree of transhybrid loss obtained
by the programmable filter must be measured from the PCM
digital input, Dx, to the PCM digital output, On. either by
digital test signal analysis or by conversion back to analog
by another AFE device.
Programmable Functions (Continued)
Three registers must be programmed in the AFE to fully
configure the Hybrid Balance Filter as follows:
Register 1: select/de-select Hybrid Balance Filter;
invert/non-invert cancellation signal;
select/de-select Hybal2 filter section;
attenuator setting. -
Register 2: select/de-select Hybalt filter;
set Hybal1 to 2nd order or Ist order;
pole and zero frequency selection.
Register 3: program pole frequency in Hybal2 filter;
program zero frequency in Hybal2 filter.
Standard filter design techniques may be used to model the
echo path (see Equation I) and design a matching hybrid
balance Mer configuration. Alternatively, the frequency re-
sponse of the echo path can be measured and the hybrid
balance fitter designed to replicate it.
"tttr----------------
' . TO Rx
I GAIN BLOCK
' o--'"''; 0A
2 ' I HYBAL 2 HYBAL 1
2L Cl - L I Hl-P/Z 2nd ORDER H
I t FILTER FILTER
I ATTENUATOR
RING It I
vr o '
X l /l A FROM TX
u 'sl , GAIN BLOCK
TL/H/10781-3
FIGURE 2. Simplified Diagram of Hybrid Balance Circuit
Applications Information
Figure 3 shows a typical application of the AFE together
with a transtormer-based DAA. One of the IL latches is con-
figured as an output to control the relay driver on the DAA
while another is an input for the ring detect signal.
POWER SUPPLIES
While the pins of the AFE device are well protected against
electrical misuse, it is recommended that the standard
CMOS practice of applying GND to the device before any
other connections are made should always be followed. In
applications where the printed circuit card may be plugged
into a hot socket with power and clocks already present,
extra long pins on the connector should be used for ground
and V33. In addition, a Schottky diode should be connected
between V33 and ground.
To minimize noise sources. all ground connections to each
device should meet at a common point as close as possible
to the device GND pin in order to prevent the interaction of
ground return currents flowing through a common bus im-
pedance. Power supply decoupling capacitors of 0.1 pF
should be connected from this common device ground point
to Voc and V53 as close to the device pins as possible. Vcc
and V35 should also be decoupled with Low Effective Se-
ries Resistance Capacitors of at least 10 pF located near
the card edge connector.
Rmatch
= CCLK tt
-----. (S
SYSTEM 6000
ASIC MCLK/BCLK
-CCC: rs“
RMG DErECT
L n ILO =
"ts APE
NS32FX210
SYSTEM SYSTEM
BUS MDAORY
NS32FX16
TLm/1071M-4
FIGURE 3. Stand-Alone FAX Application
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
Storage Temperature Range
please contact the National Semiconductor Sales VBBto GND
Office/Distributors for availability and ttpeemeatlons. Cu r r e nt at VFxO
Vcc to GND 7V Current at any Digital Output
Voltage at VFRI Vcc + 0.5V to V33 - 0.5V
Voltage at any Digital Input
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V i 5%, VBB = - 5V i 5%; TA = trc
to + 70°C by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correlation with other
production tests and/ or product design and characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V,
VBB = -5V, TA = 25°C.
VCC+0.5VtoGND-0.5V
-65''C to +150°C
Lead Temperature (Soldering, 10 sec.)
i100 mA
t 50 mA
30ty'C
Symbol Parameter Conditions L Min Typ Max Units
DIGITAL INTERFACES
" Input Low Voltage All Digital Inputs (DC Meas.)* 0.7 V
VIH Input High Voltage All Digital Inputs (DC Meas.)' 2.0 V
VOL Output Low Voltage DR. T% and CO, t = 3.2 mA, o a V
All Other DigitalOutputs, IL = 1 mA .
VoH Output High Voltage DR and CO, IL -=, - 3.2 mA,
All Other Digital Outputs 2.4 V
(exceptTSR), IL = - 1 mA
All Digital Outputs, IL = - 100 pA Vcc -0.5 V
liL Input Low Current Any Digital Input, GND < VIN < " - 1 0 10 pA
IIH Input High Current Any Digital Input Except MR,
- 1 0 1 0 A
VIH < VIN < Vcc "
Mnomy ~10 100 0A
I02 Output Current in High DR and CO
Impedance State (T RI-STATE) lL5-lL0 When Selected as Inputs - 1 O 10 WA
GND < VOUT < Vcc
ANALOG INTERFACES
lvpm Input Current, VFRI -3.3V < VFRI < 3.3V - 10.0 10.0 WA
RVFR. Input Resistance -3.3V < 1/Fnl < 3.3V 390 620 kn
VOSR Input Offset Voltage Receive Gain = 0 dB 200 mV
Applied at VFnl Receive Gain = 25.4 dB 10 mV
RLVFXO Load Resistance Transmit Gain = 0 dB 15k
Transmit Gain = -0.5 dB 500 n
Transmit Gain = --t.2 dB aoo
CLVFxo Load Capacitance RLVFXO 2 3000 2 0 o F
CLVFXO from VFxO to GND p
ROVFXO Output Resistance Steady Zero PCM Code
. 1.0 3.0 n
Applied to Dx
VOSX Output Offset Voltage Alternating i Zero PCM Code Applied to
at Vpxo Ox, 0 dB Transmit Gain 0 200 mV
‘Note: See definitions and timing conventions section.
Electrical Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V 1 5%, V95 = -5V 15%; TA =0°C
to +70''C by correlation with 100% electrical testing at TA = 25"C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = + 5V,
VBB = --5V, TA = 25''C.
Symbol L Parameter Conditions 1 Min Typ Max Units
POWER DISSIPATION
loco Power Down Current CCLK, CI, CO, = 0.4V, C19 == 2.4V
(,'lttrt"leltl1Cd'r1,'1,tttl'tts OA o.e mA
Active, Power Amp Disabled
1330 Power Down Current As Above - 0.1 - 0.3 mA
1001 Power Up Current CCLK, Cl, co = 0.41f, R = 2.4V
2'li'e,1'2'2h,rstrt"p 8.0 tq.O m
as Outputs with No Load
1331 Power Up Current As Above - 8.0 - 1 1.0 mA
icce Power Down Current Power Amp Enabled 2.0 a.o mA
IBB2 Power Down Current Power Amp Enabled - 2.0 v a.o mA
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V t 5%; VBB = -5V i 5%; TA = 0°C
to +70''C by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correiation with other
production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V,
VBB == --5V, TA = 25''C.
All timing parameters are measured at VOH = 2.0V and VOL = 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol Parameter Conditions Min Typ i Max Units
MASTER CLOCK TIMING
(MCLK Frequency of MCLK 1536 kHz
(WMH Period of MCLK High Measured trom VIH to VIH BO ns
tWML Period of MCLK Low Measured from " to " BO ns
tnM Rise Time of MCLK Measured from W. to Vet 30 ns
tFM Fall Time of MCLK Measured from VIH to " 30 ns
tpr Period of an or st Low Measured from VIL to VI. 1 MCLK Period
POM INTERFACE TIMING
tBCLK FrequencyofBCLK gais1ag'irr1','12'/,1zr,t,tLn,s '" BO$M' kHz
tng Period of BCLK High Measured from Ihr, to ViH so ns
tng Period of BCLK Low Measured from " to tht. BO ns
tag Rise Time of BCLK Measured from VIL to VIH 30 ns
tFB Fall Time of BCLK Measured from Ihr, to VL 30 ns
Timing Specifications (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = f 5V i 5%; V33 = -5V 1 5%; TA = ty'G
to +70°C by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V,
VBB = -5V, TA = 25''C.
All timing parameters are measured at VOH = 2.0V and VOL = 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol Parameter Conditions Min Typ Max Units
PCM INTERFACE TIMING (Continued)
IHBF Hold Time, BCLK Low
to FSx/n High or Low ao ns
tSFB Setup Time, FSR/x
High to BCLK Low so ns
tDBD Delay Time, BCLK Load = 100 pF Plus so ns
High to Data Valid 2 LSTTL Loads
tDBZ Delay Time, BCLK Low to Dre
Disabled if FSR Low, FSR Low
to DR Disabled if 8th BCLK 1 s BO ns
Low, or BCLK High to DR
Disabled if FSR High
tDBT Delay Time, BCLK High to t7m Load = 100 pF Plus
Low if FSR High, or FSR High 2 LSTTL Loads 60 ns
to t% Low if BCLK High
tZBT TRl-STATE Time, BCLK Low
to T-sr, High if an Low, FSR
Low to T_SR High if 8th BCLK 15 so as
Low, or BCLK High to TtTn
High if FSR High
tDFD Delay Time, stm Load = 100 pF Plus 2 LSTTL Loads,
High to Data Valid Applies it FSx/R Rises Later than 80 ns
BCLK Rising Edge in Non-Delayed
Data Mode Only
tsas Setup Time, Dx
Valid to BCLK Low att ns
tHBD Hold Time, BCLK
Low to Dx Invalid 20 ns
SERIAL CONTROL PORT TIMING
fCCLK Frequency of CCLK 2049 kHz
tWCH Period of CCLK High Measured from VIH to V.” 1 60 ns
thL Period of CCLK Low Measured from " to " 1 60 ns
tRC Rise Time of CCLK Measured from Vit. to VIH 50 ns
tFC Fall Time of CCLK Measured from VIH to VIL 50 ns
trays He1Time, CCLK Low CCLK! , tt ns
to CS Low
tHSC Hold Time, CCLK CCLKB
Low to t5g High , oo ns
tssc Setup Time, C_S
Transition to CCLK Low BO ns
Timing Specifications (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed tor Vcc = + 5V ic 5%; V38 = - 5V i 5%; TA = 0°C
to +7ty'C by correlation with 100% electrical testing at TA = 25''C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at Vcc 2 + 5V.
VBB = -5V, TA = 25°C.
All timing parameters are measured at VOH = 2.0V and VOL = 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol 1 Parameter Conditions Min Typ Max Units
SERIAL CONTROL PORT TIMING (Continued)
tssco Setup Time, c-s 80 ns
Transition to CCLK High
tsoc Setup Time, Cl
Data In to CCLK Low so ns
tHCD Hold Time, CCLK
Low to Cl Invalid 50 ns
tDCD Delay Time, CCLK High Load = 100 pF Plus BO ns
to CO Data Out Valid 2 LSTTL Loads
tDSD Delay Time, a Low Applies Only if Separate BO ns
to GO Valid c-s used for Byte 2
tDDZ Delay Time, E or 9th Applies to Earlier of trs High
CCLK High to CO or 9th CCLK High 15 80 ns
High Impedance
INTERFACE LATCH TIMING
tSLC Setup Time, IL to Interface Latch Inputs Only 1 oo ns
CCLK 8 of Byte 1
tHCL Hold Time, IL Valid from 50 ns
8th CCLK Low (Byte 1)
tom Delay Time CCLK 8 Interface Latch Outputs Only 200 ns
of Byte 2 to IL CL = 50 pF
MASTER RESET PIN
IWMR Duration of Master 1 s
Reset High p.
Timing Diagrams
epow fiulu-ILL Bled P35390410}! 'V HHHSH
XBXLX9X9X' t zXIX *0
6—18L0l/H/11
8 J I. X 9 )rs X r X g X z X 1 )-l ”a
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1am, . L l JSH‘J *EJS‘
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mm1 8.1} 33;»1aH, |
\_/LI\_§ \/\I\r*f"\l\l’m~
HHM‘ "J‘—h~— NU‘
MCLKJ \_I ETT£\ I \ -:wthw
”8“ *RB ‘ra ‘wan
BCLKJMfir—I4\ I5\ ISL 7 31r_/9\-
DR 1X2X3L4XsXsX7fai-—
- tom i
‘sra tmar
0x X'2f3X4X5X6X7X8X
FIGURE 5. Delayed Data Tlmlng Mode
TL/H/10781-5
Timing Diagrams (Continued)
Timing Diagrams (Continued)
r0...—
com 1 2 3 5.
?S tm- arr: 1 ...
‘soc 'Hsc ‘ssoo ‘ .
CI mm: m: ”0° '
amzwu:u\\\X7X6 5 4X3X2X1X0X\\\\ 7X6X5X4X3X2X1X0X\\\
INPUT T0 01 .4 p.
emz 1059.4 ,1 ram l‘ofiz’
““3333: —£’X 6X5X4X3X2X‘Lo)-
' ‘HCL '
‘SLc ' L— t0“
ILS-ILO
INPUTS ONLY OUTPUTS ONLY
TL/H/10781-6
FIGURE 6. Control Port Tlmlng
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V 1 5%, VBB = -51/ t5%; FSR and
FSX = 8 kHz or 9.6 kHz; TA == ty'C to + 70°C by correlation with 100% electrical testing at TA = 25''C. t = 1015.625 Hz, VFRI
= 0 dBmO, Dx = 0 dBmo PCM code. Transmit and receive gains programmed for maximum 0 dBmO test levels (0 dB gain),
hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and
characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V, V33 = -5V, TA = 25°C.
Symbol Parameter Conditions l Min Typ J Max Units
AMPLITUDE RESPONSE
Absolute Levels The Maximum 0 dBmO Levels are:
VFRI 1 .619 Vrms
VFXO (15 kit Load) 1.964 Vrms
The Minimum 0 dBmO Levels are:
VFnt 87.0 mVrms
VFXO (Any Load 2 30011) 105.0 mVrms
Overload Level is 3.17 dBmO
GRA Receive Gain Receive Gain Programmed for Maximum
Absolute Accuracy 0 dBmO Test Level. (All 1's in gain register)
Measure Deviation of Digital Code from - O. 1 s o. 1 s dB
Ideal 0 dBmO PCM Code at DR
TA = 25°C
GRAG Receive Gain Measure Receive Gain Over the Range
Variation with from Maximum to Minimum
Programmed Gain Calculate the Deviation from the _ 0.1 0.1 dB
Programmed Gain Relative to GRA,
i.e., GRAG = Gactual _ Gprog - GRA
TA = 25°C, Vcc = -5V, V33 = ASV
GRAF Receive Gain Relative to 1015.625 Hz, (Note 4)
Variation with Minimum Gain < GR < Maximum Gain
Frequency f = 60 Hz -26 dB
f-- 200 Hz -t.8 -0.1 dB
1: 300 Hzto 3000 Hz --0.15 0.15 dB
f = 3400 Hz -0.7 0.0 dB
f = 4000 Hz -14 dB
f 2 4600 Hz. Measure Response -32 dB
at Alias Frequency from 0 kHz to 4 kHz
GR = OdB, VFR = 1.619Vrms
Relative to 1015.625 Hz
f = 62.5 Hz -2BAt dB
f = 203.125 Hz _ 1.7 -o., dB
f = 343.75 Hz -0AS 0.15 dB
f-- 515.625 Hz -0AS 0.15 dB
f = 2140.625 Hz -o." 0.15 dB
f---- 3156.25 Hz -ttMS 0.15 dB
= 3406.250 Hz -0.Tq 0.0 dB
f = 3984.375 Hz - 13.5 dB
Relative to 1062.5 Hz (Note 4)
f = 5250 Hz, Measure 2750 Hz - " dB
f = 11750 Hz, Measure 3750 Hz -a2 dB
f 5tTC 49750 Hz, Measure 1750 Hz -a2 dB
GRAT Receive Gain Measured Relative to GRA, VCC = 5V,
Variation with V33 = -5V, --0.1 0.1 dB
Temperature Minimum Gain < GR < Maximum Gain
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V , 5%, V89 = - 5V l 5%; FSR and
FSX = 8 kHz or 9.6 kHz; TA = 0°C to + 70''C by correlation with 100% electrical testing at TA = 25°C. f = 1015.625 Hz, VFRI
= 0 dBmO, Dx = 0 dBmO PCM code. Transmit and receive gains programmed for maximum 0 dBmO test levels (0 dB gain),
hybrid balance fitter disabled. All other limits are assured by correlation with other production tests and/or product design and
characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V, VBB = -5V, TA = 25°C.
Symbol Parameter Conditions l Min Typ Max Units
AMPLITUDE RESPONSE (Continued)
GRAL Receive Gain Sinusoidal Test Method
Variation with Reference Level = 0 dBmO
Signal Level VFnl = - 40 dBmo to + 3 dBmO -tt.2 0.2 dB
VFRI = - 50 dBmo to -40 dBmO - 0.4 0.4 dB
VFRI = - 55 dBmo to - 50 dBmO - 1.2 1.2 dB
GXA Transmit Gain Transmit Gain Programmed for Maximum
Absolute Accuracy 0 dBmO Test Level (All 1's in
Gain Register). Apply 0 dBmO PCM - 0.3 0.3 dB
Code to Dx. Measure VFXO.
TA = 25''C
GXAG Transmit Gain Measure Transmit Gain Over the Range
Variation with from Maximum to Minimum Setting.
Programmed Gain Calculate the Deynation trom the _ o.2 0.2 dB
Programmed Gain Relative to Gm,
Le., GXAG = Gamual _ Gprog - GXA.
TA = 25''C, Vcc = 5V, V35 = -5V
GXAT Transmit Gain Measured Relative to GXA
Variation with Temperature Vcc = 5V, V33 = -5V --0.1 0.1 dB
Minimum Gain < Gx < Maximum Gain
GXAF Transmit Gain Relative to 1015.625 Hz, (Note 4)
Variation with Frequency Gx = 0 dB, Dx = O dBmO Code,
GR = 0 dB (Note 4)
f = 296.875 Hz - 0.1 s 0.1 6 dB
f = 1875.00 Hz -ttAS 0.41 dB
f = 2906.25 Hz -OHS 0.78 dB
f = 2984.375 Hz -OAS 0.82 dB
f = 3406.250 Hz -O.T4 0.89 dB
f = 3984.375 Hz - 1 2.2 dB
GXAL Transmit Gain Sinusoidal Test Method.
Variation with Signal Reference Level = 0 dBmO
Level Dx = -40 dBmO to + 3 dBmO - 0.2 0.2 dB
Dx = - 50 dBmO to - 40 dBmO - 0.4 0.4 dB
Dx = - 55 dBmO to -50 dBmO - 1.2 1.2 dB
Dx = 3.1 dBmo
RL = 600n, Gx = --0.5 dB -0.2 0.2 dB
RL = 3000, Gx = -1.2 dB -o.2 0.2 dB
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5V , 5%, V33 = - 5V t5%; FSR and
FSX = 8 kHz or 9.6 kHz; TA = ty'C to + 70°C by correlation with 100% electrical testing at TA = 25°C. f = 1015.625 Hz, VFRI
= o dBmO, Dx = 0 dBm0 POM code. Transmit and receive gains programmed for maximum 0 dBmO test levels (0 dB gain),
hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and
characterization. All signals reterenced to GND. Typicals specified at Vcc = + 5V, V33 = -5V, TA = 25°C.
Symbol Parameter I Conditions Min Typ I Max I Units
NRC Receive Noise, C Message (Note 1)
weighted All 'l 's in Gain Register 2 , 6 dBrnCO
Nxc Transmit Noise, C Message PCM Code is Alternating Positive
Weighted and Negative Zero 1 , dBrnCO
Nxs Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around
- 53 dBmO
Measurement, VFRI z 0 Vrms
PPSFIR Positive PowerSupply Vcc = 5.0 hoc + 100 mVrms
Rejection, Receive f = 0 kHz - 4 kHz (Note 2) 38 dBC
f = 4 kHz - 50 kHz 30 dBC
NPSRR Negative Power Supply V33 = _ 5.0 VDC + 100 mVrms
Rejection, Receive f == 0 kHz - 4 kHz (Note 2) " dBC
f = 4 kHz - 50 kHz 30 dBC
PPSRX Positive Power Supply PCM Code Equals Positive Zero
Rejection, Transmit Vcc = 5.0 Voc + 100 mVrms
Measure VFxO
f = 0 Hz-4000 Hz " dBC
f = 4 kHz-25 kHz 40 dB
== 25 kHz-50 kHz 36 dB
NPSRX Negative Power Supply PCM Code Equals Positive Zero
Rejection, Transmit V88 = --5.0 VDC + 100 mVrms
Measure VFxO
f = 0 Hz-4000 Hz " dBC
f = 4 kHz-25 kHz 40 dB
f = 25 kHz-50 kHz 36 dB
sos Spurious Out-of-Band Signals 0 dBm0, 300 Hz to 3400 Hz Input PCM
at the Channel Output Code Applied at Dx
4600 Hz-7600 Hz - ao dB
7600 Hz-8400 Hz -ao dB
8400 Hz-50,000 Hz - ao dB
DISTORTION
STDR Signal to Total Distortion Sinusoidal Test Method
STDx Receive or Transmit Level = 3.0 dBmO " dBC
Halt-Channel = 0 dBmO to -30 dBmO " dBC
= -40 dBmO 30 dBC
= - 45 dBmO " dBC
STDXL Signal to Total Distortion Sinusoidal Test Method
Transmitwith Level 2 +3.1 dBmO
Resistive Load FIL = 6000, Gx = -0.5 dB 33 dBC
h = 3000, Gx = -1.2dB " dBC
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = + 5V 1 5%, V33 = - 5V i5%; FSn and
FSx = 8 kHz or 9.6 kHz; TA = lyC to + 70''C by correlation with 100% electrical testing at TA = 25°C. f = 1015.625 Hz, VFRI
= 0 dBmO, Dx = 0 dBmO PCM code. Transmit and receive gains programmed for maximum 0 dBmO test levels (0 dB gain),
hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and
characterization. All signals referenced to GND. Typicals specified at Vcc = + 5V, Vim = -5V, TA = 25"C.
Symbot 1 Parameter Conditions Min Typ Max Units
DISTORTION
SFDR Signal Frequency _
Distortion, Receive " dB
SFDx Single Frequency w
Distortion, Transmit " dB
IMD Intermodulation Distortion Receive or Transmit
Two Frequencies in the Range -qq dB
300 Hz-3400 Hz
Note I: Measured by grounded input at VFnL
Note 2: PPSRR, NPSRR. are measured with a - 50 dBmO activation signal applied to VFRI.
Note 3: A signal is Valid if it is above Ve or below " and Invalid it it is between " and vm. For the purposes of this specification the fottowing conditions apply:
a) All input signals are defined as: " = 0.4V, VIH = 2.7V, tx < 10 ns, tr < 10 ns.
b) tn is measured from VIL to Ihrr 1.: is measured trom VIH to Vic,
c) Delay Times are measured from the input signal Valid to the output signal Valid.
d) Setup Times are measured from the data input Valid to the clock input Invalid.
e) Hold Times are measured from the clock signal Valid to the data input Invalid.
f) Pulse widths are measured from V.L to " or from VIH to VIH.
Note 4: A multi-Ione test technique is used.
Definitions and Timing Conventions
DEFINITIONS
w, is the D.C. input level above which an input
level is guaranteed to appear as a logical one.
This parameter is to be measured by performing
a functional test at reduced clock speeds and
nominal timing, (i.e., not minimum setup and hold
times or output Strobes), with the high level of all
driving signals set to Ihr, and maximum supply
voltages applied to the device.
VIL is the DC. input level below which an input
level is guaranteed to appear as a logical zero to
the device. This parameter is measured in the
same manner as VIH but with all driving signal
low levels set to ViL and minimum supply vtgt-
ages applied to the device.
VOH is the minimum DC. output level to which an
output placed in a logical one state will converge
when loaded at the maximum specified load cur-
VOL is the maximum DC. output level to which
an output placed in a logical zero state will con-
verge when loaded at the maximum specified
load current.
Threshold The threshold region is the range of input volt-
Region ages between " and VIH.
Valid A signal is Valid if it is in one of the valid logic
Signal states. (i.e., above ViH or below vo In timing
specifications, a signal is deemed valid at the in-
stant it enters a valid state.
Invalid A signal is invalid if it is not in a valid logic state,
Signal Le., when it is in the threshold region between "
and Vu-i- In timing specifications, a signal is
deemed Invalid at the instant it enters the thresh-
old region.
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply.
Signals
Period
All input signals may be characterized as: VL =
0.4V, VH = 2.4V,1R < 10 ns, tF < 10 ns.
The period of the clock signal is designated as
tpxx where xx represents the mnemonic of the
clock signal being specified.
Rise times are designated as tnw, where yy rep-
resents a mnemonic of the signal whose rise time
is being specified. tnw is measured from " to
Fall times are designated as tpyy, where yy repre-
sents a mnemonic of the signal whose fall time is
being specified. tpyy is measured from VIH to Vic.
The high pulse width is designated as thzH,
where 22 represents the mnemonic of the input
or output signal whose pulse width is being speci-
fied. High pulse widths are measured from VIH to
The low pulse width is designated as tWzzL,
where 22 represents the mnemonic of the input
or output signal whose pulse width is being speci-
fied. Low pulse widths are measured from " to
Setup times are designated as tswwxx. where w
represents the mnemonic of the input signal
whose setup time is being specified relative to a
clock or strobe input represented by mnemonic
xx. Setup times are measured from the WW Valid
to xx Invalid.
Hold times are designated as Twa. where w
represents the mnemonic of the input signal
whose hold time is being specified relative to a
clock or strobe input represented by the mne-
monic xx. Hold times are measured from xx Valid
to ww Invalid.
Delay times are designated as TDXXWIIHIL].
where xx represents the mnemonic of the input
reference signal and yy represents the mnemon-
ic of the output signal whose timing is being
specified relative to xx. The mnemonic may op-
tionally be terminated by an H or L to specify the
high going or low going transition of the output
signal. Maximum delay times are measured from
xx Valid to yy Valid, Minimum delay times are
measured from xx Valid to yy Invalid. This param-
eter is tested under the load conditions specified
in the Conditions column of the Timing Specifica-
tions section of this datasheet.
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Physical Dimensions inches (millimeters) (Continued)
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V28A msv c;
Plastic Leaded Chip Carrier (V)
Order Number N832FX210V
NS Package
LIFE SUPPORT POLICY
Number V2BA
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury _ "f L; ",, sf
to the user. _ V ' - '_....
tuttttgtMtFomAtttttrr ttatttxtatSQeneqmtttthttr National“ N" ... tl" " " .. __. - =
cmpomion emu upon Ltd. Kong Ltd. Do Incl Lute. (Amalia) m. Ltd.
2900 "rtitxxtthJtMt Drive Immune 10 Senseido Bldg SF Suite 5t3,5th F1001 Av. Brig, Fm Lima, 1383 tst Floor. 441 St. Kilda Rd.
PO. Box 58090 03080 Fwattmttg0ttttaA 4-15 Niuhi Wu Ohinachom Golden Han. 6.0 Amat-Coni. 62 Melbame. 3004
Sam Gan, CA 95052-6090 West Germany Srin'murKu. 77 Mody Road. 1mm East, 01451 Soo Paula, SP, Balsi Victory. Australia
Tel; (408) 7216000 Tel: (0-61-41) 1034.) ?okyo 160, Japan KovAoon, Hang Kong Tel: [55/11) 212-5066 Tet (03) 261-5000
TWX: (910) 339-9240 Teiex: 527e49 191:3-299-7001 191:3-7231290 Fax: (55/11) 211-1161 NSBR BR Fax: 61-3~2877458
Fax: (081411 103554 FAX: 3-299-7000 Tam: 52996 NSSEA HX
Fax: 3-3112535
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This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NS32FX210V - product/n532fx210v?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
NS32FX210J - product/n532fx21Oj?HQS=T|-nulI-null-dscatalog-df-pf—nu||-wwe
