NS32C201N-10 ,1.0 W, 5 V, timing control unitElectrical Characteristics
2.4 Switching Characteristics
1.7.1 Normal Wait States 2.4.1 Definit ..
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NS32C201N-10
1.0 W, 5 V, timing control unit
National PRELIMINARY
[ Semiconductor
NS32C201-10/NS32C201-15 Timing Control Units
General Description I: 4-bit input (WAI i n) allowing precise specification of 0 to
15 wait states
The NS32C201 Timing Control Unit (T CU) is a 24-pin device a I I d f . .
fabricated using National's microCMOS technology. It pro- Cyc a Ho or system arbitration and/or memory
refresh
vides a two-phase clock, system control logic and cycle ex- . . - -
tension logic for the Series 320000 microprocessor family. a System timing (FCLK, CTTL) and control (RD, WR, and
. . . DBE) outputs
The TCU input clock can be provided by either a crystal or . .
an external clock signal whose frequency is twice the sys- u Generel purpose Timing State Output m) that
tem clock frequency. identifies internal states
In addition to the two-phase clock for the CPU and MMU n 2rl',1Tht'""' to accommodate slower MOS
(PHI1 and PHI2), it also provides two system clocks for gen- . '' " _
eral use within the system (FCLK and CTTL). FCLK is a fast " Provides ready (RDY) output for the Series 32000
clock whose frequency is the same as the input clock. while OPUS
CTTL is a replica of PHI1 clock. ll Synchrenous system reset generation from Schmitt
The system control logic and cycle extension logic make the trigger input . . .
TCU very attractive by providing extremely accurate bus a Phase synchronization to a reference signal
control signals, and allowing extensive control over the bus I: High-speed CMOS ttrtrhnology
cycle timing. II TTL compatible inputs
II Single 5V power supply
Features I: 24-pin dual-in-line package
a Oscillator at twice the CPU clock frequency
II 2 phase full Vcc swing clock drivers (PHI1 and PHI2)
Block Diagram
" FCLK
INTERNAL CLOCK
W IESEY “w
m JdJl/h -
titWt ' tom:
TL/EE/8524-t
Sl'l-OZOZSSN/Ol-‘lOZOZSSN
NS32C201-10/NS32C201-15
Table of Contents
1.0 FUNCTIONAL DESCRIPTION 2.0 DEVICE SPECIFICATIONS
1.1 Power and Grounding 2.1 Pin Descriptions
1.2 Crystal Oscillator Characteristics 2.1.1 Supplies
1.3 Clocks 2.1.2 Input Signals
1.4 Resetting 2.1.3 Output Signals
1.5 Synchronizing Two or More TCUs
1.6 Bus Cycles
1.7 Bus Cycle Extension
2.2 Absolute Maximum Ratings
2.3 Electrical Characteristics
2.4 Switching Characteristics
1.7.1 Normal Wait States 2.4.1 Definitions
1.7.2 Peripheral Cycle 2.4.2 Output Loading
1.7.3 Cycle Hold 2.4.3 Timing Tables
1.8 Bus Cycle Extension Combinations 2.4.4 Timing Diagrams
1.9 Overriding WAIT Wait States
List of illustrations
Crystal Connection ............................................................................................. 1-1
PHI1 and PHI2 Clock Signals .................................................................................... 1-2
Recommended Reset Connections (Non Memory-Managed System) ................................................ 1-3a
Recommended Reset Connections (Memory-Managed System) .................................................... 1-3b
Slave TCU does not use RW-EN during Normal Operation .......................................................... 1-4a
Slave TCU Uses Both SYNC and AWE-N ._......W............_.....l.l.................l.. 1 Mb
Synchronizing Two TCUs m...................................................................................... 1-5
Synchronizing One TCU to an External Pulse ...................................................................... 1-6
Basic TCU Cycle (Fast Cycle) ........I..............F......l.........P_..l................... 1-7
Wait State Insertion Using TWATT (Fast Cycle) ..................................................................... 1-8
Wait State Insertion Using Wm: (Fast Cycle) ..................................................................... 1-9
Peripheral Cycle .............................................................................................. 1-10
Cycle Hold Timing Diagram T....-............................................................................... 1-11
Fast Cycle with 12 Wait States .................................................................................. 1-12
Peripheral Cyc1e with Six Wait States ............................................................................ 1-13
Cycle Hold with Three Wait States ............................................................................... 1-14
Cycle Hold of a Peripheral Cycle ...r....l.......p......-..r.r........-l.p.l.-. 1-15
Overriding WAITn Wait States .................................................................................. 1 ~16
Connection Diagram ....l.................-.......l......-....l...l...._.. 2-1
Clock Signals (a) P.............................................-..................... . .......................... 2-2
Clock Signals (b) F..............................-............................................................... 2-3
Control Inputs B..................'.'........................................................................... 2-4
Control Outputs (Fast Cycle) ..................................... . ............................................... 2-5
Control Outputs (Peripheral Cycle) ............................................................................... 2-6
Control Outputs (T Rl-STATE Timing) ............................................................................. 2-7
Cycle Hold .................................................................................................... 2-8
Wait States (Fast Cycle) ...-....Pl...-.......F........-Ip....p......-.............. 2-9
Wait States (Peripheral Cycle) ..-......_..._..............l....-r........P..m.-......... 2-10
Synchronization Timing ..............._.l......ll.....l.l.................... 2-11
1.0 Functional Description
1.1 POWER AND GROUNDING
The NS32C201 requires a single +5V power supply, ap-
plied to pin 24 (Vcc). See Electrical Characteristics. The
Logic Ground on pin 12 (GND), is the common pin for the
A 0.1 pF, ceramic decoupling capacitor must be connected
across Va: and GND, as close to the TCU as possible.
1.2 CRYSTAL OSCILLATOR CHARACTERISTICS
The NS32C201 has an internal oscillator that requires con-
nections of the crystal and bias components to XIN and
XOUT as shown in Figure 14. it is important that the crystal
and the RC components be mounted in close proximity to
the XIN, XOUT and Vcc pins to keep printed circuit trace
lengths to an absolute minimum.
Typical Crystal Specifications:
Type ........................................... At-Cut
Tolerance .............................. th005% at 25''C
Stability .......................... 0.01% from O' to 70°C
Resonance ...................... Fundamental (parallel)
Capacitance ''''''''"''''''"'''''''''''', ........ 20pF
Maximum Series Resistance ........................ 500
CRYSTAL
teen FREQUENCY R
'lit' (MHz) (OHM)
m m = 6-12 470
12-18 220
(1:) 18-24 1 00
24-30 47
TL/EE/8524-3
FIGURE 1-1. Crystal Connection Diagram
_-__——_ ..1
-Ii—5"o—J E
_.___-.._ -J
L ............. u
EXTERNAL RESET
(OPTIONAL
L - - J
RESET swn'cn
(osmomL)
1.3 CLOCKS
The NS32C201 TCU has four clock output pins. The PHI1
and PH12 clocks are required by the Series 32000 CPUs.
These clocks are non-overlapping as shown in Figure 1-2.
the T-STATEJ
NON-OVERLAPPINO
TL/EE/8524--4
FIGURE 1.2. PHI1 and PHI2 Clock Signals
Each rising edge of PHI1 defines a transition in the timing
state of the CPU.
As the TCU generates the various clock signals with very
short transition timings, it is recommended that the conduc-
tors carrying PHI1 and PHI2 be kept as short as possible. It
is also recommended that only the Series 32000 CPU and, if
used, the MMU (Memory Management Unit) be connected
to the PHI1 and PHI2 clocks.
CTTL is a clock signal which runs at the same frequency as
PHI1 and is closely balanced with it.
FCLK is a clock, running at the frequency of XIN input. This
clock has a frequency that is twice the CTTL clock frequen-
cy. The exact phase relationship between PHI1, PHI2, CTTL
and FLCK can be found in Section 2.
amt “832001.
TCU CPU
rim ritiii5 risiims5
SYSTEM RESET
TL/EE/8524-5
FIGURE 1-aa. Recommended Reset Connections (Non Memory-Managed System)
cc umczot MSW ttta2tNM6
0 mu uuu cru
r ------------ -1 ‘t
t I .m. ?
I - - - -
l RESET > w: ', l I, nsn RSTO m I','; RSWABT
'' ', l l I ..L
L. --------- J l 'I i "
EXTERNAL RESET ' I
(OPTIONAL l = t T-- 2 50 um
L - - - d
RESET SWITCH
(OPTIONAL)
TL/EE/MM-ts
FIGURE 1-3b. Recommended Reset Conrtetttlttrttt (Memory-Managed System)
Sl'lOZOZSSN/Ol'I-OZOZSSN
NS320201-10/NS3ZC201-15
1.0 Functional Description (Continued)
1.4 RESETTING RWEN/SYNC input to the slave TCU(s) is used for synchro-
The NS32C201 TCU provides circuitry to meet the reset nization. The Slave TCU samples the RWEN/SYNC input
requirements of the Series 32000 CPUs. If the Reset Input on the rising edge of XIN. When R§T5 is low and CTTL is
line. MTI is pulled low, the TCU asserts A gtt5 which resets high (see Figure Gti), if RWEN/SYNC is sampled high, the
the Series 32000 CPU. This Reset Output may also be used phase of CTTL of the Slave TCU is shifted by 009 XIN clock
as a system reset signal. Figure 1-3a illustrates the reset cycle.
connections for a non Memory-Managed system. Figure Two possible circuits for TCU synchronization are illustrated
1-3b illustrates the reset connections for a Memory-Man- in Figures 1-4a and 1-4b. It should be noted that when
aged system. RWEN/SYNC is high, the wo and WM signals will be TRI.
1.s SYNCHRONIZING TWO on MORE TCUs STATE on the slavtt TCU. . .
Note. 'GeRtsyNc should not be kept constantly high during reset. other.
During reset, (when 9316 is low), 006 or more TCUs can wisethe clock will bestoppedandthe device will notexltreset whenritmis
be synchronized with a reference (Master) TCU. The deassenad.
Iwan/svuc - .
1'ltgtt't', msm
xm 's nu cm
EXTERNAL XIN TCO
sum 13
TLJEE/8524-7
FIGURE 1-4a. Slave TCU Does Not Use RWEN During Normal Operation
RWENISYNC
'ttWelt
' " J%" cm
suvs [
mam " mu
cum 13
TL/EE/8524-8
FIGURE 1-4b. Slave TCU Uses Both SYNC and RWEN
Note: When two or more TCUa are to be synchronlzed. the XIN of all the TCUs should be connected to an external clock source. For details on the external clock,
see Swltchlng Spottlfietstiomt In Section 2.
XIN -L.,/""""lp'''"'""L.ve \ / \ f \ / "ic.
:PHASE CHANGE: '
MN/smc
iii, N
ET?) N
FIGURE 1-5. Synchronlzlng Two TCU:
TL/EE18524-9
1.0 Functional Description (Continued)
Wlsvuc / \
TL/EE/8524-10
FIGURE b6. Synchronlzlng One TCU to An External Pulse
In addition to synchronizing two or more TCUs, the RWEN/
SYNC input can be used to "fix" the phase of one TCU to
an external pulse. The pulse to be used must be high for
only one rising edge of XIN. Independent of CTTL's state at
the XlN rising edge, the CTTL state following the XIN rising
edge will be high. Figure 1-6 shows the timing of this se-
quence.
1.6 BUS CYCLES
In addition to providing all the necessary clock signals, the
N3320201 TCU provides bus control signals to the system.
The TCU senses the me signal from the CPU or MMU to
start a bus cycle. The EDIN input signal is also sampled to
determine whether a Read or Write cycle is to be gener-
CN STATES T1 tt T3
tto STATES tt T2 T3
ated. In addition to WO and WA, other signals are provided:
BTX and m. DTI" is used to enable data buffers. The
leading edge of 15iTE is delayed a half clock period during
Read cycles to avoid bus conflicts between data buffers and
either the CPU or the MMU. This is shown in Figure 1-7.
The Timing State Output CTW) is a general purpose signal
that may be used by external logic for synchronizing to a
System cycle. T96 is activated at the beginning of state T2
and returns to the high level at the beginning of state T4 of
the CPU cycle. TSU can be used to gate the CWNT signal
when continuous waits are required. Another application of
m is the control of interface circuitry for dynamic RAMs.
Notes:
. The CPU and TCU view some tim-
ing states (T-states) differently.
For clarity, reterences to T-states
will sometimes be followed by
(TCU) or (CPU). (CPU) also im.
plies (MMU).
2. Arrows indicate when the TCU
samples the input.
1% is assumed low (AO and
WR enabled) unless spxreitied dif-
fetently.
4. For clarity, T-states for both the
---q-hm---.-Mr.
TCU and CPU are shown above
the diagrams. (See Note 1.)
-- t I
L-... ---.--- ,
“E l l f
Mt HIGH
FIGURE 1-7. Battle TCU Cycle (Fast Cycle)
TL/EE/8524-tt
9 L'lOZGZSSN/OL'WZOZSSN
NS320201-10/N5320201-15
1.0 Functional Description (Continued)
1.7 BUS CYCLE EXTENSION There are three basic cycle extension modes provided by
The N3320201 TCU uses the Wait input signals to extend the TCU, as described below.
normal bus cycles. A normal bus cycle consists of four PHI1 111 Normal Walt States
clock cycles. Whenever one or more Wait inputs to the TCU
are activated, a bus cycle is extended by at least one PHI1
clock cycle. The purpose is to allow the CPU to access slow
memories or peripherals. The TCU responds to the Wait
signals by pulling the RDY signal low as long as Wait States
This is a normal Wait State insertion mode. It is initiated by
pulling CWNT or any of the WAITn lines low in the middle of
T2. Figure bl? shows the timing diagram of a bus cycle
when CWZIT is sampled high at the end of T1 and low in the
are to be inserted in the Bus cycle. middle of T2.
CPU SIATES T1 12 T3 ......... " T3 "
TCU STATES _ TI tt " "
-e l n
Kb l t
- e- J
TL/EEft1624- 1 2
FIGURE 1-8. Walt State Inserllon Using CWAIT (Fast Cycle)
1.0 Functional Description (Continued)
The RDY signal goes low during T2 and remains low until tjil7NT is high during the entire bus cycle, then the RDY line
CWAIT is sampled high by the TCU. RDY is pulled high by goes low for 1 to 15 clock cycles, depending on the binary
the TCU during the same PHI1 cycle in which the CWKIT weighted value of Wwrn. If, for example, WAIT1 and
line is sampled high. th-tNTU- are sampled low, then five wait states will be insert-
It any of the WNT7 signals are sampled low during T2 and tad. This is shown in Figure f-9.
CPO STATES T1 T2 " " .......... T3 T3 "
Ttht STATES T1 T2 m1 TW2 ....... Wht " "
EM TE-'"
---~ "d-
m-ie.,....,. -
- "I..- .i-e%
L-., --- ----ii?--r ---
- Ill, C
---_ iii'/iii,i,,i,,i,, I44 ttlil/i, ijiliiiiiiiiiiiii 4444/ 'titit
cwm 44 iliiTEiiT%ii iii')' iiiiiiiiiiiiitt (i'tii' 'f/fi)
(//f, it/'grliiiiii, /4444/ iii/tIa/iii, 44444444
"qiiLliL gf/i/rj/ijt/ij: _if/ig'iti) iiiiiiliiiiittt,l, 'i/f, /4 'fig)
FIGURE 1-9. Walt State lnsertlon Using WAlTn (Fast Cycle)
TLfEtif85M- 13
9 l'l-OZOZSSN/Ol'l-OZOZSSN
NS32C201-10/NS32C201-15
1.0 Functional Description (Continued)
1.7.2 Peripheral Cycle
This cycle is entered when the PER signal line is sampled
low at the beginning of T2. The TCU adds thm wait_states
identified as TDO-TD4 into a normal bus cycle. The RD and
CPU STATES T1 T2 " "
""'':'uri' ji fir/inf-il/is-ir/is-Ly-
WA signals are also re-shaped so the setup and hold times
for address and data will be increased.
This may be necessary when slower peripherals must be
accessed.
Figure 1-10 shows the timing diagram of a peripheral cycle.
T3 " T3 T3 "
- L.--, I-.......---...-.------....--------.---..-
FIGURE 1-10. Peripheral Cycle
1.0 Functional Description (Continued)
1.7.3 Cycle Hold
If the i5WNT input is sampled low at the end of state T1, the
TCU will go into cycle hold mode and stay in this mode for
as long ECMIT is kept low. During this mode the control
signals RD, WR, 'tgt5 and DB? are kept inactive; HDY is
CPU STATES T1 "
TCU STATES T1 til "'
FNlt JI fl
?'''r'" R h h 1"
pulled low, thus causing wait states to be inserted into the
bus cycle. The cycle hold feature can be used in applica-
tions involving dynamic RAMs. A timing diagram showing
the cycle hold feature is shown in Figure 1-11.
llll l I
m l [-
TLtEE/8524-15
FIGURE 1-11. Cycle Hold Tlmlng Dlagram
1.8 BUS CYCLE EXTENSION COMBINATIONS
Any combination of the TCU input signals used for extend-
ing a bus cycle can be activated at one time. The TCU will
honor all of the requests according to a certain priority
scheme. A cycle hold request is assigned top priority. It fol-
lows a peripheral cycle request, and then CWATT and
WE respectively.
It. for example, all the input signals CWNT, PEA and WN'h5
are asserted at the beginning of the cycle. the TCU will en-
ter the cycle hold mode. As soon as CWKIT goes high, the
input slgnal PEA is sampled to determine whether a periph-
eral cycle is requested.
Next, the TCU samples t5il7NT again and WNTE to check
whether additional wait states have to be inserted into the
bus cycle. This sampling point depends on whether FEE
was sampled high or low. It PEA was sampled high, then the
sampling point will be in the middle of the TCU state T2,
(Figure GM), otherwise it will occur three clock cycles later
(Figure 1-15). Figures 1-12 to 1-15 show the timing dia.
grams for different combinations of cycle extenslons.
9 l'lOZOZSSN/OL'I-OZOZESN
NS32C201-10/N8320201-15
1.0 Functional Description (Continued)
CN STATES
Ttlll STATES
PHI1 J
" T3 " T3.,.......T3 "
12 Tthhl Tthe m1 ... "mm 13
eiljijLriljiLji'iLhLhL1
l l I l i
1Wtf j
WIT! i
"glg Il,',' fl,','
FIGURE 1-12. Fast Cycle With 12 Walt States
(2 CWAIT and WAIT10) (Read Cycle)
1.0 Functional Description (Continued)
FIGURE 1-13. Porlphml Cycle with Six Walt States
(1 EWIIT and WINS) (Write Cycle)
Sl'l-OZOZSSN/Ol'lOZOZSSN
NS320201-10/NS32C201-15
1.0 Functional Description (Continued)
CPU STATES TI " T3 13 " Ta " T3 "
TN STAYES T1 Th TH T2 TCW TWI 1W2 T3 T4
,c.jncn.jl M h nj-y lit...)
a-a-r-l l L,....)
mm man
Whitt L0
Fiit7 m
"i'etttir" tt I
Mt l /
FIGURE 1-14. Cycle Hold with Three Walt States
(1 GWKIT and WW) (Road Cycle)
TL/EE/8624-t8
1.0 Functional Description (Continued)
CPU STATES
Ttlo STATES
"v/L/L/L/
T1 T2 T3 T3
T1 TH.... ....TH T2
i-tLi-hui-ji-ji-ll-
T3 " T3 T3 " "
T01 T02 T03 TM T3 "
MN f, u
L - g l" -
2; --- --..- L --
'm-o-i-. - ----.t
iilTt" f
cwm /%////
/,”////// /////////.
"riirii_i___ir_r_iiir_,
iiFiiiiiiiiiiiiiiGi
////////
"lilliiilh,
////////
TL/EE/8524-19
FIGURE 1-15. Cycle Hold ot a Peripheral Cycle
1.9 OVERRIDING WAITn WAIT STATES
The TCU handles the WKITn Wait States by means of an
internal counter that is reloaded with the binary value corre-
sponding to the state of the WAITn inputs each time CWAIT
is sampled low, and is decremented when CWAIT is high.
This allows to either extend a bus cycle of a predefined
number of clock cycles, or prematurely terminate it. To ter-
minate a bus cycle, for example, CWAIT must be asserted
for at least one clock cycle, and the WAITn inputs must be
forced to their inactive state.
At least one wait state is always inserted when using this
procedure as a result of CWAIT being sampled low. Figure
7-16 shows the timing diagram of a prematurely terminated
bus cycle where eleven wait states were being inserted.
SL'LOZOZSSN/Ol-‘lOZOZSSN
NS320201-10/N5320201-15
1.0 Functional Description (Continued)
CPO STATES n
Ttlo smss " m1 twt ma Tthhl " "
frtllt JL/L/il/il/L/ill/il/L/
l + l I
sampled
FIGURE 1-16. Overriding WAITn Walt States
(Write Cycle)
2.0 Device Specifications
2.1 PIN DESCRIPTIONS
The following is a description of all N832C201 pins. Tho
descriptions reference portions of the Functional Descrip-
tion, Section 1.
2.1.1 Supplies
Power (Vcc): + 5V positive supply. Section 1.1.
Ground (GND): Power supply return. Section 1.1.
2.1.2 Input Signals
Reset Input (RSTI): Active low. Schmitt triggered. asyn-
chronous signal used to generate a system reset. Section
Address Strobe (ADS): Active low. Identifies the first timing
state fr 1) of a bus cycle.
Data Direction Input (DDIN): Active low. Indicates the di-
rection of the data transfer during a bus cycle. Implies a
Read when low and a Write when high.
Note: In Rev. A of the N3326201 this signal is CMOS compatible. In later
revisions it is TTL compatible.
Road/erte Enable and Synchronization fmiilER/
SYNC): TRI-STATE© the M and the WM outputs when high
and enables them when low. Also used to synchronize the
phase of the TCU clock signals, when two or more TCUs
are used. Section 1.5.
Crystal or External Clock Source (XIN): Input from a crys-
tal or an external clock source. Section 1.3.
Ctttttlrtutttm Walt teWrum.. Active low. Initiates a continu-
ous wait if sampled low in the middle of T2 during a Fast
cycle, or in the middle of TD2, during a peripheral cycle. If
CWKIT is low at the end of TI, it initiates a Cycle Hold.
Section 1.7.1.
Four-Blt Walt State Inputs twam, Warm WAiT4 and
WAITB): Active low. These inputs, (collectively called
WNTii), allow from zero to fifteen wait states to be speci-
fied. They are binary weighted. Section 1.7.1.
Peripheral Cycle Crrrrty Active low. It active, causes the
TCU to insert five wait states into a normal bus cycle. It also
causes the Read and Write signals to be re-shaped to meet
the setup and hold timing requirement of slower MOS pe-
ripherals. Section 1.7.2.
2.1.3 Output Signals
Reset Output (RSTE): Active low. This signal becomes ac-
tive when Agn is low, initiating a system reset. R§TO goes
high on the first rising edge of PHI1 after A3FTT goes high.
Section 1.4.
Read Strobe tAmy (T RI-STATE) Active low. Identifies a
Read cycle. It is decoded from DDIN and TRI-STATE by
§WEN/SYNC. Section 1.6.
Write Strobe twmp (T RI-STATE) Active low. Identifies a
Write cycle. It is decoded from DDIN and TRl-STATE by
AWE-N/SYNC. Section 1.6.
Note: FE and WE are mutually exclusive in any cycie. Hence they are never
low at the same time.
Data Butter Enable trTiiTty Active low. This signal is used
to control the data bus buffers. it is low when the data buff-
are are to be enabled. Section 1.6.
Timing State Output (T SO): Active low. The falling edge of
TS‘G signals the beginning of state T2 of a bus cycle. The
rising edge of Tgo signals the beginning of state T4. Sec-
tion 1.6.
Ready (ROY): Active high. This signal will go low and re-
main low as long as wait states are to be inserted in a bus
cycle. It is normally connected to the RDY input of the CPU.
Section 1.7.
Fast Clock (FOLK): This is a clock running at the same
frequency as the crystal or the external source. Its frequen-
cy is twice that of the CPU clocks. Section 1.3.
CPU Clocks (PHI1 and PHI2): These outputs provide the
Series 32000 CPU with two phase, non-overlapping clock
signals. Their frequency is half that of the crystal or external
source. Section 1.3.
System Clock (CTTL): This is a system version of the PHI1
clock. Hence, it operates at the CPU clock frequency. Sec-
tion 1.3.
Crystal Output (XOUT): This line is used as the return path
for the crystal (if used). It must be left open when an exter-
nal clock source is used to drive XlN. Section 1.2.
Sl'lOZOZSSN/Ol'IOZOZSSN
NS32C201-10/NS320201-15
2.0 Device Specifications (Continued)
2.2 ABSOLUTE MAXIMUM RATINGS (Note I)
If Mllltary/Aerospace specified devices are required,
please contact the Natlonal Semlconductor Sales
offltMVDlatrlButors for avaliablllty and speclflcatlons.
Note: Absolute maximum ratings indicate limits beyond
which permamant damage may occur. Continuous opera-
tion at these limits is not intended; operation should be limit-
ed to those conditions specified under Electrical Character-
istics.
Supply Voltage 7V
Input Voltages -- 0.5V to Vcc + 0.5V
Output Voltages -0.5V to VCC + 0.5V
Storage Temperature - 65''C to + 150°C
Lead Temperature (Soldering, 10 sec.) 30ty'C
Continous Power Dissipation 1W
2.3 ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C. VCC = SV 15%, GND = 0V
Symbol Parameter Conditions Min Typ Max Unlts
VIL Input Low Voltage All Inputs Except W 8 XIN 0.8 V
VIH Input High Voltage All Inputs Except MTI & XIN 2.0 V
VT+ WSTT Rising Threshold Voltage Vcc = 5.0V 2.5 3.5 V
VHYs WSW Hysteresis Voltage Vcc = 5.0V 0.8 1.9 V
VXL XIN Input Low Voltage 0.20 Vcc V
VXH XIN Input High Voltage 0.80 Vcc V
ll. Input Low Current VIN = 0V --1 0 PA
IIH Input High Current VIN = VCC 10 pA
VOL Output Low Voltage mtggiégms Exp: XOUT, I = 2 mA th10 VCC V
VOH Output High Voltage 2g8$7u5 fl",',') th90 Vcc V
IL Leakage Current on WNW 0.4V s VIN s V00 -20 +20 pA
lcc Supply Current fxin = 20 MHz 100 120 mA
Note 1: All typical values are tor Vcc = 5V and TA = 25'C,
Connection Diagram
Dual-ln-Une Package
ME 1 " -tte
ItTiETtttrttt- 2 " y-re,
M--, a " --.em
M..-- J tl .-.ttitri
Miil- I N '--Eiltt
m-- ' tl382tt20t " -em
m-- T Ttil ll "-emt
'm- a " --m
Mt-- , " -0tTL
'tfit-.- " " "-rttA
Ftilt-- 11 u -tthn
'tto--., It u ,-rltt
TL/EE/8524-2
Top Vlew
Order Number N3320201D or N8320201N
See NS Package Number D240 or N24A
FIGURE 2.1
2.0 Device Specifications (Continued)
2.4 SWITCHING CHARACTERISTICS
2.4.1 Deflnltlons
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
and PHI2; to 15% or 85% of Vcc on all the CMOS output
signals, and to 0.8V or 2.0V on all the TTL input signals,
unless specifically stated otherwise.
2.4.2 Output Loading
Capacitive loading on output pins for the N8320201.
RDY, TEE, -t%y ................................. 50 pF
AT5, WA ........................................ 75 pF
CTTL ..................................... 50 + 100 pF
FCLK ......................................... 100 pF
PHI1, PHI2 ..................................... 170 pF
ABBREVIATIONS
L.E.--Leading Edge
Te-Trailing Edge
R.E.--Rising Edge
F.E.-Falling Edge
2.4.3 Tlmlng Tables
Symbol Figure Description RttfttrttttttefCtttttiltlontt NS32C20t-10 NS32tt20tNi UnIts
Mln l Max Min Max
CLOCK-SIGNALS (XIN, FCLK, PHI1 & PHI2) TIMING
top 2.2 Clock Period PHI1 R.E. to Next
PHI1 ms. 100 66 ns
tcu, 2.2 Clock High Time At 90% Vcc on PHI1 0.5 ttm 0.5 top 0.5 top 0.5 top
(Both Edges) -15 ns - 7 ns -10 ns -3 ns
tcu 2.2 Clock Low Time At 15% Vcc on PHI1 0.5 km 0.5 top 0.5 tap 0.510;.
-5ns +10ns -5ns +6ns
ttso ,2) 2.2 Clock Pulse Width At 2.0V on PHI1, PHI2 0.5 tty, 0.5 tcp 0.5 top 0.5 ity,
(Both Edges) - 10 ns -4 ns -8 ns -4 ns
tCLwas PHI1, PHI2 Asymmetry At 2.0V on PHI1, _ 5 5 --3 3 ns
(tCLw (1) - tcm (2)) PHI2
1cm 2.2 Clock Rise Time 15% to 90% Vcc 8 6 n s
on PHI1 RE.
‘CLF 2.2 Clock Fall Time 90% to 15% vcc 8 6 ns
on PHI1 F.E.
Govt. (1,2) 2.2 Clock Non-Overlap Time he''' Vcc on PHI1, -2 + 2 - 2 + 2 ns
tnOVLas Non-Overlap Asymmetry At 15% Vcc on PHI1, - 4 4 - 3 3 ns
(tnOVL (1) - tnow. (2)) PHI2
tXh 2.2 XIN High Time At 80% vcc on XIN 16 10 ns
(External Input) (Both Edges)
txl 2.2 XIN Low Time At 15% hx on XIN 16 10 ns
(External Input) (Both Edges)
tXFr 2.2 XIN to FCLK F.E. Delay 80% Vcc on XIN RE.
to FCLK ma. 6 29 6 25 "
txpf 2.2 XIN to FCLK F.E. Delay 15% Vcc on XIN F.E.
to FCLK F.E. 6 29 6 " "
tXCr 2.2 XIN to CTTL RE. Delay 80% Vcc on XIN RE.
to CTTL ms. 6 34 6 25 "
txp, 2.2 XIN to PHI1 RE, Delay 80% V00 on XIN RE.
to PHI1 R.E, 6 32 6 25 ntt
tpc, 2.2 FCLK to CTTL RE. Delay FCLK RE, to CTTL RE. 0 6 0 6 ns
tpcf 2.2 FCLK to CTTL F.E. Delay FCLK RE. to CTTL FE. -3 4 -3 4 "
tpp, 2.3 FCLK to PHI1 RE. Delay FCLK RE. to PHI1 RE. -3 4 -3 4 ns
tppt 2.3 FCLK to PHlt F.E. Delay FCLK RE. to PHlt F.E. -5 2 -5 2 ns
tFw 2.3 FCLK Pulse Width At 50% Vcc on FCLK 0.25 top 0.25 top 0.25 top 0.25 top
with Crystal (Both Edges) --5 ns + 5 ns -5 ns + 5 ns
tpcf 2.3 PHI2 R.E.to CTTL PH12 RE, to CTTL F.E. - -
F.E. Delay 3 4 a 6 M
km, 2.3 CTTL Pulse Width At 50% va: on CTTL 0.5 top 0.5 top 0.5 top 0.5 ttop
(Both Edges) -7 ns +1 ns -5 ns + 1 ns
Not. 1: htty, tra, tscy. tpct, ten, are measured with 100 pF load on CTTL.
Note 2: PHH and PHI2 are Interchangeable for the following parameters: top. tam, teu, tthar, 10an tar, tnovL. htpr, tppr, tret.
Sl'LOZOZSSN/Ol'lOZOZSSN
NS32CZO1-10/NS32C201-15
2.0 Device Specifications (Continued)
2.4.3 Tlmlng Tables (Continued)
Symbol Figure Descriptlon Rtthtrentte/Cttttdltitmtg NS32C201M0 Ms32c201-15 Unlts
Mln Max Min I Max
CTTL TIMING (CL = 50 pF)
tpty 2.3 PHI1 to CTTL RE. Delay PHI1 RE. to CTTL RE. -2 5 - 2 3 ns
ttmt 2.3 CTTL Rise Time 10% to 90% Vcc 7 6 ns
on CTTL R.E.
'ch 2.3 CTTL Fall Time 90% to 10% Vcc 7 6 ns
on CTTL FE.
CTTL TIMING (CL = 100 pF)
1pc, 2.3 PHI1 to CTTL RE. Delay PHI1 RE. to CTTL RE. - 2 6 -2 4 ns
tom 2.3 CTTL Rise Time 10% to 90% Vcc 8 7 ns
on CTTL R.E.
ton: 2.3 CTTL Fall Time 90% to 10% vcc a 7 ns
on CTTL F.E.
CONTROL INPUTS (m, ABS, W) TlMING
tnsrs 2.4 W Setup Time Before PHI1 RE. 20 15
tADs 2.4 505 Setup Time Before PHI1 RE. 25 20 ns
tADw 2.4 A_Ds' Pulse Width ES LE. to Mrs TE. 25 20 ns
top; 2.4 D-DIN Setup Time Before PHI1 RE. 15 13 ns
CONTROL OUTPUTS (W6, tWO, E. WA, t5rre a RWEN/SYNC) TIMING
tRST, 2.4 W6 RE. Delay After PHI1 RE. 21 10 ns
tr, 2.5 T36 L.E. Delay After PHI1 R.E. 12 8 ns
tTr 2.5 T36 T.E. Delay After PHI1 RE. 3 18 3 10 ns
trtwttn 2.5 FTD-AT/A" L.E. Delay (Fast Cycle) After PHI1 RE. 30 21 ns
tRWf(S) 2.6 '1rv.T LE. Delay After PHI1 RE. 25 1 5 ns
(Peripheral Cycle)
tRw, 2.5/6 AB/WA T.E. Delay After PHI1 RE. 3 20 3 15 ns
10W, 2.5/6 m LE. Delay (Write Cycle) After PHI1 RE. 25 15 ns
toBttrt) 2.5/6 WE L.E. DeIay (Read Cycle) After PHI2 RE. 20 11 ns
1.33, 2.5/6 BEE T.E. Delay After PHI2 RE. 20 15 ns
but 2.7 MJF Low Level to TRl-STATE After WISYNC RE. 25 20 ns
1sz 2.7 At5,% High Level to TRI-STATE After 'FW/SYNC RE. 20 15 ns
thL 2.7 FEW TRI-STATE to Low Level After AWTiN/SYNC F.E. 25 18 ns
bzrs 2.7 AT5,WA TRI-STATE to High Level After AWER/SYNC FE. 25 18 ns
WAIT STATES & CYCLE HOLD (WIT, Tarrh, m & MY) TIMING
ttrwstH) 2.8 INWt" Setup Time (Cycle Hold) Before PHI1 R.E. 30 20 ns
'cme) 2.8 CWT Hold Time (Cycle Hold) After PHI1 R.E. 0 ns
ttowstw) 2.8/9 TWATT" Setup Time (Wait States) Before PH12 R.E. 10 ns
‘cme 2.9 W Hold Time (Wait States) After PHI2 R.E. 20 10 ns
tws 2.9 1% Setup Time Before PHI2 RE. 7 6 ns
tWh 2.9 WN-TT, Hold Time After PHI2 RE. 15 10 ns
tps 2.10 Pt-yt Setup Time Before PHI1 R.E. 7 5 ns
tph 2.10 Tim Hold Time After PHI1 RE. 30 20 ns
tad 2.8/9/10 A-DN Delay After PHI2 RE. 25 12 ns
SYNCHRONIZATION (SYNC) TIMING
tsys 2.11 SYNC Setup Time Before XIN RE. 6 6 ns
tSyh 2.11 SYNC Hold Time After XIN RE. ns
tcs 2.11 CTTL/SYNC Inversion Delay 1i.T...'..T...t=(master) to 10 7 ns
RWEN/SYNC (slave)
2.0 Device Specifications (Continued)
2.4.4 Tlmlng Diagrams
'or. Vcc
tcsta) ‘novun
TL/EE/8524-21
FIGURE 2-2. Clock Signals (a)
trr, - tm
bc, - tcm tcm tce
cm I ,
FIGURE 2-3. Clock Signals (b)
TL/EE/8524-22
""l-/'-L,,. 511] N
test, -
Fn s.svir " "
tnsrr> lo
"s_.._f t "“ADS"
- S S w
ADS A I
s s " - tDs
ODIN 5 5 X
TL/EE/8524-23
FIGURE 2-4. Control Inputs
9 l'lOZOZSSN/Ol'l-OZOZESN
N832C201-10/NS32C201-15
2.0 Device Specifications (Continued)
PHI1 J1}
e-C.vet1.sie-s(Le-
titwr -
toar- F
FIGURE 2-5. Control Outputs (Fast Cycle)
"-n" 'ii' js-il-jr-ir-i:
-'"lcf1cf)cf'"1
si' f?" or-il-h-L-ir-
----thth
TL/EE/8524-24
- mm” tmer---
..__-- - .-- . - ,
---------r--"
- tum” -
----t-i,
FIGURE 2-6. Control Outputs (Peripheral Cycle)
- 2.0V
awsN/svnc 7
a 1." -..-
an _] tr." N,
m T 05v tptt
mn___3_r .
‘le 'r"--""
Rc-a,,.,,-...)]
TL/EE/8524-25
TL/ EE/8524-28
FIGURE 2-7. Control Outputs (T RI-STATE Tlmlng)
2.0 Device Specifications (Continued)
n TH1 (mm) m" (LAST) T2
t tcww)
PRI2 'N
kw u ‘ A - tcm, H
't , ( ) ttmo)
W CYCLE HOLD 'cis-ut-tif"-' Whit STATE
tea' tttd
. ----.------
Rot REMAINS LOW
FOR SUBSEOUENT WAIT
TL/EE/8524-27
FIGURE 2-8. Cycle Hold
tl T2 TCW on TW,, n
PMI ''"""-hc,_jt ps N, /‘_\
PHI2 CDs. s..y't / \
w“) (W)
t-thtt "
Whit n
tttd -
Rot J -S s--?
FIGURE 2-9. Walt State (Fast Cycle)
TL/EE/8524-28
T1 T2 T00 T01 TO2 TCW 0R TWn T03 TIU T3
ssm..y'"h '\_/\_/\ 'ssa/'"'u/'"Ns'"hcs/'"hcy'"N
CWAIT .5 '
-AR teh
tire -
PER " "
‘Ru~[ - thas
ROt ..
FIGURE 2-10. Walt State (Peripheral Cycle)
TC/EEf8524-29
Sl'lOZOZSSN/Ol'IOZOZI-ISN
NS32C201-10/NS32C201-15
2.0 Device Specifications (Continued)
Wxsvuc i
- tsy, - tsh,
FIGURE 2-11. Synchronlzatlon Tlmlng
TL/EE/8524-30
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NS32C201D-10 - product/n532c201d-10?HQS=T|-nu|I-nulI-dscataIog-df-pf-null-wwe
NS32C201D-15 - product/ns320201d-157HQS=T|-nu|I-nulI-dscatalog-df-pf—null-wwe
NS32C201N-10 - product/ns32c201n-107HQS=T|-nu|I-nulI-dscatalog-df-pf-null-wwe
NS32C201N-15 - product/ns32c201n—15?HQS=T|-nu|I-null-dscatalog-df—pf—null-wwe
