NS32202D-10 ,1.5 W, 5 V, interrup control unitBlock Diagram .................................................................................... ..
NS32203D-10 ,1.1 W, 5 V, direct memory access controller
NS32C201N-10 ,1.0 W, 5 V, timing control unitElectrical Characteristics
2.4 Switching Characteristics
1.7.1 Normal Wait States 2.4.1 Definit ..
NS32FX161AV-20 ,Advanced Imaging/Communications Signal Processors [Life-time buy]applicationsThe NS32FX164 provides a 16 Mbyte Linear external ad-Ð 18 graphics instructionsdress sp ..
NS32FX164AV-25 ,Advanced Imaging/Communications Signal Processors [Life-time buy]NS32FX161-15/NS32FX161-20/NS32FX164-20/NS32FX164-25/NS32FV16-20/NS32FV16-25AdvancedImaging/Communic ..
NS32FX164AV-25 ,Advanced Imaging/Communications Signal Processors [Life-time buy]Featurestrol functions required for a stand-alone Fax system, a PCadd-in Fax/Voice/Data Modem card ..
OPA2111 ,Dual Low Noise Precision Difet OPERATIONAL AMPLIFIERFEATURES APPLICATIONSl LOW NOISE: 100% Tested, 8nV/√Hz max at l PRECISION INSTRUMENTATION10kHzl DAT ..
OPA2111AM ,Dual Low-Noise Difet® Operational AmplifierFEATURES APPLICATIONSl LOW NOISE: 100% Tested, 8nV/√Hz max at l PRECISION INSTRUMENTATION10kHzl DAT ..
OPA2111BM ,Dual Low-Noise Difet® Operational Amplifier®OPA2111Dual Low Noise Precision®Difet OPERATIONAL AMPLIFIER
OPA2111KM ,Dual Low-Noise Difet® Operational Amplifier®OPA2111Dual Low Noise Precision®Difet OPERATIONAL AMPLIFIER
OPA2111KP ,Dual Low-Noise Difet® Operational AmplifierFEATURES APPLICATIONSl LOW NOISE: 100% Tested, 8nV/√Hz max at l PRECISION INSTRUMENTATION10kHzl DAT ..
OPA211AID ,1.1nV/rtHz Noise, Low-Power, Precision Operational Amplifier 8-SOIC -40 to 125Features... 18 Application and Implementation...... 232 Applications..... 18.1 Application Informat ..
NS32202D-10
1.5 W, 5 V, interrup control unit
National
[ Semiconductor
NS32202MO Interrupt Control Unit
General Description
The NS32202 Interrupt Control Unit (ICU) is the interrupt
controller for the Series 320000 microprocessor family. It is
a support circuit that minimizes the software and real-time
overhead required to handle multi-level. prioritized inter-
rupts. A single N332202 manages up to 16 interrupt sources.
resolvesintenuptpriorities.and suppliesasingIe-byteinterrupt
vector to the CPU.
The N832202 can operate in either of two data bus modes:
16-bit or 8-bit. In the 16-bit mode, eight hardware and eight
software interrupt positions are available. In the 8-bit mode,
16 hardware interrupt positions are available, 8 of which can
be used as software interrupts. In this mode, up to 16 addi-
tional ICUs may be cascaded to handle a maximum of 256
interrupts.
Two 16-bit counters, which may be concatenated under pro-
gram control into a single 32-bit counter, are also available
for real-time applications.
Featu res
n 16 maskable interrupt sources, cascadable to 256
u Programmable 8- or 16-bit data bus mode
a Edge or level triggering for each hardware interrupt with
individually selectable polarities
II 8 software interrupts
a Fixed or rotating priority modes
In Two 16-bit, DC to 10 MHz counters, that may be con-
catenated into a single 32-bit counter
II Optional 8-bit I/O port available in 8-bit data bus mode
I: High-speed XMOSTM technology
a Single, +5V supply
a 40-pin, dual in-line package
Basic System Configuration
Q-- lit
ammo MAS!“
CPU mam:
WU? ICU
NDM-CASUDEO
INIEIIUPT SOURCES
CASCADED t
M32201 e
. CASCADED
t INTEMUPT
SOURCES
cASCADED :
m2”: .
TL/EE/5117-1
OL‘ZOZZSSN
NS32202-10
Table of Contents
1.0 PRODUCT INTRODUCTION 3.0 ARCHITECTURAL DESCRIPTION (Continued)
1.1 I/O Buffers 3.9 FPRT - First Priority Registers (R14, R15)
1.2 Read/Write Logic and Decoders 3.10 MCTL - Mode Control Register (R16)
1.3 Timing and Control 3.11 OSCASN - Output Clock Assignment (R17)
1.4 Priority Control 3.12 CIPTR " Counter Interrupt Pointer Register (R18)
1.5 Counters 3.13 PDAT - Port Dada Register (R19)
3.14 IPS . Interrupt/Port Select Register (R20)
3,15 PDIR - Port Direction Register (R21)
3.16 CCTL - Counter Control Register (R22)
2,2 Initialization 3.17 CICTL - Counter Interrupt Control Register (R23)
2.3 Vectored Interrupt Handling 3.18 LCSV/HCSV - L-Counter Starting Value/H-Counter
2.3.1 Non-Cascaded Operation Starting Value Registers (R24, R25, R28, and R27)
2.3.2 Cascade Operation 3.19 LCCV/HCCV - L-Counter Current Value/H-Counter
Current Value Registers (R28, R29, R30, and R31)
2.4 Internal ICU Operating Sequence
2.5 Interrupt Priority Modes 3.20 Register Initialization
2.0 FUNCTIONAL DESCRIPTION
2.1 Reset
2,5.1 Fixed Priority Mode 4.0 DEVICE SPECIFICATIONS
2.5.2 Auto-Rotata Mode 4.1 NS32202 Pin Descriptions
2.5.3 Special Mask Mode 4.1.1 Power Supply
2.5.4 Polling Mode 4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
3,0 ARCHITECTURAL DESCRIPTION
3.1 HVCT - Hardware Vector Register (R0)
3.2 SVCT - Software Vector Register (RI)
3.3 ELTG - Edge/Level Triggering Registers (R2, R3)
3.4 TPL - Triggering Polarity Registers (R4, R5)
3.5 IPND - Interrupt Pending Registers (R6, R7) 4.4.1 ?t1nitty'.
3.6 ISRV - Interrupt ln-Service Registers (R8, R9) 4.4.1 .1 Tfmfng P"s
3.7 IMSK " Interrupt Mask Registers (R10, R11) 4.4.1.2 Timing Diagrams
3.8 CSRC - Cascaded Source Registers (R12, R13)
List of Illustrations
NS32202 ICU Block Diagram .................................................................................... 1-1
Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values ........................... 1-2
Counter Configuration and Basic Operations ....................................................................... 1-3
Interrupt Control Unit Connections in 16-Bit Bus Mode .............................................................. 2-1
Interrupt Control Unit Connections in 8-Bit Bus Mode ............................................................... 2-2
Cascaded Interrupt Control Unit Connections in B-Bit Bus Mode ...................................................... 2-3
CPU Interrupt Acknowledge Sequence ....lp....l........--l..l.ll....r 2-4
Interrupt Dispatch and Cascade Tables ........................................................................... 2-5
CPU Return from Interrupt Sequence ............................................................................. 2-6
ICU Interrupt Acknowledge Sequence .........l.l......ll..............l..F...... 2-7
ICU Return from Interrupt Sequence .............................................................................. 2-8
ICU Internal Registers .......................................................................................... 3-1
HVCT Register Data Coding ..................................................................................... 3-2
Recommended ICU's Initialization Sequence ...................................................................... 3-3
NS32202 ICU Connection Diagram '_..........-........-........-.-..........-.......... 4-1
Timing Specification Standard -....-......-........-......-......q.-l.p 4-2
READ/ INTA Cycle ............................................................................................. 4-3
Write Cycle T....................-.............................................................................. 4-4
Interrupt Timing in Edge Triggering Mode .......................................................................... 4-5
Interrupt Timing in Level Triggering Mode '.r.r-..l..........ll..P.........l..Pq.... 4-6
External Interrupt-Sampling-Clock to be Provided at Pin COUT/SCIN When in Test Mode ................................ 4-7
Internal lntarrupt-Sampling-Clock to be Provided at Pin COUT/SCIN .................................................. 4-8
Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT/SCIN or G0/R0-G3/R6,
in Both Pulsed Form and Square Waveform ....................................................................... 4-9
1.0 Product Introduction
The NS32202 ICU functions as an overall manager in an
interrupt-oriented system environment. Its many features
and options permit the design of sophisticated interrupt sys-
Figure t--t shows the internal organization of the NS32202.
As shown, the NS32202 is divided Into five functional
blocks. These are described in the following paragraphs:
1.1 vo BUFFERS AND LATCHES
The I/O Buffers and Latches block is the interface with the
system data bus. It contains bidirectional buffers for the
data I/O pins. It also contains registers and logic circuits
that control the operation of pins G0/lR0,...,G7/lR14
when the ICU is in the 8-bit bus mode.
1.2 READ/WRITE LOGIC AND DECODERS
The Read/Write Logic and Decoders manage all internal
and external data transfers for the ICU. These include Data,
Control, and Status Transfers. This circuit accepts inputs
from the CPU address and control buses. In turn. it issues
commands to access the internal registers of the ICU.
1.3 TIMING AND CONTROL
The Timing and Control Block contains status elements that
select the ICU operating mode. It also contains state ma-
chines that generate all the necessary sequencing and con-
trol signals.
67/ IR“
66/1111?
BSIIMO
tit/ou
81/132
MIIIO AND
tn LATCH“
" 0 BUFFER
1.4 PRIORITY CONTROL
The Priority Control Block contains 16 units, one for each
interrupt position. These units provide the following tune-
tions.
. Sensing the venous forms of hardware interrupt sig-
nals 6.9. level (high/low) or edge (rising/falling)
. Resolving priorities and generating an interrupt re-
quest to the CPU
. Handling cascaded arrangements
0 Enabling software interrupts
0 Providing for an automatic return from interrupt
. Enabling the assignment of any interrupt position to
the internal counters
. Providing for rearrangement of priorities by assigning
the first priority to any interrupt position
. Enabling automatic rotation of priorities
1.5 COUNTERS
This block contains two ltr-bit counters. called the H-coun-
ter and the L-counter. These are down counters that count
from an initial value to zero. Both counters have a 16-bit
register (designated HCSV and LCSV) for loading their re-
starting values. They also have registers containing the cur-
rent count values (HCCV and LCCV). Both sets of registers
are fully described in Section 3.
IE! Ills tit? II! tttM lltt3 M15
MINI"! LOGIC
AND DEWDEM
M. At " " "
TL/EE/5117-2
FIGURE 1-1. NS32202 ICU Block Diagram
OL'ZOZZSSN
NS32202-10
1.0 Product Introduction (Continued)
The counters are under program control and can be used to
generate interrupts. When the count reaches zero, either
counter can generate an interrupt request to any of the 16
interrupt positions. The counter then teioeds the start value
from the appropriate registers and resumes counting. Figure
1-2 shows typical counter output signals available from the
NS32202.
The maximum input clock frequency is 2.5 MHz.
A divide-by-four prescaler is also provided. When the pre-
scaler is used, the input ctock frequency can be up to 10
When intervals longer than provided by a 16-bit counter are
needed, the L- and H-countere can be concatenated to form
a 32-bit counter. In this case, both counters are controlled
by the H-counter control bits. Refer to the discussion of the
Counter Control Register in Section 3 for additional infoma-
tion. Figure 1-3 summarizes counter read/write operations.
2.0 Functional Descriptlon
2.1 RESET
The ICU is reset when a logic low signal is present on the
HST pin. At reset, most internal ICU registers are affected.
and the ICU becomes inactive.
2.2 INITIALIZATION
After reset, the CPU must initialize the NS32202 to estabtish
its configuration. Proper initialization requires knowledge ot
the ICU register's formats. Therefore, a tlowtthart of e rec-
ommended initialization sequence is shown in (Figure 3-3)
after the discussion of the ICU registers.
The operation sequence shown in Figure 3-3 ensures that
all counter output pins remain inactive until the counters are
completely initialized.
2.3 VECTORED INTERRUPT HANDLING
For details on the operation of the vectored interrupt mode
for a particular Series 32000 CPU, refer to the data sheet for
ttttItem
mam t 1
(m. VALUE-I)‘
PUMPKIN
f) i--
COUNTER
W8 1, 0
(NH. VALUE I: "
0 1 0 I
OUTPUT"!
(NT. m-n)
rd1'l'1llll, J
TUEE/5117-4
FIGURE 1-2. Counter Output Signals In Pulsed Form and Square Waveform for Three Different Initial Value:
2.0 Functional Description (Continued)
that CPU. In this discussion. it is assumed that the NS32202
is working with a CPU in the vectored interrupt mode. Sever-
al ICU applications are discussed, including non-cascaded
and cascaded operation. Figures JV f, 2-2, and 2-3 show
typical configurations of the ICU used with the N832016
A peripheral device issues an interrupt request by sending
the proper signal to one of the NS32202 interrupt inputs. If
the interrupt input is not masked, the ICU activates its Inter-
rupt Output (NT) pin and generates an interrupt vector byte,
The interrupt vector byte identifies the interrupt source in its
four least significant bits. When the CPU detects a low level
on its Interrupt Input pin, it performs one or two interrupt
acknowledge cycles depending on whether the interrupt re-
quest is from the master iCU or a cascaded ICU. Figure 2-4
shows a flowchart of a typical CPU Interrupt Acknowledge
sequence.
STAETING VALUE g:
ulWnltlml
ZERO DETECT E
comma " it
mm couman mamas l g
CURRENT VALUE A A
LCCV/HCCV
TL/EE/5117-5
BASIC OPERATIONS:
WRITING TO LCSV/HCSV - (IDB)
READING LCSV/HCSV _ (IDB)
WRITING TO LCCV/HCCV - (IDB)
(only possible when counters are halted) _ (IDB)
READING LCCV/HCCV - (IDB)
(only possible when counter
readings are frozen)
COUNTER COUNTS AND READINGS ARE
NOT FROZEN -
COUNTER RELOADS STARTING VALUE -
(occurs on the clock cycle following
the one in which it reaches zero)
FIGURE 1-3. Counter Configuration and Basic Operations
OL'ZOZZSSN
N832202-10
2.0 Functional Description (Continued)
m-m mu;
uncu All-M M-M
mam k RTE Ilttr+--.
AT! 323%: ' Ft mr4-
8t1 = ttt um -
'git ' ird
mm: m -
t5t5itt mu
Iurm tttrw-
m'm5 no-m_ it/Ill, I
m1 Mt Ill -
f ‘L l m
mu ml: m W 55 'll
tell Mr [ Mi m -
tn-ths
FIGURE 2- l. Interrupt Control Unlt Connectlono In 16-Blt Bus Mode
NOTE: In the B-Bit Bus Mode the Master ICU Registers appear at even
addresses (A0 =0) since the ICU communicates with the least sig-
nificant byte of the CPU data bus.
A1041! T,'.'-- = Ao-m
wen w-" amm H
"320t' " tNo--. m mm: H
cm tt8nR10_
W t'l1li'g', t Ft sum -
m t ttt cum H
if Q riii mm: H
mm: mxmmH
W "ttrf--
WFFEI WW i mu -
m-mu f - com llttrq-
nm mu m -
t f " " l' h
run rm: R “i Ei I
"3t20t - I?.. m .-
mu m m m -
FIGURE 2-2. Interrupt Control Unlt Connections In IVBit Bus Mode
TL/EE/5117-6
TL/EE/5117-7
2.0 Functional Description (Continued)
tttr-to
nu mu m m E
tell m
FIGURE 2-3. Cascaded Interrupt Control Unit Connections In B-Blt Bus Mode
W ammo
et" women W'"
:11 mm: was
tt3/te8
mmn 3mm
N53220: ml“
TL/EE/5117-8
OL'ZOZZSSN
NS32202-10
2.0 Functional Description (Continued)
. Cond. A is true if current instruction is terminated
or an interruptible point in a string instruction is
reached.
SUSPEND
INSTRUCTION EXECUTION
DISABLE INTERRUPI' S
EXECUTE MASTER INTA
CYCLE AND READ VECTOR
FROM ADDRESS FFFEUhc
OBTAIN CASCADE ICU ADDRESS
FROM CASCADE TABLE
HECUTE CASCADE!) INTA
CYCLE AND READ VEC'IOR
FRO“ CASCADE) ICU
OBTAIN EXTERNAL PROCEDURE
DESCRIPTOR FROM
INTERN" DISI‘AYCH TABLE
OBTAIN SERVICE ROUTINE
ENTRY POINT
SAVE 9806M“ 000m.
MOD REGISTER Alto
CPU STATUS DH
INTERRUPT STADK
RESUME INSYRUCTIM
HECU'HON AT SERVICE
ROUTWE ENTRY POINT
FIGURE 2-4. CPU Interrupt Acknowledge Sequence
TC/EE/5117-9
2.0 Functional Description (Continued)
In general, vectored interrupts are serviced by interrupt rou-
tines stored in system memory. The Dispatch Table stores
up to 256 external procedure descriptors for the various
service procedures. The CPU INTBASE register points to
the top of the Dispatch Table. Figure 2-5 shows the layout
of the Dispatch Table. This figure also shows the layout of
the Cascade Table, which is discussed with ICU cascaded
operation.
2.3.1 tlttttAtattttaded Operation. Whenever an interrupt re-
quest from a peripheral device is issued directly to the mas-
ter ICU, a non-cascaded interrupt request to the CPU re-
sults. In a system using a single NS32202, up to 16 interrupt
requests can be prioritized. Upon receipt of an interrupt re-
quest on the W" pin, the CPU performs a Master Interrupt-
Acknowledge bus cycle, reading a vector byte from address
FFFE0016. This vector is then used as an index into the
dispatch table in order to find the External Procedure De-
scriptor tor the proper interrupt service procedure. The serv-
ice procedure eventually returns via the Return-trom-Inter-
rupt (RET) instruction, which performs a Return-trom-Inter-
rupt bus cycle, informing the ICU that it may re-prioritize any
interrupt requests still pending. Figure 2-6 shows a typical
CPU RETI sequence. In a system with only one ICU, the
vectors provided must be in the range of 0 through 127; this
can be ensured by writing OXXXXXXX into the SVCT regis-
2.3.2 Cascaded Operation. In cascaded operation, one or
more of the interrupt inputs of the master ICU are connect-
ed to the Interrupt Output pin of one or more cascaded
lCUs. Up to 16 cascaded lCUs may be used, giving a sys-
tem total of 256 interrupts.
Note: The number of cascaded ICUs is practically limited to 15 because the
Dispatch Table tor the NS32016 CPU is constructed with entries 1
through 15 either used for NMI and Trap descriptors. or reserved for
future use. Interrupt position 0 of the master ICU should not be cas-
caded, so it can be vectored through Dispatch Table entry o, reserved
tor non-vectored interrupts. In this case. the nttrVvttctorttd interrupt
entry (entry 0) is also available for vectored interrupt operation, since
the CPU is operating in the vectored interrupt mode.
The address of the master ICU should be FFFE0015. C)
Cascaded ICUs can be located at any system address. A list
of cascaded ICU addresses is maintained in the Cascade
Table as a series of sixteen 32-bit entries.
ONottt.. The CPU status corresponding to both, master interrupt acknowl-
edge and return trom interrupt bus cycles, as well as address bit
A8, could be used to generate the chip select (CS) signal for ac-
cessing the master ICU during one of the above cycles. In this case
the master tCU can reside at any system address. The oniy limita-
tion is that the least significant 5 or 6 address bits (6 in the 8-bit bus
mode) must be zero. The address bit A8 must be decoded to pre-
vent an NMI bus cycle from reading the hardware vector register of
the ICU. This could happen. since the NS32016 CPU performs a
dummy read cycle from address FFFFoow. with the same status
as a master INTA cycle, when a nort-rnaskable-interrupt is acknowl-
ter. By providing a negative vector value, the master ICU edged“
flags the interrupt source as a cascaded ICU (see below).
amonv r
mas: masses ARE
use: at m: cm bums
(WW uscwen [cu ADDRIS a m: seem cm: as
m nm on mi
SEQUENCE m an m:
imam vmon mu
mm: mm h cascm Ko.
ChStM@ttlJltgIhtESS" ___?___-
IrlTBME-" CA3 menu: iNDEX
INTBASE ChStNEtHtlllAthh1ESSt5 (__i_L__.__I)_
asusmt rm DESCRIPTOR
um um mp
oescmmas'
nzsewsn'
(mmssuo vscmn)
m. nsscnmon 18
nismcn mt:
moescmmnn _------'--------
mt. nescmma 255
(m; FrTBhhio-- "ASTER IN'8 ----- CPU READS THIS Lawton thmltlit
mm nausea aim cm: or nm on am
sequence To an amen
THE 1mm?! VECTOR OR
A W TABLE INDEX HIGH
THE IASTEI ICU.
. Table entries 1 to 15 should not be used by the ICU since they contain NMI and Trap Descriptors
or are reserved for future use. (For more details refer to NS32016 data sheet.)
FIGURE 2-5. Interrupt Dispatch and Cascade Tables
TL/EE/5117-10
0 l'ZOZZSSN
NS32202-10
2.0 Functional Description (Continued)
CiiiEiD
EXECUTE MASTER RE" CYCLE
AND READ VECTOR
FROM ADDRESS FFFEOOII
OBTAIN mews!) Itll)
ADDRESS FROM CASCADE
EXECUTE CASCADE!)
leo CYCLE 'tlo READ
VECTOR FROM
CASCADED 100
DiSCARD VECTOR
RESTORE CPU STATUS.
M00 REGISTER AND
RETURN ADDRESS FRO"
INTERRUPT STACK
RESUME INSTRUCTION
EXEBUTION AT
RESTORE!) ADDRESS
TL/EE/51t7-11
FIGURE 2-6. CPU Return from Interrupt Sequence
The master ICU maintains a list (in the CSRC register pair)
of its interrupt positions that are cascaded. It also provides a
4-bit (hidden) counter (in-service counter) for each interrupt
position to keep track of the number of interrupts being
serviced in the cascade ICUs. When a cascaded interrupt
input is active. the master ICU activates its interrupt output
and the CPU responds with a Master Interrupt Acknowledge
Cycle. However, instead of generating a positive interrupt
vector, the master cu generates a negative Cascade Table
index.
The CPU interprets the negative number returned from the
master ICU as an index into the Cascade Table. The Cas-
cade Table is located in a negative direction from the Dis.
patch Table, and it contains the virtual addresses of the
hardware vector registers for any cascaded NS32202s in
the system. Thus, the Cascade Table index supplied by the
master ICU identifies the cascaded cu that requested the
interrupt.
Once the cascaded ICU is identified, the CPU performs a
Cascaded Interrupt Acknowledge cycle. During this cycle,
the CPU reads the final vector value directly from the cas-
caded ICU, and uses it to access the Dispatch Table. Each
cascaded ICU, of course, has its own set of 16 unique inter-
rupt vectors, one vector for each of its 16 interrupt positions.
The CPU interprets the vector value mad during a Cascad-
ed Interrupt Acknowledge cycle as an unsigned number.
Thus, this vector can be in the range 0 through 255.
When a cascaded interrupt service routine completes its
task, it must return control to the interrupted program with
the same RETI instruction used in non-cascaded interrupt
service routines. However, when the CPU performs a Mas.
ter Return From Interrupt cycle, the CPU accesses the mas-
ter ICU and reads the negative Cascade Table index identi-
tying the cascaded cu that originally received the interrupt
request. Using the cascaded ICU address, the CPU now
performs a Cascaded Return From Interrupt cycle, informing
the cascaded ICU that the service routine is over. The byte
provided by the cascaded ICI.) during this cycle is ignored.
2.4 INTERNAL ICU OPERATING SEQUENCE
The NS32202 ICU accepts two interrupt types, software and
hardware.
Software interrupts are initiated when the CPU sets the
proper bit in the Interrupt Pending (IPND) registers (R6, R7),
located in the ICU. Bits are set and reset by writing the
proper byte to either R6 or R7. Software interrupts can be
masked, by setting the proper bit in the mask registers (RIO,
Hardware interrupts can be either internal or external to the
ICU. Internal ICU hardware interrupts are initiated by the on-
chip counter outputs. External hardware interrupts are initia-
ted by devices external to the ICU, that are connected to
any of the ICU interrupt input pins.
Hardware interrupts can be masked by setting the proper bit
in the mask registers (R10, R11). It the Freeze bit (FRZ),
located in the Mode Control Register (MCTL), is set, all in-
coming hardware interrupts are inhibited from setting their
corresponding bits in the IPND registers. This prevents the
ICU from recognizing any hardware interrupts.
Once the ICU is initialized, it is enabled to accept interrupts.
If an active interrupt is not masked, and has a higher priority
than any interrupt currently being serviced, the ICU acti-
vates its Interrupt Output (TNT). Figure 2-7 is a flowchart
showing the ICU interrupt acknowledge sequence.
The CPU responds to the active WT line by performing an
Interrupt Acknowledge bus cycle. During this cycle, the ICU
clears the IPND bit corresponding to the active interrupt po-
sition and sets the corresponding bit in the Interrupt ln-Serv-
ice Registers (ISRV). The 4-bit in-service counter in the
master ICU is also incremented by one if the fixed priority
mode is selected and the interrupt is from a cascaded ICU.
The ISRV bit remains set until the CPU performs a RETI bus
cycle and the 4-bit in-service counter is decremented to
zero. Figure 2-6 is a flowchart showing ICU operation dur-
ing a RETI bus cycle.
When the ISRV bit is set. the W output is disabled. This
output remains inactive until a higher priority interrupt posi-
tion becomes active, or the ISRV bit is cleared.
An exception to the above occurs in the master ICU when
the fixed priority mode is selected, and the interrupt input is
connected to the W output of a cascaded ICU. In this case
the ISRV bit does not inhibit an interrupt of the same priority.
This is to allow nesting of interrupts in a cascaded ICU.
2.0 Functional Description (Continued)
l MTuuUTot l .
ANY UNNMD
PENDING?
nltlmtjuN
INTERN" IEOUW
"IVICIM
m m mm
At m ACTIVE
l! ACKNOWLEDGE
INTA HIGH!" Monty
CVCLE KIWI"
(XECUTED? I
A881“ HI" PRIORITY
TO COMIWIDINO
INTEIIUH POSITION
ACKNOWLEDGE
NWNEIT 'ftoiltt
REDUIIT
INTERN"
IMMIUH
00TH." mmmm
VECTOI (”IIWW)
tht DATA '08
JNCREMENI
lN-SERVICE
COUNTER
. Cond. B is true it any one of the following condi-
ttt '3“ NT tions is satisfied.
RESET mm In . . .
ter Rt INACTIVE I) No Interrupt is being serviced
2) There is a pending unmasked interrupt with
priority higher than that of the interrupt being
servicad.
3) There is a pending unmasked interrupt from a
cascaded ICU with priority higher or same " that
of the highest priority interrupt position in the
" master ICU with the ISRV bit Bat.
OUTPUT mm: TAIL!
mu "tttWW)
tht mu IUI
TL/EEm117-t2
FIGURE 2-7. ICU Interrupt Acknowledge Sequence
0 l'ZOZZSSN
NS32202-10
2.0 Functional Description (Continued)
OUTPUT
CASCADE there
INIEHRUP'T
BEING SERVICE!)
FROM A
CASCADED "
OUTPUT
INTERRU"
VECYOR
INTERRUH ISRV MT
AND ASSIGN FIRSY
mom" TO NEXT
INTERRUFT POSIYION
AUTOROTATE
SELECTED?
"tm180Pt
BEING SERVlCED
FROM A
CASCADE!)
DECHEMENT
IN-SERVICE
COUNTER
lN-SERVICE
COUNTER
(NIERRUPY
ISRV ttlt
TL/EE/5117-13
FIGURE 2-8. ICU Return from Interrupt Sequence
2.0 Functional Description (Continued)
2.5 INTERRUPT PRIORITY MODES
The NS32202 ICU can operate in one of four interrupt priori-
ty modes: Fixed Priority; Auto-Rotate; Special Mask; and
Polling. Each mode is described below.
2.5.1 Fixed Prlorlty Mode
In the Fixed Priority Mode (also called Fully Nested Mode),
each interrupt position is ranked in priority from 0 to 15, with
o being the highest priority. In this mode, the processing of
lower priority interrupts is nested with higher priority inter-
rupts. Thus, while an interrupt is being serviced, any other
interrupts of the same or lower priority are inhibited. The ICU
does, however, recognize higher priority interrupt requests.
When the interrupt service routine executes its RETI instruc-
tion, the corresponding ISRV bit is cleared. This allows any
lower priority interrupt request to be serviced by the CPU.
At reset, the default priority assignment gives interrupt IRO
priority 0 (highest priority), interrupt IRI priority 1, and so
forth. Interrupt IR15 is, of course. assigned priority 15, the
lowest priority. The default priority assignment can be al-
tered by writing an appropriate value into register FPRT (L)
as explained in Section 3.9.
Note: When the lCU generates an interrupt request to the CPU for a higher
priority interrupt while a lower priority interrupt is still being serviced by
the CPU, the CPU responds to the interrupt request only it its internal
interrupt enable ttag is set. Normally, this flag is reset at the beginning
of an interrupt acknowledge cycle and set during the RETI cycle. It the
CPU is to respond to higher priority interrupts during any interrupt
service routine, the service routine must set the internal CPU interrupt
enable flag, as soon during the service routine as desired.
2.5.2 Auto-Rotate Mode
The Auto Rotate Mode is selected when the NTAR bit is set
to o, and is automatically entered after Reset. In this mode
an interrupt source position is automatically assigned lowest
priority after a request at that position has been serviced.
Highest priority then passes to the next lower priority posi-
tion. For example, when servicing of the interrupt request at
position 3 is completed (ISRV bit 3 is cleared), interrupt po-
sition 3 is assigned lowest priority and position 4 assumes
highest priority. The nesting ot interrupts is inhibited, since
the interrupt being serviced always has the highest priority.
This mode is used when the interrupting devices have to be
assigned equal priority. A device requesting an interrupt, will
have to wait, in the worst case, until each of the 15 other
devices has been serviced at most once.
2.5.3 Special Mask Mode
The Special Mask Mode is used when it is necessary to
dynamically alter the ICU priority structure while an interrupt
is being serviced. For example, it may be desired in a partie-
ular interrupt service routine to enable lower priority inter-
rupts during a part of the routine. To do so, the ICU must be
programmed in fixed priority mode and the interrupt service
routine must control its own in-service bit in the ISRV regis-
The bits of the ISRV registers are changed with either the
Set Bit Interlocked or Clear Bit Interlocked instructions (SBI-
TIW or CBITlW). The in-service bit is cleared to enable low-
er priority interrupts and set to disable them.
Note: For proper operation of the ICU, an interrupt service routine must set
its ISRV bit before executing the RETI instruction. This prevents the
RET I cycle trom clearing the wrong ISRV bit.
2.5.4 Polling Mode
The Polling Mode gives complete control of interrupt priority
to the system software. Either some or all of the interrupt
positions can be assigned to the polling mode. To assign all
interrupt positions to the polling mode, the CPU interrupt
enable flag is reset. To assign only some of the interrupt
positions to the polling mode, the desired interrupt positions
are masked in the Interrupt Mask registers (IMSK). In either
case, the polling operation consists of reading the Interrupt
Pending (IPND) registers.
If necessary, the IPND read can be synchronized by setting
the Freeze (FRZ) bit in the Mode Control register (MCTL).
This prevents any change in the IPND registers during the
read. The FRZ bit must be reset after the polling operation
so the lPND contents can be updated. If an edge-triggered
interrupt occurs while the IPND registers are frozen, the in-
terrupt request is latched, and transferred to the IPND regis-
ters as soon as FRZ is reset.
The polling mode is useful when a single routine is used to
service several interrupt levels.
3.0 Architectural Description
The NS32202 has thirty-two 8-bit registers that can be ac-
cessed either individually or in pairs. In 16-bit data bus
mode, register pairs can be accessed with the CPU word or
double-word reference instructions. Figure 3-1 shows the
ICU internal registers. This figure summarizes the name,
function, and offset address for each register.
Because some registers hold similar data, they are grouped
into functional pairs and assigned a single name. However,
if a single register in a pair is referenced, either an L or an H
is appended to the register name. The letters are placed in
parentheses and stand for the low order 8 bits (L) and the
high order 8 bits (H). For example. register R6, part of the
Interrupt Pending (IPND) register pair, is referred to individu-
ally es lPND(L).
The following paragraphs give detailed descriptions of the
registers shown in Figure 3-1.
3.1 HVCT- HARDWARE VECTOR REGISTER (R0)
The HVCT register is a single register that contains the in-
terrupt vector byte supplied to the CPU during an Interrupt
Acknowledge (INTA) or Return From Interrupt (RETI) cycle.
The HVCT bit map is shown below:
7 6 5 3 2
[BlBlBngVIV
OL'ZOZZSSN
NS32202-10
3.0 Architectural Description (Continued)
REG. NUMBER AND REG. REG. FUNCTION
ADDRESS IN HEX. NAME
R0(0016) HVCT-.- HARDWARE VECTOR
R1 (0116) SVCT - SOFTWARE VECTOR
R2 (0216) ELTG - EDGE/LEVEL TRIGGERING
n5(0516) n4(o416) TPL-. TRIGGEHINGPOLARITY
R7(071s) R6(0616) IPND-. INTERRUPTSPENDING
R9 (0916) R8 (0816) ISRV - INTERRUPTS IN-SERVICE
muoaw) momma) B/SK-- INTERRUPTMASK
R13 (0015) R12 (0015) CSRC - CASCADED SOURCE
R15 (0Fus) R14 (0516) FPRT - FIRST PRIORITY
R16 (1016) MCTL - MODE CONTROL
R17 (1116) OCASN - OUTPUT CLOCK ASSIGNMENT
me (1216) CIPTR - COUNTER INTERRUPT POINTER
R19 (1316) PDAT- PORT DATA
R20 (1415) IPS - INTERRUPT/PORT SELECT
R21 (1516) PDIR - PORT DIRECTION
R22 (1616) CCTL - COUNTER CONTROL
R23 (1716) CICTL - COUNTER INTERRUPT CONTROL
R25 (1915) R24 (1816) LCSV - L-COUNTER STARTING VALUE
R27 (1 Bus)
R26 (1A15) HCSV - H-COUNTER STARTING VALUE
R29 (1 the) R28 (1 the) LCCV - L-COUNTER CURRENT VALUE
R31(1F16) R30(1E1e) HCCV-. H-COUNTERCURRENTVALUE
FIGURE 3-1. ICU Internal Reglsiers
3.0 Architectural Description (Continued)
The BBBB field is the bias which is programmed by writing
BBBBOOOOg to the SVCT register (R1). The VVVV field iden-
tifies one of the 16 interrupt positions. The contents of the
HVCT register provide various information to the CPU, as
shown in Figure 3-2
Note It The ICU always interprets a read of the HVCT register as either an
INTA or RETI cycle. Since these cycles cause internal changes to
the ICU, normal programs must never read the ICU HVCT register.
Note 2: It the HVCT register is read with ST1 = 0 (INTA cycle) and no
unmasked interrupt is pending, the binary value BBBB1111 is re-
turned and any pending edge-triggered interrupt in position 15 is
cleared.
It the auto-rotate priority mode is selected, the FPRT register is also
cleared, thus preventing any interrupt from being acknowledged. In
this case a reintialization of the FPRT register is required for the
ICU to acknowledge interrupts again.
It a read of the HVCT register is performed with ST1 = 1 (RETI
cycle). the binary value BBBBI l 11 is returned,
If the auto-rotate mode is selected, a priority rotation is also per-
formed.
3.2 SVCT - SOFTWARE VECTOR REGISTER (R1)
The SVCT register is a copy of the HVCT register. it allows
the programmer to read the contents of the HVCT register
without initiating a INTA or RETI cycle in the ICU. It also
allows a programmer to change the BBBB field of the HVCT
register. The bit map of the SVCT register is the same as for
the HVCT register.
During a write to SVCT, the four least significant bits are
unaffected while the tour most significant bits are written
into both SVCT and HVCT (R1 and R0).
The SVCT register is updated dynamically by the ICU. The
tour least significant bits always contain the vector value
that would be returned to the CPU if a INTA or RETl cycle
were executed. Therefore, when reading the SVCT register,
the state of the CPU ST1 pin is used to select either pend-
ing interrupt data or in-service interrupt data. For example, if
the SVCT register is read with ST1 = 0 (as for an INTA
cycle), the VWV field contains the encoded value of the
highest priority pending interrupt. On the other hand, if the
SVCT register is read with ST1 = 1, the WW field contains
the encoded value of the highest priority in-service interrupt.
Note: If the CPU ST1 output is connected directly to the ICU ST1 input, the
vector read from SVCT is always the RETI vector. If both the INTA
and RETI vectors are desired, additional logic must be added to drive
the ICU ST1 input. A typical circuit is shown below. In this circuit. the
state of the ICU ST1 input is controlled by both the CPU STI output
and the selected address bit.
cm I MOR " 100
TL/EE/5117-14
3.3 ELTG - EDGE/LEVEL TRIGGERING
REGISTERS (R2, R3)
The ELTG registers determine the input trigger mode for
each of the 16 interrupt inputs. Each input is assigned a bit
in this register pair. An interrupt input is leveI-triggered if its
bit in ELTG is set to 1. The input is edge-triggered if its bit is
cleared. At reset, all bits in ELTG are set to I.
If odd-numbered interrupt positions must be used for soft-
ware interrupts, the edge triggering mode must be selected
and the corresponding interrupt inputs should be prevented
from changing state.
3.4 TPL - TRIGGERING POLARITY
REGISTERS (R4, RS)
The TPL registers determine the polarity of either the active
level or the active edge for each of the 16 interrupt inputs.
As with the ELTG registers, each input is assigned a bit.
Possible triggering modes for the various combinations of
ELTG and TPL bits are shown below.
ELTG BIT TPL BIT TRIGGERING MODE
0 0 Falling Edge
0 1 Rising Edge
1 0 Low Level
1 1 High Level
Software interrupt positions are not affected by their TPL
bits. At reset, all TPL bits are set to 0.
Note 1: If tsdgtsd-triggertrd interrupts are to be handled, the TPL register
should be programmed before the ELTG register.
This prevents spurious interrupt requests from being generated dur-
ing the ICU initialization from trdgertriggererd interrupt positions.
Note 2: Hardware interrupt inputs connected to cascaded ICUs must have
their TPL Bits set to th
3.5 IPND - INTERRUPT PENDING REGISTERS (R6, R7)
The IPND registers track interrupt requests that are pending
but not yet serviced. Each interrupt position is assigned a bit
in lPND. When an interrupt is pending, the corresponding bit
in IPND is set. The lPND data are used by the ICU to gener-
ate interrupts to the CPU. These data are also used in poll-
ing operations.
INTA CYCLE (ST1 = 0)
RETICYCLEiST1--=t)
Highest priority pending interrupt is from:
Highest priority in-service interrupt was from:
BBBB cascaded ICU any other source cascaded ICU any other source
1111 programmed bias' 1111 programmed bias'
WW encoded value of the highest encoded value of the highest
priority pending interrupt
priority in-service interrupt
'The Programmed bias for the master ICU must range trom 0000 to 01112 because the CPU interprets a one in the most significant bit position as a Cascade Table
Index indicator for a cascaded ICU.
FIGURE 3-2. HVCT Register Data Codlng
OL'ZOZZSSN
N 332202-1 0
3.0 Architectural Description (Continued)
The IPND registers are also used for requesting software
interrupts. This is done by writing specially formatted data
bytes to either IPND(L) or IPND(H). The formats differ for
registers R6 and R7. These formats are shown below:
IPND(L) (R6) - SOOOOPPP
|PND(H) (R7) - S0001 PPP
Where: s = Set (S = 1) or Clear (S = 0)
PPP = is a binary number identifying one of
eight bits
Note: The data read from either R6 or R7 are different from that written to
the register because the ICU returns the register contents. rather than
the formatted byte used to set the register bits.
The ICU automatically clears a set IPND bit when the pend-
ing interrupt request is serviced. All pending interrupts in a
register can be cleared by writing the pattern 'XIXXXXXX'
to it (X = don't care). To avoid conflicts with asynchronous
hardware interrupt requests, the IPND registers should be
frozen before pending interrupts are cleared. Refer to the
Mode Control Register description for details on freezing
the IPND registers.
At reset, all IPND bits are set to 0.
Note: The edge sensing mechanism used for hardware interrupts in the
NS32202 ICU is a latching device that can be cleared only by ac-
knowledging the interrupt or by changing the trigger mode to level
sensing. Therefore, before clearing pending interrupts in the IPND
registers, any edge-triggered interrupt inputs must first be switched to
the IeveI-triggered mode, TNs clears the edge-triggered interrupts;
the remaining interrupts can then be cleared in the manner described
above. This applies to clearing the interrupts only. Edgertriggered in-
terrupts can be set without changing the trigger mode.
3.6 ISRV- INTERRUPT lN-SERVICE
REGISTERS (R8, R9)
The ISRV registers track interrupt requests that are current-
ly being serviced. Each interrupt position is assigned a bit in
ISRV. When an interrupt request is serviced by the ICU, its
corresponding bit is set in the ISRV registers. Before gener-
ating an interrupt to the CPU, the ICU checks the ISRV reg-
isters to ensure that no higher priority interrupt is currently
being serviced.
Each time the CPU executes an RETI instruction, the ICU
clears the ISRV bit corresponding to the highest priority in-
terrupt in service. The ISRV registers can also be written
into by the CPU. This is done to implement the special mask
priority mode.
At reset, the SRV registers are set to 0.
Note: It the ICU initialization does not follow a hardware reset. the ISRV
register should be cleared during initialization by writing zeroes into it.
3.7 IMSK - INTERRUPT MASK REGISTERS (R10, R11)
Each NS32202 interrupt position can be individually
masked. A masked interrupt source is not acknowledged by
the ICU. The lMSK registers store a mask bit for each of the
ICU interrupt positions. It an interrupt position's IMSK bit is
set to 1, the position is masked.
The IMSK registers are controlled by the system software.
At reset, all IMSK bits are set to I, disabling all interrupts.
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit in the IMSK register. However, if an interrupt is set
pending during the CPU instruction that masks off that interrupt. the
CPU may still perform an interrupt acknowledge cycle following that
instruction since it might have sampled the WT line before the ICU
deasserted it. This could cause the ICU to provide an invalid vector.
To avoid this problem, the above operation should be performed with
the CPU interrupt disabled.
3.8 CSRC - CASCADED SOURCE
REGISTERS (R12, R13)
The CSRC registers track any cascaded interrupt positions.
Each interrupt position is assigned a bit in the CSRC regis-
ters. If an interrupt position's CSRC bit is set, that position is
connected to the It7T- output of another NS32202 ICU, im., it
is a cascaded interrupt.
At reset, the CSRC registers are set to 0.
Note 1: It any cascaded ICU is used, the CSRC register should be cleared
during initialization (if the initialization does not follow a hardware
reset) by writing zeroes into it. This should be done before setting
the bits corresponding to the cascaded interrupt positions. This op-
eration ensures that the 4-bit in-service counters (associated with
each interrupt position to keep track of cascaded interrupts) always
get cleared when the ICU is re-initialized.
Note 2: Only the Master ICU should have any CSRC bits set. If CSRC bits
are set in a cascaded ICU, incorrect operation results.
3.9 FPRT - FIRST PRIORITY REGISTERS (R14, R15)
The FPRT registers track the ICU interrupt position that cur-
rently holds first priority. Only one bit of the FPRT registers
is set at one time. The set bit indicates the interrupt position
with first (highest) priority.
The FPRT registers are automatically updated when the ICU
is in the auto-rotate mode. The first priority interrupt can be
determined by reading the FPRT registers. This operation
returns a 16-bit word with only one bit set. An interrupt posi-
tion can be assigned first priority by writing a formatted data
byte to the FPRT(L) register. The format is shown below:
7 6 5 4 3 2 1 0
xixlxlFlFlFlFl
Where:XXXX=
Don't Care
A binary number from 0 to 15 indi-
cating the interrupt position as-
signed first priority.
Note: The byte above is written only to the FPRTiL) register. Any data writ-
ten to FPRT(H) is ignored.
At reset the FFFF field is set to o, thus giving interrupt posi-
tion 0 first priority.
3.10 MCTL - MODE CONTROL REGISTER (R16)
The contents of the MCTL set the operating mode of the
NS32202 ICU. The MCTL bit map is shown below.
7 6 5 4 3 2 l 0
lcrnzicoUTiicouTMlcLKMlFrdVnusediNTAriT1tsNti
3.0 Architectural Description (Continued)
CFFtZ Determines whether or not the N832202 coun-
ter readings are frozen. When frozen, the
counters continue counting but the LCCV and
HCCV registers are not updated. Reading of
the true value of LCCV and HCCV is possible
only while they are frozen.
CFRZ = 0 = > LCCV and HCCV Not Frozen
CFRZ = 1 = > LCCV and HCCV Frozen
Determines whether the COUT/SCIN pin is an
input or an output. COUT/SCIN should be
used as an input only for testing purposes. In
this case an external sampling clock must be
provided otherwise hardware interrupts will not
be recognized.
COUTD = 0 = > COUT/SCIN is Output
COUTD = 1 = > COUT/SCIN is Input
When the COUT/SCIN pin is programmed as
an output (COUTD=0), this bit determines
whether the output signal is in pulsed form or in
square wave form.
COUTM = o = > Square Wave Form
COUTM = 1 => Pulsed Form
Used only in the 8-bit Bus Mode. This bit con-
trols the clock wave form on any of the pins
GO/lFtO, . . . ,GS/IR6 programmed as counter
output.
CLKM = O = > Square Wave Form
CLKM 1 => Pulsed Form
Freeze Bit. in order to allow a synchronous
reading of the interrupt pending registers
(IPND), their status may be frozen, causing the
ICU to ignore incoming requests. This is of spe-
cial importance if a polling method is used.
FRZ = 0 = > IPND Not Frozen
FRZ = 1 => IPND Frozen
Determines whether the lCU is in the AUTO-
ROTATE or FIXED Priority Mode. In AUTO-
ROTATE mode, the interrupt source at the
highest priority position, after being serviced, is
assigned automatically lowest priority. In this
mode, the interrupt in service always has high-
est priority and nesting of interrupts is therefore
inhibited.
NTAR = 0 = > Auto-Rotate Mode
NTAR = 1 = > Fixed Mode
Controls the data bus mode of operation.
T16N8 = => e-Bit Bus Mode
T16N8 1 => 16-Bit Bus Mode
At reset, all MCTL bits except COUTD, are reset to 0.
COUTD is set to 1.
3.11 OCASN - OUTPUT CLOCK
ASSIGNMENT REGISTER (R17)
Used only in the 8-bit Bus Mode. The four least significant
bits of this register control the output clock assignments on
pins GO/IRO. . . . ,G3/IR6. lf any of these bits is set to 1, the
clock generated by either the H-Counter or the H+ L-Coun-
ter will be output to the corresponding pin. The four most
significant bits of OCASN are not used. At Reset the four
least significant bits are set to 0.
Note: The interrupt sensing mechanism on pins GO/IRO ..... GS/IRG is not
disabled when any of these pins is programmed as clock output.
Thus, to avoid spurious interrupts. the corresponding bits in register
IPS should also be set to zero.
3.12 CIPTR - COUNTER INTERRUPT
POINTER REGISTER (R18)
The CIPTR register tracks the assignment of counter out-
puts to interrupt positions. A bit map of this register is shown
below.
dlziilil
Where: HHHH = A 4-bit binary number identifying the
interrupt position assigned to the H-
Counter (or the H + L-COunter if the
counters are concatenated).
LLLL = A 4-bit binary number identifying the
interrupt position assigned to the L-
counter.
Note: Assignment of a counter output to an interrupt position also requires
control bits to be set in the CICTL register. It a counter output is
assig had to an interrupt position, external hardware interrupts at that
position are ignored.
At reset, all bits in the CIPTR are set to 1. (T his means both
counters are assigned to interrupt position 15.)
3.13 PDAT- PORT DATA REGISTER (R19)
Used only in the 8-bit Bus Mode. This register is used to
input or output data through any of the pins G0/
mo, . . . ,G7/lFt14 programmed as l/O ports by the IPS reg-
ister. Any pin programmed as an output delivers the data
written into PDAT. The input pins ignore it. Reading PDAT
provides the logical value of all l/O pins, INPUT and OUT-
3.14 IPS - INTERRUPT/PORT SELECT REGISTER (R20)
Used only in the 8-bit Bus Mode. This register controls the
function of the pins G0/lR0, . . . ,G7/IFl14. Each of these
pins is individually programmed as an I/O port, if the corre-
sponding bit of IPS is 0; as an interrupt source, it the cone-
sponding bit is 1. The assignment of the H-Counter output
to GO/IRO. . . . ,G3/IR6 by means of reg. OCASN overrides
the assignment to these pins as l/O ports or interrupt in-
At Reset, all the lPS bits are set to 1.
Note: Whenever a bit in the lPS register is set to zero, to program the
corresponding pin as an l/O port, any pending interrupt on the corre-
sponding interrupt position will be cleared.
3.15 PDIR - PORT DIRECTION REGISTER (R21)
Used only in the 8-bit Bus Mode. This register determines
the direction of any of the pins GO/IRO, . . . ,G7/IR14 pro-
grammed as l/O ports by the IPS register. A logic 1 indi-
cates an input, while a logic 0 indicates an output.
At Reset, all the PDIR bits are set to 1.
3.16 CCTL - COUNTER CONTROL REGISTER (R22)
The CCTL register controls the operating modes of the
counters. A bit map of CCTL is shown below.
7 6 5 4 3 2 1 O
[t-octoricrNraslcouTict:)uro)onuNricnuNLlcDcRHlcDcnr4
CCON Determines whether the counters are indepen-
dent or concatenated to form a single 32-bit
counter (H+ L-Counter). If a 32-bit counter is
selected, the bits corresponding to the H-
Ol'ZOZZSSN
NS32202-10
3.0 Architectural Description (Continued)
Counter will control the H + L-Counter, while
the bits corresponding to the L-Counter are not
CCON = 0 = > Two 16-bit Counters
CCON = 1 = > One 32-bit Counter
Determines whether the external clock is
prescaled or not.
CFNPS = 0 = > Clock Prescaled (divided by 4)
CFNPS = = > Clock Not Prescaied.
COUT1 8
COUTO These bits are effective only when the COUT/
SCIN pin is programmed as an OUTPUT
(COUTD bit in reg. MCTL is 0). Their logic lev-
els are decoded to provide different outputs for
COUT/SCIN, as detailed in the table below:
COUT1 COUTO COUT/SCIN Output Signal
0 0 Internal Sampling Oscillator
0 1 Zero Detect Of L-Counter
1 0 Zero Detect Of H-Counter
1 1 Zero Detect Of H + L-Counter'
‘It the H- and L-Counters are not concatenated and
COUT1/COUTO are both I, the COUT/SCIN pin is active
when either counter reaches zero.
Determines the state of either the H-Counter or
the H+L-Counter, depending upon the status
of CCON.
CFtUNH = o = > H-Counter or H+L-Counter
Halted
CRUNH = 1 = > H-Counter or H + L-Counter
Running
Effective only when CCON = 0. This bit deter-
mines whether the L-Counter is running or halt.
CRUNL = 0 = > L-Counter Halted
CRUNL = = > L-counter Running
Effective only when CRUNH = 0 (Counter Halt-
ed). This bit is the single cycle decrement sig-
nal for either the H-Counter or the H + L-Coun-
CDCRH = 0 => No Effect
CDCRH = 1 = > Decrement H-Counter or
H + L-Counter
Effective only when CRUNL = O and CCON =
0. This bit is the single cycle decrement signal
for the L-Counter.
CDCFtL = 0 = > No Effect
CDCRL = 1 = > Decrement L-Counter
Note: The bits CDCRL and CDCRH are set when a logic 1 is written into
them, but, they are automatically cleared after the end ot the write
operation. TNs is needed to accomplish the decrement operation.
Therefore, these bite always contain 0 when read.
Reset does not affect the CCTL bits.
3.17 CICTL - COUNTER INTERRUPT
CONTROL REGISTER (R23)
The CICTL register controls the counter interrupts and rec-
ords counter interrupt status. Interrupts can be generated
from either of the 16-bit counters. When the counters are
concatenated, the interrupt control is through the H-Counter
control bits. In this case the CIEL bit should be set to zero to
avoid spurious interrupts from the L-Counter. A bit map of
the CICTL register is shown following.
7 6 5 4 3 2 1 0
IBERH I CIRH I CIEH [WENH I 05m GIRL] CIEL] wENLj
H-Counter Error Flag. This bit is set (1) when a
second interrupt request from the H-Counter
(or H+L-Counter) occurs before the first re-
quest is acknowledged.
H-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the H-Counter (or
H+L-Counter). It is automatically reset when
the interrupt is acknowledged.
H-Counter Interrupt Enable. When it is set, the
H-Counter (or H+L-Counter) interrupt is en-
abted.
H-Counter Control Write Enable. When WEHN
is set (I), bits CERH, CIRH, and CIEH can be
written.
L-Counter Error Flag. This bit is set (1) when a
second interrupt request from the L-Counter
occurs before the first request is acknowl-
edged.
L-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the L-Counter. It is
automatically reset when the interrupt is ac-
knowledged.
L-Counter Interrupt Enable. When it is set (I),
the L-Counter interrupt is enabled.
L-Counter Control Write Enable. When WENL
is set (1), bits CERL, CIHL, and ClEL can be
written.
Note: Setting the write enable bits (WENH or WENL) and writing any of the
other CICTL bits are concurrent operations. That is, the ICU will ig-
nore any attempt to alter CICTL bits it the proper write enable bit is
not set in the data byte.
At reset, all CICTL bits are set to o. However, if the counters
are running, the bits CIRL, CERL, CIRH and CEFtH may be
set again after the reset signal is rem0ved.
3.18 LCSV/HCSV - L-COUNTER STARTING VALUE/
H-COUNTER STARTING VALUE REGISTERS
(R24, R25, R26, AND R27)
The LCSV and HCSV registers store the start values for the
L-Counter and H-Counter, respectively. Each time a counter
reaches zero. the start value is automatically reloaded from
either LCSV or HCSV, one clock cycle after zero count is
reached. Loading LCSV or HCSV from the CPU must be
synchronized to avoid writing the registers while the reload-
ing of the counters is occurring. One method is to halt the
counters while the registers are loaded.
When the 16-bit counters are concatenated, the LCSV and
HCSV registers hold the 32-bit start count, with the least
significant byte in R24 and the most significant byte in R27.
3.19 LCCV/HCCV - L-COUNTER CURRENT VALUE/
H-COUNTER CURRENT VALUE REGISTERS
(R28, R29, RM, AND R31)
The LCCV and HCCV registers hold the current value of the
counters. if the CFRZ bit in the MCTL register is reset (O),
these registers are updated on each clock cycle with the
current value of the counters. LCCV and HCCV can be read
only when the counter readings are frozen (CFRZ bit in the
3.0 Architectural Description (Continued)
CF.) 0
mmnuzs mm
LEAVING mum '0
an IT LOGIC 1
mu commas
av ammo m
m cnum. mo mum no
cnmm m ocu
KER- cctc msam
no mmmm csnc
vs: IMTIAutE WCT,
rpm, m
INITIALIZE
Lew, MW I
um cum INITIAUZE ms
wan: counrsn's
manna muss
mo LCCV mo m
uccv T0 avom
Lt91tl mum
counrs
ms! courn w
mmmzz m um T0
CICVL mama comm.
rm " m oumt
w: mu EMILE ms
Imam mtmun
Mn smruua cum
nus uooe
couums
mumuzz um?
" RM, 0cm.
5 mm aUms
" am am
CLEAR CIUNLAND/Ol
ISRV, csac cnuun m m. cm
l F-----
INITIALIlE MM
TL/EE/5117-15
FIGURE 3-3. Recommended lCU’s lnltlallzatlon Sequence
Ol'ZOZZSSN
NS32202-10
3.0 Architectural
Description (Continued)
MCTL register is I). They can be written only when the
counters are halted (CRUNL and/or CRUNH bits in the
CCTL register are O). This last feature allows new initial
count values to be loaded immediately into the counters,
and can be used during initialization to avoid long initial
counts.
When the 16-bit counters are concatenated. the LCCV and
HCCV registers hold the 32-bit current value, with the least
significant byte in R28 and the most significant byte in R31.
3.20 REGISTER INITIALIZATION
Figure 3-3 shows a recommended initialization procedure
for the lCU that sets up all the ICU registers for proper oper-
ation.
4.0 Device Specifications
4.1 NS32202 PIN DESCRIPTIONS
4.1.1 Power Supply
Power (Vcc): + 5V DC Supply
Ground (GND): Power Supply Return
4.1.2 Input Signals
Reset (W): Active low. This signal initializes the ICU, (T he
ICU initializes to the 8-bit bus mode.)
Chip Select (E): Active low. This signal enables the ICU to
respond to address, data, and control signals from the CPU.
Addresses (A0 through A4): Address lines used to select
the ICU internal registers for read/write operations.
High Byte Enable (m): Active low. Enables data trans-
ters on the most-significant byte of the Data Bus. if the ICU
is in the 8-bit Bus Mode, this signal is not used and should
be connected to either GND or VCC-
Read trTr5y Active low. Enables data to be read from the
ICU's internal registers.
Write film).. Active low. Enables data to be written into the
ICU's internal registers.
Status (ST1): Status signal from the CPU. When the Hard-
ware Vector Register is read, this signal differentiates an
INTA cycle from an RETI cycle. If ST1 =0 the cu initiates
an INTA cycle. If ST1 =1 an RETl cycle will result.
Interrupt Requests ttRt, IR3.. ., IR15): These eight in-
puts are used for hardware interrupts. Each may be individu-
ally triggered in one of tour modes: Rising Edge, Falling
Edge, Low Level, or High Level.
Counter Clock (CLK): External clock signal to drive the ICU
internal counters.
4.1.3 Output Signals
Interrupt Output (m: Active low. This signal indicates
that an interrupt is pending.
4.1.4 lnput/Output Signals
Data Bus 0-7 (D0 through D7): Eight low-order data bus
lines used in both 8-bit and 16-bit bus modes.
General Purpose vo Llnes (GD/IRO, Gt/IR2, . . . ,G'I/
IR14): These pins are the high-order data bits when the ICU
is in the 16-bit bus mode. When the ICU is in the 8-bit bus
mode, each of these can be individually assigned one of the
following functions:
. Additional Hardware
. General Purpose Data Input
. General Purpose Data Output
0 Clock Output from H-Counter (Pins G0/IRO through
G3/IR6 only)
It should be noted that, for maximum flexibility in assigning
interrupt priorities, the interrupt positions corresponding to
pins GO/IRO, . . . ,G7/IR14 and IR1,...,IR15 are inter-
leaved.
Interrupt Input (IRO through
Counter or Oscillator Output/Sampllng Clock Input
(COUT/SCIN): As an output, this pin provides either a clock
signal generated by the ICU internal oscillator, or a zero
detect signal from one or both of the ICU counters. As an
input, it is used for an external clock. to override the internal
oscillator used for interrupt sampling. This is done only for
testing purposes.
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ty'C to + 70'C
Storage Temperature --65''C to + 150''C
All Input or Output Voltages with
Respect to GND -0.5V to + 7.0V
Power Dissipation 1.5 Watt
4.3 ELECTRICAL CHARACTERISTICS
TA = O'' to 70'C, Vcc = +5v d: 5%, GND = OV
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
Symbol Parameter Conditions Min Typ Max Unlts
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2 mA 0.45 V
VOH Output High Voltage loH = -400 pA 2.4 V
IL Leakage Current 0.4 s VIN s vcc -20 20 A
(Output and IIO Pins in TRI-STATE/input mode) p.
I. Input Load Current Vin = 0 to V00 --20 20 pA
ICC PowerSupply Current lam = 0, T = ty'C 300 mA
Connection Diagram
Mu- 1 co --ttt
gif--. t n --llit3
'rt---, 3 " --IMt
o,iii-) 4 " --llt9
tl8ntttt-e s M u—m
$Vtlit8- 5 " L-iii;
M/ilu-- 7 M e-tit'
t13ftft8- a " '--llt,
ttttttu--, ' "fl" " km
m/ttte-- m u M --iRi
ammo“ " 30 ---tli
ot-- " N '--tbut/8th,
- 13 a '--m
06-1 " " --m
- " N ---M
tu--, 16 ts = n
tit-- " " - "
m--- n t3 w-ht
'o-) " " - An
MD to " ~53
Top Vlew TL/EE/5117-3
Order Number N332202D-6, N632202D-10
See NS Package Number D406
FIGURE 4-1
Ol'ZOZZSSN
NS32202-10
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
4.4.1 Deflnltlons
All the timing specifications given in this section refer to
0.8V or 2.0V on the input and output signals as illustrated in
Figure 1, unless sptsaTcally Mated otherwise.
" TEST FONTS TEST POINTS “1X
TL/EE/5117-16
FIGURE 4-2. Tlmlng Speelfleatlon Standard
4.4.1.1 Tlmlng Tables
Attttrevlatlttrta..
LE.-ltsading edge
T.E,--trailing edge
RE.-rising edge
Fe-falling edge
Symbol Flgure Description Reference/Condltions "$220240 Units
Min Max
READ CYCLE
tAhRDia 4-3 Address Hold Time After W TE. 10 ns
tAsRDa 4-3 Address Setup Time Before ATf LE. 35 ns
tCShRDia 4..3 t% Hold Time After W T.E. 15 ns
tCSsnDa 4-3 c-s' Setup Time Before AT5 LE. 30 ns
chRDia 4-3 Data Hold Time After R_D TE. 5 50 ns
tRDaDv 4-3 Data Valid After AT L.E. 150 ns
mm 4-3 R-D Pulse Width At 0.8V (Both Edges) 160 ns
tSSRDa 4-3 ST1 Setup Time Before ITD- LE. 35 ns
tShRDia 4-3 ST1 Hold Time After W T.E. - 30 ns
WRITE CYCLE
tAhWRia 4-4 Address Hold Time After W T.E. 10 ns
IASWRa 4-4 Address Setup Time Before W LE. 35 ns
tcshwnia 4-4 .C-S Hold Time After W TE. 15 ns
logswna 4-4 tTS- Setup Time Before WTI LE. 30 ns
chwgia 4-4 Data Hold Time After i'lim T.E. 10 ns
tDszia 4-4 Data Setup Time Before WA TE. 70 ns
tWRiapf 4-4 Port Output Floating After WA' T.E. (T o PDIR) 200 ns
tWRiaPv 4-4 Port Output Valid After W-R T.E. 200 ns
twnw 4-4 WA Pulse Width At 0.8V (Both Edges) 160 ns
4.0 Device Specifications (Continued)
4.4.1.1 Tlmlng Tables (Continued)
Symbol Figure Destrrlptlon Reference/Conditions NS32202-t0 Units
Mln I Max
OTHER TIMINGS
tcoun 4-8 Internal Sampling Clock At 0.8V (Both Edges) 50 ns
Low Time
tCOUTp 4-8 Internal Sampling Clock Period 400 ns
tSCINh 4-7 External Sampling Clock High Time At 2.0V (Both Edges) 100 ns
tscml 4-7 External Sampling Clock Low Time At 0.8V (Both Edges) 100 ns
tscho 4-7 External Sampling Clock Period 800 ns
ton 4-9 External Clock High Time At 2.0V (Both Edges) 100 n s
(Without Prescaler)
tChp 4-9 External Clock High Time At2.0V (Both Edges) 40 ns
(With Prescaler)
tel 4-9 External Clock Low Time At 0.8V (Both Edges) 100 n s
(Without Prescaler)
telp 4-9 External Clock Low Time At 0.8V (Both Edges) 40 ns
(With Prescaler)
to, 4-9 External Clock Period
(Without Prescaler) 400 ns
ttow 4-9 External Clock Period
(With Prescaler) 100 ns
tGCOUTI 4-9 Counter Output Transition Delay After CLK FE. 300 ns
tCOUTw 4-9 Counter Output Pulse At 0.8V (Both Edges) 50 ns
Width in Pulsed Form
tACKIR 4-5 Interrupt Request Delay After Previous Interrupt 500 n S
Acknowledge
tlmd 4-5 W Output Delay After Interrupt
Request Active 800 ns
tmw 4-5 Interrupt Request Pulse At 0.8V (Both Edges) 50 ns
Width in Edge Trigger
tRSTw RST Pulse Width At 0.8V (Both Edges) 400 ns
4.4.1.2 Tlmlng Diagrams
ADDRESS K
- u",,--: lum-
M -y 1cm- --utttae-
two: mo. ttm-
[ ie""-'""""""'"-""""
mm Iome-
om nus om VAUO
TL/EE/5117-17
FIGURE 4-3. READ/INTA Cycle
Ol-‘ZOZZSSN
NS32202-10
4.0 Device Specifications (Continued)
ADDRESS 1 K
---tewm--- -M-
c'''-" C""""
um M, -ta-,--l
Ioum -.tt--
o,a,gs"'"-'"-""'"""" X MYAVAUD -.t...-
__....__.____.... ---
----t----
OUYPUI NO
TL/EE/511r-18
FIGURE 4-4. Write Cycle
n N _ I
tuna ' Um
tr'"""""-"'""
ittf (mu) N 7
TL/EE/5117-19
FIGURE 4-5. Interrupt Tlmlng In Edge Triggering Mode
‘6 ilf1TA) "sc,..-...,.,,.....]"'
TL/EE/5117-20
FIGURE 4-6. Interrupt Tlmlng In Level Triggering Mode
4.0 Device Specifications (Continued)
TL/EE/5117-21
Note.. Interrupts are sampled on the rising edge of CLK.
FIGURE 4-7. External interrupt-Sampling-Clock to be Provlded at Pln COUTISCIN When In Teat Mode
lam tram
w l / "ssl"-"'"-""'',]"-
FIGURE 4-8. Internal Interrupt-Sampllng-Clock Provlded at Pln COUT/SCIN
TL/EE/5117-22
ter tht hm»
m_/_\_/ _/_\_/_\__
tatam--
COUNTER OUTPUT
IN PULSED FORM
comma oumur m
m 8thWIt --
TL/EE/5117-23
FIGURE 4-9. Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT/SCIN or
GtUR0,...,G3/R6, In Both Pulsed Form and Square Waveform
OL'ZOZZSSN
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NS32202D-6 - product/n532202d-6?HQS=T|-nu|I-nu|I-dscatalog-df-pf-null-wwe
NS32202D-10 - product/n332202d-10?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
