NMC9346 ,1024 Bit Serial Electrically Erasable Programmable MemoryBlock Diagram
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NMC9346N ,+6 to -0.3V; 1024-bit serial electrically erasable programmable memoryFeatures
The NM09346 Is a 1024-bit non-volatile, sequential I Designed for 40,000 erasé/write cy ..
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NMD050505SC , Isolated 1W Twin Output DC/DC Converters
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NMC9346
1024 Bit Serial Electrically Erasable Programmable Memory
NATL SENICOND {MEMORY} LUE I) [IESULLE'E DUELEEE n [I
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[ Semiconductor
T-46-13-27
NMC9346 1024-Bit Serial Electrically Erasable
Programmable Memory
General Description
The NM09346 is a 1024-bit non-volatile, sequential
EZPROM, fabricated using advanced N-channel EZPROM
technology. It is an external memory with the 1024 blts of
read/write memory divided Into 64 registers of 18 bits each.
Each register can be serially read or written by a COP4OO
controller, or a standard microprocessor. Written Informa-
tion ls stored In a floating gate cell until updated by an erase
and write cycle. The NM09346 has been designed for appli-
cations requiring up to 4 x 104 erase/write cycles per regis-
ter. A power-down mode ls provided by cs to reduce power
consumption by 75 percent.
Features
I 40,000 erase/wrlte cycles typical
I 10 year data retention
ll Low cost
I Single supply read/write/erase operations (5Vf. 10%)
I TTL compatible
I 64 x 16 serial read/write memory
I MICROWIRETM compatible serial I/O
I Simple Interfacing
ll Low standby power
I Non-volatile erase and write
I Reliable floating gate technology
I Self-timed programming cycle
I Device status signal during programming
Block Diagram
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Pln Names
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
Vcc Power Supply
GND Ground
NC No Connection
TL/D/9205-t
QVSGOWN
NM09346
NATL SEMICOND {MEMORY} 10E I) DESULLEE UUELEEB Cl fl
. T-46-13-27
Connection Diagrams
14-Pln B-Nn
DuaI-In-Llne Package (N) SO Package (M) so Package (MB)
IIS-it U '-1lu1 “-1 "-" cs-t V 8-ytlc
"- , 1 w-tie tlt- 2 tr-tts Sht- 2 7 -tlo
'le- ' 12 m-tttl
ill-' '--" ttit--' tt-ktr 01-3 6-tl0
th-- a 10 -" tro- 4 5 -tplt)
tgl---, I ' -tltllt tro- I I -tltitt rup/szos-1
NI:- T I -titl Top View
To View TUDN20S-2 See NS Package Number MOBA
S NS P p momma Device Marklng: 9346,
ee ackage Number NOSE T up View 9348E, 9346M
See NS Package Number M148
Devlce Marklng:9346M14
9346EM14, 9346MMt4
Ordering Information
Commercial Temp. Range
(0'C to + 70°C)
Extended Temp. Range
(-4tt'C to + 85°C)
Military Temp. Range
i-SST to + 125°C)
Order Number Order Number Order Number
NM09346N NM09346EN NMC9346MN
NM09346M NM09346EM NM69346MM
NM09346M8 NM09346EM8 NMC9346MM8
Absolute Maximum Ratings Operating Conditions
If Mllttary/Aerospaee specified devlces are required, Ambient Storage Temperatures
contact the National Semiconductor Sales omce/ NM69346 Wt? to + 70'0
Dlstrlbutors tor availablllty and tepetMeatlona. NM09346E -40''C to +85'C
Voltage Relative to GND + 6V to -0.3V NMC9346M -65'C to +125"?
Ambient Storage Temperature -65T to + 125''C Positive Supply Voltage 4.5V to 5.5V
Lead Temperature
(Soldering, 10 seconds) 300°C
ESD rating. 2000V
DC and AC Electrical Characteristics vcc ''' 6V h10% unless otherwise specified
Symbol Parameter Part Number Condmons Min Max Units
Vcc Operating Voltage NMC9346, NM09348E 4 ti 5 ti V
NMC9346M . .
l Operating Current NMC9346 Vcc=5.5V. CS=1, SK=1 12 mA
CO1 Erase/Write Operating Current Vcc = 5.5V 12 mA
Operating Current NM09346E Vcc=5.5V. CS-- LSK=1 14 mA
Erase/Write Operatlng Current Vcc = 5.5V 14 mA
Operating Current NM09346M Veg;m 5.5V,CS=1. SK=1 15 mA
Erase/Write Operating Current Vcc" 5.5V " mA
NATL SENICOND {MEMORY} LDE I)
JESULLEE 0013];be a fl
====-=====--t-r-----
T-46-13-27 - '
DC and AC Electrical Characteristics Vcc = 5V , 10% unless otherwise stmcltfet' (Continued) co
Symbol Parameter Part Number Conditions Min Max Units g
lccz Standby Current NM09346 Vcc=5.5V, cs= 0 mA trt
Standby Current NMC9346E Vcc-- 5.5V, CS=0 4 mA
Standby Current NM09346M' Vccsa 5.5V, cs = 0 5 mA
Input Voltage Levels NM09346, NM09346E,
l/L NM09346M -0.1 0.8 V
VIH 2.0 Vcc + 1 v
Output Voltage Levels NM09346. NMG9346E,
VOL NMC9346M |0L=2.1 tttA 0.4 V
Von KOH-- -400 pA 2.4 v
IL) Input Leakage Current NM09346. NM09346E. VIN = 6.5V 10 M
NM09346M
Ito Output Leakage Current NM09346, NMC9346E, VOUT .--. 5.5V, GS = o 10 pLA
NM09346M
SK Frequency MM09346 0 250 kHz
tSKH SK High Time (Note 2) 1 p.s
tSKL SK Low Time (Note 2) 1 us
SK Frequency MMC9346E 0 kHz
SK High Time (Note 2) 1 250 p.s
SK Low Time (Note 2) 1 [LS
SK Frequency MM09346M 0 kHz
SK High T1me(Note 2) 2 200 “5
SK Low Time (Note 2) 1 us
Inputs NMC9346, NMC9346E,
tcss cs NMC9346M 0.2 11.5
tCSH 0 [us
tas DI 0.4 p.s
tDlH 0.4 [J.S
Output NM09346, cL= 100 pF
tpdl DO NM09346E, Voc-- o.av, VOH = 2.0V 2 [1.5
1de NM09346M v.._= 0.45v. VIH = 2.40V 2 p5
tE/w Self-Tlmed Program Cycle NM09346 10 ms
Self-Timed Program Cycle NMC9346E 10 ms
Self-Timed Program Cycle NM69346M 12 ms
tas Min cs Low Time (Note 3) NM09346. NM09346E, 1 s
NMC9346M "
tsv Rising Edge of cs to Status Valid NM09346. NMC9346E, CL--- 100 pF 1 s
NM09346M "
t0H. 11H Falling Edge of CS to DO TRl-STATEo NMC9346, NM09346E. 0 4 s
NMC9346M . ll
Endurance NM09346. NM09346E. Data Changes Typical Cycles
NM09346M per Bit 40,000
Nora 1: Stress above those listed under "Absolute Maximum Hallngs" may cause permanent damage to ma device. This is a stress rating only and ttmMirmal
operation of the devlca at these or any other conditions above those indicated ln (he operational sections of the specification Is not implied. Exposure to absolute
maximum tating conditions for extended periods may affect device reliability.
Note P. The SK frequency spec. specifies a minimum SK clock period of 4 us. therefore In an SK clock cycle tsitrt F ISKL mustlm greater than or equal to 4 P5-
e.g.. it 15th = t p5 then the minimum tsm = 3 93 In order to meal the SK frequency specification.
Nola 3: CS must be brought low for a mlnImum ot 1 yrs (tos) between consecmive instruclian cycles.
‘Thruaul this table "M" Iefers to temperature range (-65t to +125'C). not package.
NM69346
NATL SEMICOND {MEMORY} LEIE I) DESDLLEE UUELEES H fl
Functional Description
The NM69348 is a small peripheral memory Intended for
use with COPSTM controllers and other nonvolatile memory
applications. The NM09346 Is organized as sixty-tour regis-
ters and each register is sixteen bits wide. The input and
output pins are controlled by separate serial formats, Seven
9-bit instructions can be executed. The instmction format
has a logical '1' as a start hit. two bite as an op code. and six
bits of address. The programming cycle is malf-timed, with
the data out (DO) pin indicating the ready/busy status of the
chip. The on-chip programming voltage generator allows the
user to use a single power supply (Vcc). it only generates
high voltage during the programming modes (mite, erase,
chip erase, chip write) to prevent spurious programming dur.
ing other modes, The DO pin is valid as data out during the
read mode, and it Initiated, as e ready/busy status indicator
during a programming cycle. During all other modes the DO
pln Is in TRI-STATE, eliminating bus contention.
The read instruction is the only instruction which outputs
senai data on the DO pin. After a read instruction ls re-
ceived, the Instruction and address are decoded. followed
by data transfer from the memory register Into a 16-bit seri-
ei-out shift register. A dummy bit (logical '0') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK ciock.
ERASE/WRITE ENABLE AND DISABLE
When Va: Is applied to the part It powers up In the program-
ming disable (EWDS) state, programming must be preceded
by a programming enable (EWEN) instruction. Programming
remains enabled until a programming disable (EWDS) in.
struction is executed or V00 Is removed tram the part. The
programming enable instruction (EWEN) ls needed to keep
the part in the enable state it the power supply (Vcc) noise
tails below operating range. The programming disabte in.
structlon Is provided to protect against accidental data dis-
turb. Execution of a read instruction is independent of both
EWEN and EWDS instructions.
ERASE (Note 4)
Like most E2PROMs, the register must first be erased (all
bits set to logical 'I') before the register can be written (cer-
instruction Set for NMC9346
T-46-13-27
tain bits set to logical 'O'), After an erase instniction is Input,
GS is dropped low. This falling edge of CS determines the
start of the seit-timed programming cycle. it 08 Is brought
high subsequently (after observing the tcs spasliieatitml,
the DO pin wiil indicate the reedy/busy status of the chip.
The DO pin will go low it the chip is still programming. The
DO pin will go high when all bits of the register at the M.
dress speelfied In the instruction have been set to a logical
'1'. The part Is now ready for the next instruction sequence.
WHITE (Note 4)
The write Instruction is followed by 16 bits of data to be
written Into the specified address. After the last bit at data
(Do) Is put on the data In (DI) pin cs must be brought low
before the next rising edge of the SK clock. This tailing edge
of CS initiates the seit-timed programming cycle. Like all
programming modes, DO indicates the ready/busy status of
the chip it CS ls brought high after a minimum of 1 HS (log).
DO=logical 'ty Indicates that programming is still In prog-
ress. DO-Ioglcei '1' indicates that the register at the ad.
dress tspeclfied In the instruction has been written with the
data pattern tspecified in the instruction and the part is ready
for another instruction. The register to be written Into must
have been previously erased.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease ot programming.
Erasing the chip means that all registers in the memory ar-
ray have each bit set to a logical '1'. Each register is then
ready for a write instruction. The chip erase cycle is identical
to the erase cycle except for the different op code.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is Identical to the write cycle except tor
the different op code. Ail registers are simultaneously writ.
ten with the data pattern specified in the instruction.
Note 4: During a programming mode (write, erase. chip erase. chip write).
SK ciock is only needed white the actual instruction. Le, start bit, op
code. address and data, is being Input. it can remain deactivated
during the seii-timed programming cycle and status check.
instruction SB Op Code Address Data Comment.
READ 1 10 A5A4A3A2A1A0 Read Register A5A4A3A2AIA0
WRITE 1 Ot A5A4A3A2AIA0 tM 5-00 Write Register A5A4A3A2A1A0
ERASE 1 It A5A4A3A2A1Ao Erase RegisterA5A4AaA2A1A0
EWEN 1 00 11mm Erase/Write Enable
EWDS l 00 00W Erase/Write Disable
ERAL 1 00 10mm Erase All Registers
WRAL 1 00 Ohootx D16-DO Write M Registers
NM69346 has 7 instructions as shown. Note that the MSB of any given instruction is e“1"endls viewed as a start bit in the
Interface sequence. The next 8 bits carry the op code and the 8-bit address tor t of M, 16-bit registers.
NATL SENICOND {MEMORY} 10E I) DESULLEE ClClia1lagi, E: [I
T-46-13-27
Timing Diagrams
Synchronous Data Timing
l 4PS* I
SK "--tskH tSKL
ht. L----.
tms l tins, tDIH_
th4PS th4PS th4YS
tcss tcw
0.2 [1.5 0.0 Ms
'Thls is the minimum SK period (5 pa tor NMCOGOGM)
TLID/9205-4
SPSEOHN
NM09346
Instruction Timing
m J: \ n/1‘uMnx-FYMXmst
Timing Diagrams (Continued)
Im-SYITE
T-46-13-27
HAILEI"
TL/D/BZOS-S
NATL SEMICOND {MEMORY} ICE I) [IESULLEE UUELEE? ll ll
NATL SEMICOND {MEMORY} lUE I) DESULLEE UUELEEE U I]
T-46-13-27 --.-.--
Timing Diagrams (Continued)
TLlD/9205-6
3k 7f—‘mm
J-” ammo: swan
1% mm: mum
1 1 IYASXMXAJX Xu\ !
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QVSGOWN
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
NMC9346 - product/nm09346?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
