NMC9307EN ,Vcc=5V+/-10%, 256-bit serial electrically erasable programmable memoryElectrical Characteristics
Lead Temperature (Soldering, 10 sec.) 300°C
ESD Rating 2000V
Note ..
NMC9346 ,1024 Bit Serial Electrically Erasable Programmable MemoryBlock Diagram
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NMC9346EN ,+6 to -0.3V; 1024-bit serial electrically erasable programmable memoryBlock Diagram
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NMC9346N ,+6 to -0.3V; 1024-bit serial electrically erasable programmable memoryFeatures
The NM09346 Is a 1024-bit non-volatile, sequential I Designed for 40,000 erasé/write cy ..
NMC93C56 ,Electrically Erasable Programmable MemoriesBlock Diagram
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REGISTER
ADDRESS
REGiSTER
DECODER
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NMD050505SC , Isolated 1W Twin Output DC/DC Converters
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
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OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
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NMC9307EN
Vcc=5V+/-10%, 256-bit serial electrically erasable programmable memory
NMC9307
I National
Semiconductor
NMC9307 256-Bit Serial Electrically Erasable
Programmable Memory
General Description
The NMC9307 is a 256-bit non-volatile sequential access
memory fabricated using advanced floating gate N-channel
EZPROM technology. It is a peripheral memory designed for
data storage and/or timing and is accessed via the simple
MICROWIRETM serial interface. The device contains 256
bits of read/write memory divided into 16 registers of 16 bits
each. Each register can be serially read or written by a
COP400 series controller. Bulk programming instructions
(chip erase, chip write) can be enabled or disabled by the
user for enhanced data protection. Written information is
stored in a floating gate cell with at least 10 years data
retention and can be updated by an erase-write cycle. The
NMC9307 has been designed to meet applications requiring
up to 40,000 erase/write cycles per register. A power down
mode reduces power consumption by 70 percent.
Features
Low cost
40,000 erase/write cycles
10 year data retention
Single supply operation (5We 10%)
TTL compatible
16X " serial read/write memory
MICROWIRE compatible serial I/O
Compatible with COP400 processors
Low standby power
Non-volatile erase and write
Reliable floating gate technology
Block and Connection Diagrams
VP? VBC
GENERA'IOR
E’PRO M
c:com 255 ms
1/18 [stm
ADDRESS
LMCHES " AMPS
nscusma
(11 ms; tut
MSTRUCTION
IEGISI’ER cut
(9 BITS)
INSTRUCYION
CONTROL
BENEMYDRS
TL/D/9204-1
Dual-in-Line Package (N)
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TL/D/9204-2
Top Vlew
See NS Package Number N08E
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TL/D/9204-3
Top Vlew
See NS Package Number M148
Note: Contact factory for $08 availability.
Pln Names
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
Vcc Power Supply
GND Ground
Absolute Maximum Ratings
If Milltary/Aerospace specified devlces are required,
please contact the National Semlconductor Sales
Offitte/Dltttrlbutttrs for avallablllty and trpeeltleatlona.
Voltage Relative to GND + 6V to - 0.3V
Ambient Operating Temperature
NMC9307
NMC9307E
Ambient Storage Temperature
ty'C to + 70°C
-40°C to + 85°C
-65''C to + 125''C
Electrical Characteristics
Lead Temperature (Soldering, 10 sec.) 300°C
ESD Rating 2000V
Note: Stresses above those listed under "Absolute Maxi-
mum Ratings " may cause permanent damage to the device.
This is a stress rating only and functional operation of the
de vice at those or any other conditions above those indicat-
ed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Parameter Conditions Part No Min Max Units
Operating Voltage (Vcc) 4.5 5.5 V
Operating Current ('CC1) Vcc = 5.5V, cs = 1 9307 10 m A
9307E 12
Standby Current (lccz) vcc= 5.5V, cs = o 9307 3 mA
9307E 4
Input Voltage Levels
VI. - 0.1 0.8 V
l/m 2.0 Vcc + 1 V
Output Voltage Levels
VOL IOL--- 2.1 mA 0.4 V
VOH lOH = -400 FLA 2.4 V
Input Leakage Current VIN = 5.5V 10 FA
Input Leakage Current VIN= 0 to 5.5V "
PINS1,2,3 :10 WA
PIN 6 i 50 “A
Output Leakage Current VOUT = 5.5V, cs = 0 10 p
SK Frequency 0 250 kHz
SK HIGH TIME tSKH (Note 2) 1 us
SK LOW TIME tSKL (Note 2) 1 p5
Input Set-Up and Hold Times
CS toss 0.2 p.s
tCSH 0 P5
DI tDIS 0.4 ps
tom 0.4 p.s
Output Delay CL = 100 pF
DO tpm VOL = 0.8V, Vor, = 2.0V 2 us
tPDO " = 0.45V, " = 2.40V 2 MS
Erase/Write Pulse Width (tE/w) (Note I) 10 30 ms
CS Low Time (tog) (Note 3) 1 ps
Endurance Number of Data .
Changes per Bit 40, 000 Typical
Note 1: tan” measured to rising edge of SK or cs, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 Ms, therefore in an SK clock cycle, ISKH + tSKL must be greater than or equal to 4 ws.
9.9. if tst = ms then the minimum 'SKH = 3 ps in order to meet the SK frequency specification.
Note 3: CS must be brought low for a minimum of 1 us (tcs) between consecutive instruction cycles.
ZOEGOWN
NMC9307
Instruction Set
Instruction SB Op Code Address Data Comments
READ o, 1 10xx A3A2A1A0 Read register A3A2A1A0
WRITE 0, 1 01xx A3A2A1A0 D15 - D0 Write register A3A2A1A0
ERASE o, 1 1 1xx A3A2A1A0 Erase register A3A2A1AO
EWEN 0, 1 0011 met Erase/write enable
EWDS 0, 1 0000 XXXX Erase/write disable
ERAL 0, 1 0010 XXXX Erase all registers
WRAL 0, 1 0001 m D15 - D0 Write all registers
The NMC9307 has 7 instructions as shown. Note that MSB of any given instruction is a "I" and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and the 4-bit address for 1 of 16, Ithtrit registers.
X is a dun't care state.
Functional Description
The NMG9307 is a small peripheral memory intended for
use with COPSTM controllers and other non-volatile memory
applications. The NMC9307 is organized as sixteen regis-
ters and each register is sixteen bits wide. The input and
output pins are controlled by separate serial formats. Seven
9-bit instructions can be executed. The instruction format
has a logical 'I' as a start bit, four bits as an op code, and
four bits of address. SK clock cycle is necessary after CS
equals logical "I" before the instruction can be loaded. The
on-chip programming-voltage generator allows the user to
use a single power supply (Vcc). Only during the read mode
is the serial output (D0) pin valid. During all other modes the
DO pin is in TRI-STATE', eliminating bus contention.
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is re-
ceived, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit seri-
aI-out shift register. A dummy bit (logical 'ty) precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
ERASE/WRITE ENABLE AND DISABLE
Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming disable instruction is provided to protect
against accidental data disturb. Execution of a READ in-
struction is independent of both EWEN and EWDS instruc-
tions.
ERASE (Note 4)
Like most E2PROMS, the register must first be erased (all
bits set to Is) before the register can be written (certain bits
set to Os). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to Is. When the erase/write
programming time (tE/w) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.
WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS fol-
lowing the instruction. The on-chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH. the programming cycle ends. All pro-
gramming modes should be ended with CS high for one SK
period, or followed by another instruction.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory ar-
ray have each bit set to a 1. Each register is then ready for a
WRITE instruction. The chip erase (ERAL) instruction is ig-
nored if the BPE pin is at VI, i.e., data is not changed.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle. except for
the different op code. All registers are simultaneously writ-
ten with the data pattern specified in the instruction.
The chip write (WRAL) instruction is ignored if the BPE pin is
at VlL. i.e., the array data is not changed.
Note 4: During a programming mode (write, erase. chip erase. chip write),
SK clock is only needed while the actual instruction, i.e., start bit, op code,
address and data, is being input. It can remain deactivated during the Erase/
Write pulse width (tE/w)
Timing Diagrams
Synchronous Data Timing
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NMC9307
'tglw measured to n'sing edge of SK or CS. whichever occurs last.
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Timing Diagrams (Continued)
TL/D/9204 —6
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NM09307
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This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NMC9307EM - product/nm09307em?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
NMC9307EN - product/nmc9307en?HQS=T|-nu|I-nulI-dscatalog-df-pf-null-wwe
NMC9307M - product/nmc9307m?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII—wwe
NMC9307N - product/nmc9307n?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI—wwe
